auich.c revision 1.17.4.1
1 /* $NetBSD: auich.c,v 1.17.4.1 2004/03/15 05:41:16 jmc Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 /* #define ICH_DEBUG */ 99 /* 100 * AC'97 audio found on Intel 810/820/440MX chipsets. 101 * http://developer.intel.com/design/chipsets/datashts/290655.htm 102 * http://developer.intel.com/design/chipsets/manuals/298028.htm 103 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 104 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 105 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 106 * AMD8111: 107 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 109 * 110 * TODO: 111 * - Add support for the microphone input. 112 */ 113 114 #include <sys/cdefs.h> 115 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.17.4.1 2004/03/15 05:41:16 jmc Exp $"); 116 117 #include <sys/param.h> 118 #include <sys/systm.h> 119 #include <sys/kernel.h> 120 #include <sys/malloc.h> 121 #include <sys/device.h> 122 #include <sys/fcntl.h> 123 #include <sys/proc.h> 124 125 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 126 127 #include <dev/pci/pcidevs.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/auichreg.h> 130 131 #include <sys/audioio.h> 132 #include <dev/audio_if.h> 133 #include <dev/mulaw.h> 134 #include <dev/auconv.h> 135 136 #include <machine/bus.h> 137 138 #include <dev/ic/ac97reg.h> 139 #include <dev/ic/ac97var.h> 140 141 struct auich_dma { 142 bus_dmamap_t map; 143 caddr_t addr; 144 bus_dma_segment_t segs[1]; 145 int nsegs; 146 size_t size; 147 struct auich_dma *next; 148 }; 149 150 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 151 #define KERNADDR(p) ((void *)((p)->addr)) 152 153 struct auich_cdata { 154 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 155 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 156 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 157 }; 158 159 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 160 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 161 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 162 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 163 164 struct auich_softc { 165 struct device sc_dev; 166 void *sc_ih; 167 168 audio_device_t sc_audev; 169 170 bus_space_tag_t iot; 171 bus_space_handle_t mix_ioh; 172 bus_space_handle_t aud_ioh; 173 bus_dma_tag_t dmat; 174 175 struct ac97_codec_if *codec_if; 176 struct ac97_host_if host_if; 177 178 /* DMA scatter-gather lists. */ 179 bus_dmamap_t sc_cddmamap; 180 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 181 182 struct auich_cdata *sc_cdata; 183 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 184 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 185 #define dmalist_mici sc_cdata->ic_dmalist_mici 186 187 int ptr_pcmo, 188 ptr_pcmi, 189 ptr_mici; 190 191 /* i/o buffer pointers */ 192 u_int32_t pcmo_start, pcmo_p, pcmo_end; 193 int pcmo_blksize, pcmo_fifoe; 194 195 u_int32_t pcmi_start, pcmi_p, pcmi_end; 196 int pcmi_blksize, pcmi_fifoe; 197 198 u_int32_t mici_start, mici_p, mici_end; 199 int mici_blksize, mici_fifoe; 200 201 struct auich_dma *sc_dmas; 202 203 int sc_fixed_rate; 204 int sc_ac97rate; 205 /* SiS 7012 hack */ 206 int sc_sample_size; 207 int sc_sts_reg; 208 209 void (*sc_pintr)(void *); 210 void *sc_parg; 211 212 void (*sc_rintr)(void *); 213 void *sc_rarg; 214 215 /* Power Management */ 216 void *sc_powerhook; 217 int sc_suspend; 218 u_int16_t ext_status; 219 }; 220 221 #define FIXED_RATE 48000 222 223 /* Debug */ 224 #ifdef AUDIO_DEBUG 225 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 226 int auich_debug = 0xfffe; 227 #define ICH_DEBUG_CODECIO 0x0001 228 #define ICH_DEBUG_DMA 0x0002 229 #define ICH_DEBUG_PARAM 0x0004 230 #else 231 #define DPRINTF(x,y) /* nothing */ 232 #endif 233 234 int auich_match(struct device *, struct cfdata *, void *); 235 void auich_attach(struct device *, struct device *, void *); 236 int auich_intr(void *); 237 238 const struct cfattach auich_ca = { 239 sizeof(struct auich_softc), auich_match, auich_attach 240 }; 241 242 int auich_open(void *, int); 243 void auich_close(void *); 244 int auich_query_encoding(void *, struct audio_encoding *); 245 int auich_set_params(void *, int, int, struct audio_params *, 246 struct audio_params *); 247 int auich_round_blocksize(void *, int); 248 int auich_halt_output(void *); 249 int auich_halt_input(void *); 250 int auich_getdev(void *, struct audio_device *); 251 int auich_set_port(void *, mixer_ctrl_t *); 252 int auich_get_port(void *, mixer_ctrl_t *); 253 int auich_query_devinfo(void *, mixer_devinfo_t *); 254 void *auich_allocm(void *, int, size_t, int, int); 255 void auich_freem(void *, void *, int); 256 size_t auich_round_buffersize(void *, int, size_t); 257 paddr_t auich_mappage(void *, void *, off_t, int); 258 int auich_get_props(void *); 259 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 260 void *, struct audio_params *); 261 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 262 void *, struct audio_params *); 263 264 int auich_alloc_cdata(struct auich_softc *); 265 266 int auich_allocmem(struct auich_softc *, size_t, size_t, 267 struct auich_dma *); 268 int auich_freemem(struct auich_softc *, struct auich_dma *); 269 270 void auich_powerhook(int, void *); 271 int auich_set_rate(struct auich_softc *, int, uint); 272 void auich_finish_attach(struct device *); 273 unsigned int auich_calibrate(struct auich_softc *); 274 275 276 struct audio_hw_if auich_hw_if = { 277 auich_open, 278 auich_close, 279 NULL, /* drain */ 280 auich_query_encoding, 281 auich_set_params, 282 auich_round_blocksize, 283 NULL, /* commit_setting */ 284 NULL, /* init_output */ 285 NULL, /* init_input */ 286 NULL, /* start_output */ 287 NULL, /* start_input */ 288 auich_halt_output, 289 auich_halt_input, 290 NULL, /* speaker_ctl */ 291 auich_getdev, 292 NULL, /* getfd */ 293 auich_set_port, 294 auich_get_port, 295 auich_query_devinfo, 296 auich_allocm, 297 auich_freem, 298 auich_round_buffersize, 299 auich_mappage, 300 auich_get_props, 301 auich_trigger_output, 302 auich_trigger_input, 303 NULL, /* dev_ioctl */ 304 }; 305 306 int auich_attach_codec(void *, struct ac97_codec_if *); 307 int auich_read_codec(void *, u_int8_t, u_int16_t *); 308 int auich_write_codec(void *, u_int8_t, u_int16_t); 309 void auich_reset_codec(void *); 310 311 static const struct auich_devtype { 312 int vendor; 313 int product; 314 const char *name; 315 const char *shortname; 316 } auich_devices[] = { 317 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 318 "i82801AA (ICH) AC-97 Audio", "ICH" }, 319 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 320 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 321 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 322 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 323 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 324 "i82440MX AC-97 Audio", "440MX" }, 325 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 326 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 327 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 328 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 329 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 330 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 331 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 332 "SiS 7012 AC-97 Audio", "SiS7012" }, 333 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 334 "nForce MCP AC-97 Audio", "nForce" }, 335 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 336 "nForce2 MCP-T AC-97 Audio", "nForce2" }, 337 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 338 "nForce3 MCP-T AC-97 Audio", "nForce3" }, 339 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 340 "AMD768 AC-97 Audio", "AMD768" }, 341 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 342 "AMD8111 AC-97 Audio", "AMD8111" }, 343 { 0, 0, 344 NULL, NULL }, 345 }; 346 347 static const struct auich_devtype * 348 auich_lookup(struct pci_attach_args *pa) 349 { 350 const struct auich_devtype *d; 351 352 for (d = auich_devices; d->name != NULL; d++) { 353 if (PCI_VENDOR(pa->pa_id) == d->vendor 354 && PCI_PRODUCT(pa->pa_id) == d->product) 355 return (d); 356 } 357 358 return (NULL); 359 } 360 361 int 362 auich_match(struct device *parent, struct cfdata *match, void *aux) 363 { 364 struct pci_attach_args *pa = aux; 365 366 if (auich_lookup(pa) != NULL) 367 return (1); 368 369 return (0); 370 } 371 372 void 373 auich_attach(struct device *parent, struct device *self, void *aux) 374 { 375 struct auich_softc *sc = (struct auich_softc *)self; 376 struct pci_attach_args *pa = aux; 377 pci_intr_handle_t ih; 378 bus_size_t mix_size, aud_size; 379 pcireg_t v; 380 const char *intrstr; 381 const struct auich_devtype *d; 382 u_int16_t ext_id, ext_status; 383 384 d = auich_lookup(pa); 385 if (d == NULL) 386 panic("auich_attach: impossible"); 387 388 printf(": %s\n", d->name); 389 390 if ((d->vendor == PCI_VENDOR_INTEL 391 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) 392 || (d->vendor == PCI_VENDOR_INTEL 393 && d->product == PCI_PRODUCT_INTEL_82801EB_AC)) { 394 /* 395 * Use native mode for ICH4/ICH5 396 */ 397 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 398 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 399 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 400 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 401 v | ICH_CFG_IOSE); 402 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 403 0, &sc->iot, &sc->mix_ioh, NULL, 404 &mix_size)) { 405 printf("%s: can't map codec i/o space\n", 406 sc->sc_dev.dv_xname); 407 return; 408 } 409 } 410 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 411 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 412 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 413 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 414 v | ICH_CFG_IOSE); 415 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 416 0, &sc->iot, &sc->aud_ioh, NULL, 417 &aud_size)) { 418 printf("%s: can't map device i/o space\n", 419 sc->sc_dev.dv_xname); 420 return; 421 } 422 } 423 } else { 424 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 425 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 426 printf("%s: can't map codec i/o space\n", 427 sc->sc_dev.dv_xname); 428 return; 429 } 430 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 431 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 432 printf("%s: can't map device i/o space\n", 433 sc->sc_dev.dv_xname); 434 return; 435 } 436 } 437 sc->dmat = pa->pa_dmat; 438 439 /* enable bus mastering */ 440 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 441 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 442 v | PCI_COMMAND_MASTER_ENABLE); 443 444 /* Map and establish the interrupt. */ 445 if (pci_intr_map(pa, &ih)) { 446 printf("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 447 return; 448 } 449 intrstr = pci_intr_string(pa->pa_pc, ih); 450 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 451 auich_intr, sc); 452 if (sc->sc_ih == NULL) { 453 printf("%s: can't establish interrupt", sc->sc_dev.dv_xname); 454 if (intrstr != NULL) 455 printf(" at %s", intrstr); 456 printf("\n"); 457 return; 458 } 459 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 460 461 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 462 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 463 "0x%02x", PCI_REVISION(pa->pa_class)); 464 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 465 466 if (d->vendor == PCI_VENDOR_SIS 467 && d->product == PCI_PRODUCT_SIS_7012_AC) { 468 sc->sc_sts_reg = ICH_PICB; 469 sc->sc_sample_size = 1; 470 } else { 471 sc->sc_sts_reg = ICH_STS; 472 sc->sc_sample_size = 2; 473 } 474 475 /* Set up DMA lists. */ 476 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 477 auich_alloc_cdata(sc); 478 479 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 480 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 481 482 /* Reset codec and AC'97 */ 483 sc->sc_ac97rate = FIXED_RATE; 484 auich_reset_codec(sc); 485 486 sc->host_if.arg = sc; 487 sc->host_if.attach = auich_attach_codec; 488 sc->host_if.read = auich_read_codec; 489 sc->host_if.write = auich_write_codec; 490 sc->host_if.reset = auich_reset_codec; 491 492 if (ac97_attach(&sc->host_if) != 0) 493 return; 494 495 auich_read_codec(sc, AC97_REG_EXTENDED_ID, &ext_id); 496 if ((ext_id & (AC97_CODEC_DOES_VRA | AC97_CODEC_DOES_MICVRA)) != 0) { 497 auich_read_codec(sc, AC97_REG_EXTENDED_STATUS, &ext_status); 498 if ((ext_id & AC97_CODEC_DOES_VRA) !=0) 499 ext_status |= AC97_ENAB_VRA; 500 if ((ext_id & AC97_CODEC_DOES_MICVRA) !=0) 501 ext_status |= AC97_ENAB_MICVRA; 502 auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, ext_status); 503 504 /* so it claims to do variable rate, let's make sure */ 505 if (auich_set_rate(sc, AUMODE_PLAY, 44100) == 44100) 506 sc->sc_fixed_rate = 0; 507 else 508 sc->sc_fixed_rate = FIXED_RATE; 509 auich_set_rate(sc, AUMODE_PLAY, FIXED_RATE); 510 } else { 511 sc->sc_fixed_rate = FIXED_RATE; 512 } 513 if (sc->sc_fixed_rate) 514 printf("%s: warning, fixed rate codec\n", sc->sc_dev.dv_xname); 515 516 /* Watch for power change */ 517 sc->sc_suspend = PWR_RESUME; 518 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 519 520 config_interrupts(self, auich_finish_attach); 521 } 522 523 void 524 auich_finish_attach(struct device *self) 525 { 526 struct auich_softc *sc = (void *)self; 527 528 if (sc->sc_fixed_rate == 0) 529 sc->sc_ac97rate = auich_calibrate(sc); 530 531 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 532 } 533 534 #define ICH_CODECIO_INTERVAL 10 535 int 536 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 537 { 538 struct auich_softc *sc = v; 539 int i; 540 uint32_t status; 541 542 /* wait for an access semaphore */ 543 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 544 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 545 DELAY(ICH_CODECIO_INTERVAL)); 546 547 if (i > 0) { 548 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 549 DPRINTF(ICH_DEBUG_CODECIO, 550 ("auich_read_codec(%x, %x)\n", reg, *val)); 551 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 552 if (status & ICH_RCS) { 553 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 554 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 555 *val = 0xffff; 556 } 557 return 0; 558 } else { 559 DPRINTF(ICH_DEBUG_CODECIO, 560 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 561 return -1; 562 } 563 } 564 565 int 566 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 567 { 568 struct auich_softc *sc = v; 569 int i; 570 571 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 572 /* wait for an access semaphore */ 573 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 574 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 575 DELAY(ICH_CODECIO_INTERVAL)); 576 577 if (i > 0) { 578 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 579 return 0; 580 } else { 581 DPRINTF(ICH_DEBUG_CODECIO, 582 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 583 return -1; 584 } 585 } 586 587 int 588 auich_attach_codec(void *v, struct ac97_codec_if *cif) 589 { 590 struct auich_softc *sc = v; 591 592 sc->codec_if = cif; 593 return 0; 594 } 595 596 void 597 auich_reset_codec(void *v) 598 { 599 struct auich_softc *sc = v; 600 int i; 601 uint32_t control, status; 602 603 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 604 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 605 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 606 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 607 608 for (i = 500000; i >= 0; i--) { 609 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 610 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 611 break; 612 DELAY(1); 613 } 614 if (i <= 0) { 615 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 616 /* XXX: should not attach the audio device */ 617 } else { 618 if (status & ICH_SCR) 619 printf("%s: The 2nd codec is ready.\n", 620 sc->sc_dev.dv_xname); 621 if (status & ICH_S2CR) 622 printf("%s: The 3rd codec is ready.\n", 623 sc->sc_dev.dv_xname); 624 } 625 } 626 627 int 628 auich_open(void *v, int flags) 629 { 630 631 return 0; 632 } 633 634 void 635 auich_close(void *v) 636 { 637 struct auich_softc *sc = v; 638 639 auich_halt_output(sc); 640 auich_halt_input(sc); 641 642 sc->sc_pintr = NULL; 643 sc->sc_rintr = NULL; 644 } 645 646 int 647 auich_query_encoding(void *v, struct audio_encoding *aep) 648 { 649 650 switch (aep->index) { 651 case 0: 652 strcpy(aep->name, AudioEulinear); 653 aep->encoding = AUDIO_ENCODING_ULINEAR; 654 aep->precision = 8; 655 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 656 return (0); 657 case 1: 658 strcpy(aep->name, AudioEmulaw); 659 aep->encoding = AUDIO_ENCODING_ULAW; 660 aep->precision = 8; 661 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 662 return (0); 663 case 2: 664 strcpy(aep->name, AudioEalaw); 665 aep->encoding = AUDIO_ENCODING_ALAW; 666 aep->precision = 8; 667 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 668 return (0); 669 case 3: 670 strcpy(aep->name, AudioEslinear); 671 aep->encoding = AUDIO_ENCODING_SLINEAR; 672 aep->precision = 8; 673 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 674 return (0); 675 case 4: 676 strcpy(aep->name, AudioEslinear_le); 677 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 678 aep->precision = 16; 679 aep->flags = 0; 680 return (0); 681 case 5: 682 strcpy(aep->name, AudioEulinear_le); 683 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 684 aep->precision = 16; 685 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 686 return (0); 687 case 6: 688 strcpy(aep->name, AudioEslinear_be); 689 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 690 aep->precision = 16; 691 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 692 return (0); 693 case 7: 694 strcpy(aep->name, AudioEulinear_be); 695 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 696 aep->precision = 16; 697 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 698 return (0); 699 default: 700 return (EINVAL); 701 } 702 } 703 704 int 705 auich_set_rate(struct auich_softc *sc, int mode, uint srate) 706 { 707 u_int16_t val, rate, inout; 708 u_int32_t rvalue; 709 710 inout = mode == AUMODE_PLAY ? ICH_PM_PCMO : ICH_PM_PCMI; 711 712 auich_read_codec(sc, AC97_REG_POWER, &val); 713 auich_write_codec(sc, AC97_REG_POWER, val | inout); 714 715 rvalue = srate * FIXED_RATE / sc->sc_ac97rate; 716 if (mode == AUMODE_PLAY) { 717 auich_write_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, rvalue); 718 auich_read_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, &rate); 719 } else { 720 auich_write_codec(sc, AC97_REG_PCM_LR_ADC_RATE, rvalue); 721 auich_read_codec(sc, AC97_REG_PCM_LR_ADC_RATE, &rate); 722 } 723 724 auich_write_codec(sc, AC97_REG_POWER, val); 725 726 /* Cast to avoid integer overflow */ 727 rvalue = (u_int32_t)rate * sc->sc_ac97rate / FIXED_RATE; 728 return rvalue; 729 } 730 731 int 732 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 733 struct audio_params *rec) 734 { 735 struct auich_softc *sc = v; 736 struct audio_params *p; 737 int mode; 738 739 for (mode = AUMODE_RECORD; mode != -1; 740 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 741 if ((setmode & mode) == 0) 742 continue; 743 744 p = mode == AUMODE_PLAY ? play : rec; 745 if (p == NULL) 746 continue; 747 748 if ((p->sample_rate != 8000) && 749 (p->sample_rate != 11025) && 750 (p->sample_rate != 12000) && 751 (p->sample_rate != 16000) && 752 (p->sample_rate != 22050) && 753 (p->sample_rate != 24000) && 754 (p->sample_rate != 32000) && 755 (p->sample_rate != 44100) && 756 (p->sample_rate != 48000)) 757 return (EINVAL); 758 759 p->factor = 1; 760 if (p->precision == 8) 761 p->factor *= 2; 762 763 p->sw_code = NULL; 764 /* setup hardware formats */ 765 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 766 p->hw_precision = 16; 767 if (p->channels < 2) 768 p->hw_channels = 2; 769 switch (p->encoding) { 770 case AUDIO_ENCODING_SLINEAR_BE: 771 if (p->precision == 16) { 772 p->sw_code = swap_bytes; 773 } else { 774 if (mode == AUMODE_PLAY) 775 p->sw_code = linear8_to_linear16_le; 776 else 777 p->sw_code = linear16_to_linear8_le; 778 } 779 break; 780 781 case AUDIO_ENCODING_SLINEAR_LE: 782 if (p->precision != 16) { 783 if (mode == AUMODE_PLAY) 784 p->sw_code = linear8_to_linear16_le; 785 else 786 p->sw_code = linear16_to_linear8_le; 787 } 788 break; 789 790 case AUDIO_ENCODING_ULINEAR_BE: 791 if (p->precision == 16) { 792 if (mode == AUMODE_PLAY) 793 p->sw_code = 794 swap_bytes_change_sign16_le; 795 else 796 p->sw_code = 797 change_sign16_swap_bytes_le; 798 } else { 799 if (mode == AUMODE_PLAY) 800 p->sw_code = 801 ulinear8_to_slinear16_le; 802 else 803 p->sw_code = 804 slinear16_to_ulinear8_le; 805 } 806 break; 807 808 case AUDIO_ENCODING_ULINEAR_LE: 809 if (p->precision == 16) { 810 p->sw_code = change_sign16_le; 811 } else { 812 if (mode == AUMODE_PLAY) 813 p->sw_code = 814 ulinear8_to_slinear16_le; 815 else 816 p->sw_code = 817 slinear16_to_ulinear8_le; 818 } 819 break; 820 821 case AUDIO_ENCODING_ULAW: 822 if (mode == AUMODE_PLAY) { 823 p->sw_code = mulaw_to_slinear16_le; 824 } else { 825 p->sw_code = slinear16_to_mulaw_le; 826 } 827 break; 828 829 case AUDIO_ENCODING_ALAW: 830 if (mode == AUMODE_PLAY) { 831 p->sw_code = alaw_to_slinear16_le; 832 } else { 833 p->sw_code = slinear16_to_alaw_le; 834 } 835 break; 836 837 default: 838 return (EINVAL); 839 } 840 841 if (sc->sc_fixed_rate) 842 p->hw_sample_rate = sc->sc_fixed_rate; 843 else 844 p->hw_sample_rate = auich_set_rate(sc, mode, 845 p->sample_rate); 846 } 847 848 return (0); 849 } 850 851 int 852 auich_round_blocksize(void *v, int blk) 853 { 854 855 return (blk & ~0x3f); /* keep good alignment */ 856 } 857 858 int 859 auich_halt_output(void *v) 860 { 861 struct auich_softc *sc = v; 862 863 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 864 865 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 866 867 return (0); 868 } 869 870 int 871 auich_halt_input(void *v) 872 { 873 struct auich_softc *sc = v; 874 875 DPRINTF(ICH_DEBUG_DMA, 876 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 877 878 /* XXX halt both unless known otherwise */ 879 880 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 881 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 882 883 return (0); 884 } 885 886 int 887 auich_getdev(void *v, struct audio_device *adp) 888 { 889 struct auich_softc *sc = v; 890 891 *adp = sc->sc_audev; 892 return (0); 893 } 894 895 int 896 auich_set_port(void *v, mixer_ctrl_t *cp) 897 { 898 struct auich_softc *sc = v; 899 900 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 901 } 902 903 int 904 auich_get_port(void *v, mixer_ctrl_t *cp) 905 { 906 struct auich_softc *sc = v; 907 908 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 909 } 910 911 int 912 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 913 { 914 struct auich_softc *sc = v; 915 916 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 917 } 918 919 void * 920 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 921 { 922 struct auich_softc *sc = v; 923 struct auich_dma *p; 924 int error; 925 926 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 927 return (NULL); 928 929 p = malloc(sizeof(*p), pool, flags|M_ZERO); 930 if (p == NULL) 931 return (NULL); 932 933 error = auich_allocmem(sc, size, 0, p); 934 if (error) { 935 free(p, pool); 936 return (NULL); 937 } 938 939 p->next = sc->sc_dmas; 940 sc->sc_dmas = p; 941 942 return (KERNADDR(p)); 943 } 944 945 void 946 auich_freem(void *v, void *ptr, int pool) 947 { 948 struct auich_softc *sc = v; 949 struct auich_dma *p, **pp; 950 951 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 952 if (KERNADDR(p) == ptr) { 953 auich_freemem(sc, p); 954 *pp = p->next; 955 free(p, pool); 956 return; 957 } 958 } 959 } 960 961 size_t 962 auich_round_buffersize(void *v, int direction, size_t size) 963 { 964 965 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 966 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 967 968 return size; 969 } 970 971 paddr_t 972 auich_mappage(void *v, void *mem, off_t off, int prot) 973 { 974 struct auich_softc *sc = v; 975 struct auich_dma *p; 976 977 if (off < 0) 978 return (-1); 979 980 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 981 ; 982 if (!p) 983 return (-1); 984 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 985 off, prot, BUS_DMA_WAITOK)); 986 } 987 988 int 989 auich_get_props(void *v) 990 { 991 992 return (AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | 993 AUDIO_PROP_FULLDUPLEX); 994 } 995 996 int 997 auich_intr(void *v) 998 { 999 struct auich_softc *sc = v; 1000 int ret = 0, sts, gsts, i, qptr; 1001 1002 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 1003 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 1004 1005 if (gsts & ICH_POINT) { 1006 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 1007 DPRINTF(ICH_DEBUG_DMA, 1008 ("auich_intr: osts=0x%x\n", sts)); 1009 1010 if (sts & ICH_FIFOE) { 1011 printf("%s: fifo underrun # %u\n", 1012 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1013 } 1014 1015 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1016 if (sts & (ICH_LVBCI | ICH_CELV)) { 1017 struct auich_dmalist *q; 1018 1019 qptr = sc->ptr_pcmo; 1020 1021 while (qptr != i) { 1022 q = &sc->dmalist_pcmo[qptr]; 1023 1024 q->base = sc->pcmo_p; 1025 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1026 DPRINTF(ICH_DEBUG_DMA, 1027 ("auich_intr: %p, %p = %x @ 0x%x\n", 1028 &sc->dmalist_pcmo[i], q, 1029 sc->pcmo_blksize / 2, sc->pcmo_p)); 1030 1031 sc->pcmo_p += sc->pcmo_blksize; 1032 if (sc->pcmo_p >= sc->pcmo_end) 1033 sc->pcmo_p = sc->pcmo_start; 1034 1035 if (++qptr == ICH_DMALIST_MAX) 1036 qptr = 0; 1037 } 1038 1039 sc->ptr_pcmo = qptr; 1040 bus_space_write_1(sc->iot, sc->aud_ioh, 1041 ICH_PCMO + ICH_LVI, 1042 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1043 } 1044 1045 if (sts & ICH_BCIS && sc->sc_pintr) 1046 sc->sc_pintr(sc->sc_parg); 1047 1048 /* int ack */ 1049 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1050 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1051 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1052 ret++; 1053 } 1054 1055 if (gsts & ICH_PIINT) { 1056 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1057 DPRINTF(ICH_DEBUG_DMA, 1058 ("auich_intr: ists=0x%x\n", sts)); 1059 1060 if (sts & ICH_FIFOE) { 1061 printf("%s: fifo overrun # %u\n", 1062 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1063 } 1064 1065 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1066 if (sts & (ICH_LVBCI | ICH_CELV)) { 1067 struct auich_dmalist *q; 1068 1069 qptr = sc->ptr_pcmi; 1070 1071 while (qptr != i) { 1072 q = &sc->dmalist_pcmi[qptr]; 1073 1074 q->base = sc->pcmi_p; 1075 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1076 DPRINTF(ICH_DEBUG_DMA, 1077 ("auich_intr: %p, %p = %x @ 0x%x\n", 1078 &sc->dmalist_pcmi[i], q, 1079 sc->pcmi_blksize / 2, sc->pcmi_p)); 1080 1081 sc->pcmi_p += sc->pcmi_blksize; 1082 if (sc->pcmi_p >= sc->pcmi_end) 1083 sc->pcmi_p = sc->pcmi_start; 1084 1085 if (++qptr == ICH_DMALIST_MAX) 1086 qptr = 0; 1087 } 1088 1089 sc->ptr_pcmi = qptr; 1090 bus_space_write_1(sc->iot, sc->aud_ioh, 1091 ICH_PCMI + ICH_LVI, 1092 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1093 } 1094 1095 if (sts & ICH_BCIS && sc->sc_rintr) 1096 sc->sc_rintr(sc->sc_rarg); 1097 1098 /* int ack */ 1099 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1100 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1101 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1102 ret++; 1103 } 1104 1105 if (gsts & ICH_MIINT) { 1106 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1107 DPRINTF(ICH_DEBUG_DMA, 1108 ("auich_intr: ists=0x%x\n", sts)); 1109 if (sts & ICH_FIFOE) 1110 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1111 1112 /* TODO mic input dma */ 1113 1114 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1115 } 1116 1117 return ret; 1118 } 1119 1120 int 1121 auich_trigger_output(void *v, void *start, void *end, int blksize, 1122 void (*intr)(void *), void *arg, struct audio_params *param) 1123 { 1124 struct auich_softc *sc = v; 1125 struct auich_dmalist *q; 1126 struct auich_dma *p; 1127 size_t size; 1128 1129 DPRINTF(ICH_DEBUG_DMA, 1130 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1131 start, end, blksize, intr, arg, param)); 1132 1133 sc->sc_pintr = intr; 1134 sc->sc_parg = arg; 1135 1136 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1137 ; 1138 if (!p) { 1139 printf("auich_trigger_output: bad addr %p\n", start); 1140 return (EINVAL); 1141 } 1142 1143 size = (size_t)((caddr_t)end - (caddr_t)start); 1144 1145 /* 1146 * The logic behind this is: 1147 * setup one buffer to play, then LVI dump out the rest 1148 * to the scatter-gather chain. 1149 */ 1150 sc->pcmo_start = DMAADDR(p); 1151 sc->pcmo_p = sc->pcmo_start + blksize; 1152 sc->pcmo_end = sc->pcmo_start + size; 1153 sc->pcmo_blksize = blksize; 1154 1155 sc->ptr_pcmo = 0; 1156 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1157 q->base = sc->pcmo_start; 1158 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1159 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1160 sc->ptr_pcmo = 0; 1161 1162 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1163 sc->sc_cddma + ICH_PCMO_OFF(0)); 1164 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1165 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1166 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1167 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1168 1169 return (0); 1170 } 1171 1172 int 1173 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1174 void *v; 1175 void *start, *end; 1176 int blksize; 1177 void (*intr)(void *); 1178 void *arg; 1179 struct audio_params *param; 1180 { 1181 struct auich_softc *sc = v; 1182 struct auich_dmalist *q; 1183 struct auich_dma *p; 1184 size_t size; 1185 1186 DPRINTF(ICH_DEBUG_DMA, 1187 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1188 start, end, blksize, intr, arg, param)); 1189 1190 sc->sc_rintr = intr; 1191 sc->sc_rarg = arg; 1192 1193 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1194 ; 1195 if (!p) { 1196 printf("auich_trigger_input: bad addr %p\n", start); 1197 return (EINVAL); 1198 } 1199 1200 size = (size_t)((caddr_t)end - (caddr_t)start); 1201 1202 /* 1203 * The logic behind this is: 1204 * setup one buffer to play, then LVI dump out the rest 1205 * to the scatter-gather chain. 1206 */ 1207 sc->pcmi_start = DMAADDR(p); 1208 sc->pcmi_p = sc->pcmi_start + blksize; 1209 sc->pcmi_end = sc->pcmi_start + size; 1210 sc->pcmi_blksize = blksize; 1211 1212 sc->ptr_pcmi = 0; 1213 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1214 q->base = sc->pcmi_start; 1215 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1216 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1217 sc->ptr_pcmi = 0; 1218 1219 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1220 sc->sc_cddma + ICH_PCMI_OFF(0)); 1221 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1222 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1223 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1224 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1225 1226 return (0); 1227 } 1228 1229 int 1230 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1231 struct auich_dma *p) 1232 { 1233 int error; 1234 1235 p->size = size; 1236 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1237 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1238 &p->nsegs, BUS_DMA_NOWAIT); 1239 if (error) 1240 return (error); 1241 1242 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1243 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1244 if (error) 1245 goto free; 1246 1247 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1248 0, BUS_DMA_NOWAIT, &p->map); 1249 if (error) 1250 goto unmap; 1251 1252 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1253 BUS_DMA_NOWAIT); 1254 if (error) 1255 goto destroy; 1256 return (0); 1257 1258 destroy: 1259 bus_dmamap_destroy(sc->dmat, p->map); 1260 unmap: 1261 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1262 free: 1263 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1264 return (error); 1265 } 1266 1267 int 1268 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1269 { 1270 1271 bus_dmamap_unload(sc->dmat, p->map); 1272 bus_dmamap_destroy(sc->dmat, p->map); 1273 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1274 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1275 return (0); 1276 } 1277 1278 int 1279 auich_alloc_cdata(struct auich_softc *sc) 1280 { 1281 bus_dma_segment_t seg; 1282 int error, rseg; 1283 1284 /* 1285 * Allocate the control data structure, and create and load the 1286 * DMA map for it. 1287 */ 1288 if ((error = bus_dmamem_alloc(sc->dmat, 1289 sizeof(struct auich_cdata), 1290 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1291 printf("%s: unable to allocate control data, error = %d\n", 1292 sc->sc_dev.dv_xname, error); 1293 goto fail_0; 1294 } 1295 1296 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1297 sizeof(struct auich_cdata), 1298 (caddr_t *) &sc->sc_cdata, 1299 BUS_DMA_COHERENT)) != 0) { 1300 printf("%s: unable to map control data, error = %d\n", 1301 sc->sc_dev.dv_xname, error); 1302 goto fail_1; 1303 } 1304 1305 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1306 sizeof(struct auich_cdata), 0, 0, 1307 &sc->sc_cddmamap)) != 0) { 1308 printf("%s: unable to create control data DMA map, " 1309 "error = %d\n", sc->sc_dev.dv_xname, error); 1310 goto fail_2; 1311 } 1312 1313 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1314 sc->sc_cdata, sizeof(struct auich_cdata), 1315 NULL, 0)) != 0) { 1316 printf("%s: unable tp load control data DMA map, " 1317 "error = %d\n", sc->sc_dev.dv_xname, error); 1318 goto fail_3; 1319 } 1320 1321 return (0); 1322 1323 fail_3: 1324 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1325 fail_2: 1326 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1327 sizeof(struct auich_cdata)); 1328 fail_1: 1329 bus_dmamem_free(sc->dmat, &seg, rseg); 1330 fail_0: 1331 return (error); 1332 } 1333 1334 void 1335 auich_powerhook(int why, void *addr) 1336 { 1337 struct auich_softc *sc = (struct auich_softc *)addr; 1338 1339 switch (why) { 1340 case PWR_SUSPEND: 1341 case PWR_STANDBY: 1342 /* Power down */ 1343 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1344 sc->sc_suspend = why; 1345 auich_read_codec(sc, AC97_REG_EXTENDED_STATUS, &sc->ext_status); 1346 break; 1347 1348 case PWR_RESUME: 1349 /* Wake up */ 1350 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1351 if (sc->sc_suspend == PWR_RESUME) { 1352 printf("%s: resume without suspend.\n", 1353 sc->sc_dev.dv_xname); 1354 sc->sc_suspend = why; 1355 return; 1356 } 1357 sc->sc_suspend = why; 1358 auich_reset_codec(sc); 1359 DELAY(1000); 1360 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1361 auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, sc->ext_status); 1362 break; 1363 1364 case PWR_SOFTSUSPEND: 1365 case PWR_SOFTSTANDBY: 1366 case PWR_SOFTRESUME: 1367 break; 1368 } 1369 } 1370 1371 /* -------------------------------------------------------------------- */ 1372 /* Calibrate card (some boards are overclocked and need scaling) */ 1373 1374 unsigned int 1375 auich_calibrate(struct auich_softc *sc) 1376 { 1377 struct timeval t1, t2; 1378 uint8_t ociv, nciv; 1379 uint64_t wait_us; 1380 uint32_t actual_48k_rate, bytes, ac97rate; 1381 void *temp_buffer; 1382 struct auich_dma *p; 1383 1384 /* 1385 * Grab audio from input for fixed interval and compare how 1386 * much we actually get with what we expect. Interval needs 1387 * to be sufficiently short that no interrupts are 1388 * generated. 1389 */ 1390 1391 /* Force the codec to a known state first. */ 1392 auich_write_codec(sc, AC97_REG_PCM_LR_ADC_RATE, 48000); 1393 1394 /* Setup a buffer */ 1395 bytes = 64000; 1396 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1397 1398 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1399 ; 1400 if (p == NULL) { 1401 printf("auich_calibrate: bad address %p\n", temp_buffer); 1402 return FIXED_RATE; 1403 } 1404 sc->dmalist_pcmi[0].base = DMAADDR(p); 1405 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size); 1406 1407 /* 1408 * our data format is stereo, 16 bit so each sample is 4 bytes. 1409 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1410 * we're going to start recording with interrupts disabled and measure 1411 * the time taken for one block to complete. we know the block size, 1412 * we know the time in microseconds, we calculate the sample rate: 1413 * 1414 * actual_rate [bps] = bytes / (time [s] * 4) 1415 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1416 * actual_rate [Hz] = (bytes * 250000) / time [us] 1417 */ 1418 1419 /* prepare */ 1420 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1421 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1422 sc->sc_cddma + ICH_PCMI_OFF(0)); 1423 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1424 (0 - 1) & ICH_LVI_MASK); 1425 1426 /* start */ 1427 microtime(&t1); 1428 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1429 1430 /* wait */ 1431 nciv = ociv; 1432 do { 1433 microtime(&t2); 1434 if (t2.tv_sec - t1.tv_sec > 1) 1435 break; 1436 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1437 ICH_PCMI + ICH_CIV); 1438 } while (nciv == ociv); 1439 microtime(&t2); 1440 1441 /* stop */ 1442 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1443 1444 /* reset */ 1445 DELAY(100); 1446 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1447 1448 /* turn time delta into us */ 1449 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1450 1451 auich_freem(sc, temp_buffer, M_DEVBUF); 1452 1453 if (nciv == ociv) { 1454 printf("%s: ac97 link rate calibration timed out after %" 1455 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1456 return FIXED_RATE; 1457 } 1458 1459 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1460 1461 if (actual_48k_rate < 50000) 1462 ac97rate = 48000; 1463 else 1464 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1465 1466 printf("%s: measured ac97 link rate at %d Hz", 1467 sc->sc_dev.dv_xname, actual_48k_rate); 1468 if (ac97rate != actual_48k_rate) 1469 printf(", will use %d Hz", ac97rate); 1470 printf("\n"); 1471 1472 return ac97rate; 1473 } 1474
Indexes created Wed Oct 22 13:09:56 GMT 2025