auich.c revision 1.25
1 /* $NetBSD: auich.c,v 1.25 2002/10/04 14:33:30 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * 107 * TODO: 108 * - Add support for the microphone input. 109 * - 4ch/6ch support. 110 * - auich_calibrate() is called in auich_open(). It causes about 0.1sec 111 * delay in the first open(). auich_calibrate() should be called in 112 * auich_attach(). However microtime() doesn't work in the attach 113 * stage. 114 */ 115 116 #include <sys/cdefs.h> 117 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.25 2002/10/04 14:33:30 kent Exp $"); 118 119 #include <sys/param.h> 120 #include <sys/systm.h> 121 #include <sys/kernel.h> 122 #include <sys/malloc.h> 123 #include <sys/device.h> 124 #include <sys/fcntl.h> 125 #include <sys/proc.h> 126 127 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 128 129 #include <dev/pci/pcidevs.h> 130 #include <dev/pci/pcivar.h> 131 #include <dev/pci/auichreg.h> 132 133 #include <sys/audioio.h> 134 #include <dev/audio_if.h> 135 #include <dev/mulaw.h> 136 #include <dev/auconv.h> 137 138 #include <machine/bus.h> 139 140 #include <dev/ic/ac97reg.h> 141 #include <dev/ic/ac97var.h> 142 143 struct auich_dma { 144 bus_dmamap_t map; 145 caddr_t addr; 146 bus_dma_segment_t segs[1]; 147 int nsegs; 148 size_t size; 149 struct auich_dma *next; 150 }; 151 152 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 153 #define KERNADDR(p) ((void *)((p)->addr)) 154 155 struct auich_cdata { 156 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 157 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 158 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 159 }; 160 161 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 162 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 163 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 164 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 165 166 struct auich_softc { 167 struct device sc_dev; 168 void *sc_ih; 169 170 audio_device_t sc_audev; 171 172 bus_space_tag_t iot; 173 bus_space_handle_t mix_ioh; 174 bus_space_handle_t aud_ioh; 175 bus_dma_tag_t dmat; 176 177 struct ac97_codec_if *codec_if; 178 struct ac97_host_if host_if; 179 180 /* DMA scatter-gather lists. */ 181 bus_dmamap_t sc_cddmamap; 182 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 183 184 struct auich_cdata *sc_cdata; 185 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 186 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 187 #define dmalist_mici sc_cdata->ic_dmalist_mici 188 189 int ptr_pcmo, 190 ptr_pcmi, 191 ptr_mici; 192 193 /* i/o buffer pointers */ 194 u_int32_t pcmo_start, pcmo_p, pcmo_end; 195 int pcmo_blksize, pcmo_fifoe; 196 197 u_int32_t pcmi_start, pcmi_p, pcmi_end; 198 int pcmi_blksize, pcmi_fifoe; 199 200 u_int32_t mici_start, mici_p, mici_end; 201 int mici_blksize, mici_fifoe; 202 203 struct auich_dma *sc_dmas; 204 205 int sc_fixed_rate; 206 int sc_calibrated; /* sc_ac97rate has correct value */ 207 int sc_ac97rate; 208 int sc_ignore_codecready; 209 210 /* SiS 7012 hack */ 211 int sc_sample_size; 212 int sc_sts_reg; 213 214 void (*sc_pintr)(void *); 215 void *sc_parg; 216 217 void (*sc_rintr)(void *); 218 void *sc_rarg; 219 220 /* Power Management */ 221 void *sc_powerhook; 222 int sc_suspend; 223 u_int16_t ext_status; 224 }; 225 226 #define FIXED_RATE 48000 227 228 /* Debug */ 229 #ifdef AUDIO_DEBUG 230 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 231 int auich_debug = 0xfffe; 232 #define ICH_DEBUG_CODECIO 0x0001 233 #define ICH_DEBUG_DMA 0x0002 234 #define ICH_DEBUG_PARAM 0x0004 235 #else 236 #define DPRINTF(x,y) /* nothing */ 237 #endif 238 239 int auich_match(struct device *, struct cfdata *, void *); 240 void auich_attach(struct device *, struct device *, void *); 241 int auich_intr(void *); 242 243 CFATTACH_DECL(auich, sizeof(struct auich_softc), 244 auich_match, auich_attach, NULL, NULL); 245 246 int auich_open(void *, int); 247 void auich_close(void *); 248 int auich_query_encoding(void *, struct audio_encoding *); 249 int auich_set_params(void *, int, int, struct audio_params *, 250 struct audio_params *); 251 int auich_round_blocksize(void *, int); 252 int auich_halt_output(void *); 253 int auich_halt_input(void *); 254 int auich_getdev(void *, struct audio_device *); 255 int auich_set_port(void *, mixer_ctrl_t *); 256 int auich_get_port(void *, mixer_ctrl_t *); 257 int auich_query_devinfo(void *, mixer_devinfo_t *); 258 void *auich_allocm(void *, int, size_t, int, int); 259 void auich_freem(void *, void *, int); 260 size_t auich_round_buffersize(void *, int, size_t); 261 paddr_t auich_mappage(void *, void *, off_t, int); 262 int auich_get_props(void *); 263 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 264 void *, struct audio_params *); 265 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 266 void *, struct audio_params *); 267 268 int auich_alloc_cdata(struct auich_softc *); 269 270 int auich_allocmem(struct auich_softc *, size_t, size_t, 271 struct auich_dma *); 272 int auich_freemem(struct auich_softc *, struct auich_dma *); 273 274 void auich_powerhook(int, void *); 275 int auich_set_rate(struct auich_softc *sc, int mode, uint srate); 276 unsigned int auich_calibrate(struct auich_softc *sc); 277 278 279 struct audio_hw_if auich_hw_if = { 280 auich_open, 281 auich_close, 282 NULL, /* drain */ 283 auich_query_encoding, 284 auich_set_params, 285 auich_round_blocksize, 286 NULL, /* commit_setting */ 287 NULL, /* init_output */ 288 NULL, /* init_input */ 289 NULL, /* start_output */ 290 NULL, /* start_input */ 291 auich_halt_output, 292 auich_halt_input, 293 NULL, /* speaker_ctl */ 294 auich_getdev, 295 NULL, /* getfd */ 296 auich_set_port, 297 auich_get_port, 298 auich_query_devinfo, 299 auich_allocm, 300 auich_freem, 301 auich_round_buffersize, 302 auich_mappage, 303 auich_get_props, 304 auich_trigger_output, 305 auich_trigger_input, 306 NULL, /* dev_ioctl */ 307 }; 308 309 int auich_attach_codec(void *, struct ac97_codec_if *); 310 int auich_read_codec(void *, u_int8_t, u_int16_t *); 311 int auich_write_codec(void *, u_int8_t, u_int16_t); 312 void auich_reset_codec(void *); 313 314 static const struct auich_devtype { 315 int vendor; 316 int product; 317 const char *name; 318 const char *shortname; 319 } auich_devices[] = { 320 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 321 "i82801AA (ICH) AC-97 Audio", "ICH" }, 322 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 323 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, /* i810-L */ 324 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 325 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 326 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 327 "i82440MX AC-97 Audio", "440MX" }, 328 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 329 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, /* i830Mx i845MP/MZ*/ 330 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 331 "i82801DB (ICH4) AC-97 Audio", "ICH4" }, /* i845E i845Gx */ 332 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 333 "SiS 7012 AC-97 Audio", "SiS7012" }, 334 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 335 "nForce MCP AC-97 Audio", "nForce-MCP" }, 336 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 337 "AMD768 AC-97 Audio", "AMD768" }, 338 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 339 "AMD8111 AC-97 Audio", "AMD8111" }, 340 { 0, 341 NULL, NULL }, 342 }; 343 344 static const struct auich_devtype * 345 auich_lookup(struct pci_attach_args *pa) 346 { 347 const struct auich_devtype *d; 348 349 for (d = auich_devices; d->name != NULL; d++) { 350 if (PCI_VENDOR(pa->pa_id) == d->vendor 351 && PCI_PRODUCT(pa->pa_id) == d->product) 352 return (d); 353 } 354 355 return (NULL); 356 } 357 358 int 359 auich_match(struct device *parent, struct cfdata *match, void *aux) 360 { 361 struct pci_attach_args *pa = aux; 362 363 if (auich_lookup(pa) != NULL) 364 return (1); 365 366 return (0); 367 } 368 369 void 370 auich_attach(struct device *parent, struct device *self, void *aux) 371 { 372 struct auich_softc *sc = (struct auich_softc *)self; 373 struct pci_attach_args *pa = aux; 374 pci_intr_handle_t ih; 375 bus_size_t mix_size, aud_size; 376 pcireg_t csr; 377 const char *intrstr; 378 const struct auich_devtype *d; 379 u_int16_t ext_id, ext_status; 380 u_int32_t status; 381 382 d = auich_lookup(pa); 383 if (d == NULL) 384 panic("auich_attach: impossible"); 385 386 printf(": %s\n", d->name); 387 388 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 389 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 390 printf("%s: can't map codec i/o space\n", 391 sc->sc_dev.dv_xname); 392 return; 393 } 394 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 395 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 396 printf("%s: can't map device i/o space\n", 397 sc->sc_dev.dv_xname); 398 return; 399 } 400 sc->dmat = pa->pa_dmat; 401 402 /* enable bus mastering */ 403 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 404 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 405 csr | PCI_COMMAND_MASTER_ENABLE); 406 407 /* Map and establish the interrupt. */ 408 if (pci_intr_map(pa, &ih)) { 409 printf("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 410 return; 411 } 412 intrstr = pci_intr_string(pa->pa_pc, ih); 413 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 414 auich_intr, sc); 415 if (sc->sc_ih == NULL) { 416 printf("%s: can't establish interrupt", sc->sc_dev.dv_xname); 417 if (intrstr != NULL) 418 printf(" at %s", intrstr); 419 printf("\n"); 420 return; 421 } 422 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 423 424 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 425 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 426 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 427 428 /* SiS 7012 needs special handling */ 429 if (d->vendor == PCI_VENDOR_SIS 430 && d->product == PCI_PRODUCT_SIS_7012_AC) { 431 sc->sc_sts_reg = ICH_PICB; 432 sc->sc_sample_size = 1; 433 } else { 434 sc->sc_sts_reg = ICH_STS; 435 sc->sc_sample_size = 2; 436 } 437 /* nForce MCP quirk */ 438 if (d->vendor == PCI_VENDOR_NVIDIA 439 && d->product == PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC) { 440 sc->sc_ignore_codecready = TRUE; 441 } 442 443 444 /* Set up DMA lists. */ 445 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 446 auich_alloc_cdata(sc); 447 448 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 449 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 450 451 sc->sc_ac97rate = FIXED_RATE; 452 /* Reset codec and AC'97 */ 453 auich_reset_codec(sc); 454 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 455 if (!(status & ICH_PCR)) { /* reset failure */ 456 if (d->vendor == PCI_VENDOR_INTEL 457 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) { 458 /* MSI 845G Max never return ICH_PCR */ 459 sc->sc_ignore_codecready = TRUE; 460 } else { 461 return; 462 } 463 } 464 /* Print capabilities though there are no supports for now */ 465 if ((status & ICH_SAMPLE_CAP) == ICH_POM20) 466 printf("%s: 20 bit precision support\n", sc->sc_dev.dv_xname); 467 if ((status & ICH_CHAN_CAP) == ICH_PCM4) 468 printf("%s: 4ch PCM output support\n", sc->sc_dev.dv_xname); 469 if ((status & ICH_CHAN_CAP) == ICH_PCM6) 470 printf("%s: 6ch PCM output support\n", sc->sc_dev.dv_xname); 471 472 sc->host_if.arg = sc; 473 sc->host_if.attach = auich_attach_codec; 474 sc->host_if.read = auich_read_codec; 475 sc->host_if.write = auich_write_codec; 476 sc->host_if.reset = auich_reset_codec; 477 478 if (ac97_attach(&sc->host_if) != 0) 479 return; 480 481 auich_read_codec(sc, AC97_REG_EXTENDED_ID, &ext_id); 482 if ((ext_id & (AC97_CODEC_DOES_VRA | AC97_CODEC_DOES_MICVRA)) != 0) { 483 auich_read_codec(sc, AC97_REG_EXTENDED_STATUS, &ext_status); 484 if ((ext_id & AC97_CODEC_DOES_VRA) !=0) 485 ext_status |= AC97_ENAB_VRA; 486 if ((ext_id & AC97_CODEC_DOES_MICVRA) !=0) 487 ext_status |= AC97_ENAB_MICVRA; 488 auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, ext_status); 489 490 /* so it claims to do variable rate, let's make sure */ 491 if (auich_set_rate(sc, AUMODE_PLAY, 44100) == 44100) 492 sc->sc_fixed_rate = 0; 493 else 494 sc->sc_fixed_rate = FIXED_RATE; 495 } else { 496 sc->sc_fixed_rate = FIXED_RATE; 497 } 498 if (sc->sc_fixed_rate) 499 printf("%s: warning, fixed rate codec\n", sc->sc_dev.dv_xname); 500 501 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 502 503 /* Watch for power change */ 504 sc->sc_suspend = PWR_RESUME; 505 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 506 } 507 508 #define ICH_CODECIO_INTERVAL 10 509 int 510 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 511 { 512 struct auich_softc *sc = v; 513 int i; 514 uint32_t status; 515 516 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 517 if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) { 518 printf("auich_read_codec: codec is not ready (0x%x)\n", status); 519 *val = 0xffff; 520 return -1; 521 } 522 /* wait for an access semaphore */ 523 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 524 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 525 DELAY(ICH_CODECIO_INTERVAL)); 526 527 if (i > 0) { 528 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 529 DPRINTF(ICH_DEBUG_CODECIO, 530 ("auich_read_codec(%x, %x)\n", reg, *val)); 531 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 532 if (status & ICH_RCS) { 533 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 534 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 535 *val = 0xffff; 536 } 537 return 0; 538 } else { 539 DPRINTF(ICH_DEBUG_CODECIO, 540 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 541 return -1; 542 } 543 } 544 545 int 546 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 547 { 548 struct auich_softc *sc = v; 549 int i; 550 551 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 552 if (!sc->sc_ignore_codecready 553 && !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) { 554 printf("auich_write_codec: codec is not ready."); 555 return -1; 556 } 557 /* wait for an access semaphore */ 558 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 559 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 560 DELAY(ICH_CODECIO_INTERVAL)); 561 562 if (i > 0) { 563 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 564 return 0; 565 } else { 566 DPRINTF(ICH_DEBUG_CODECIO, 567 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 568 return -1; 569 } 570 } 571 572 int 573 auich_attach_codec(void *v, struct ac97_codec_if *cif) 574 { 575 struct auich_softc *sc = v; 576 577 sc->codec_if = cif; 578 return 0; 579 } 580 581 void 582 auich_reset_codec(void *v) 583 { 584 struct auich_softc *sc = v; 585 int i; 586 uint32_t control; 587 588 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 589 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 590 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 591 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 592 593 for (i = 500000; i-- && 594 !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR); 595 DELAY(1)); /* or ICH_SCR? */ 596 if (i <= 0) 597 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 598 } 599 600 int 601 auich_open(void *v, int flags) 602 { 603 struct auich_softc *sc = v; 604 605 if (!sc->sc_fixed_rate && !sc->sc_calibrated) { 606 sc->sc_ac97rate = auich_calibrate(sc); 607 sc->sc_calibrated = TRUE; 608 } 609 return 0; 610 } 611 612 void 613 auich_close(void *v) 614 { 615 struct auich_softc *sc = v; 616 617 auich_halt_output(sc); 618 auich_halt_input(sc); 619 620 sc->sc_pintr = NULL; 621 sc->sc_rintr = NULL; 622 } 623 624 int 625 auich_query_encoding(void *v, struct audio_encoding *aep) 626 { 627 628 switch (aep->index) { 629 case 0: 630 strcpy(aep->name, AudioEulinear); 631 aep->encoding = AUDIO_ENCODING_ULINEAR; 632 aep->precision = 8; 633 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 634 return (0); 635 case 1: 636 strcpy(aep->name, AudioEmulaw); 637 aep->encoding = AUDIO_ENCODING_ULAW; 638 aep->precision = 8; 639 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 640 return (0); 641 case 2: 642 strcpy(aep->name, AudioEalaw); 643 aep->encoding = AUDIO_ENCODING_ALAW; 644 aep->precision = 8; 645 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 646 return (0); 647 case 3: 648 strcpy(aep->name, AudioEslinear); 649 aep->encoding = AUDIO_ENCODING_SLINEAR; 650 aep->precision = 8; 651 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 652 return (0); 653 case 4: 654 strcpy(aep->name, AudioEslinear_le); 655 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 656 aep->precision = 16; 657 aep->flags = 0; 658 return (0); 659 case 5: 660 strcpy(aep->name, AudioEulinear_le); 661 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 662 aep->precision = 16; 663 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 664 return (0); 665 case 6: 666 strcpy(aep->name, AudioEslinear_be); 667 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 668 aep->precision = 16; 669 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 670 return (0); 671 case 7: 672 strcpy(aep->name, AudioEulinear_be); 673 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 674 aep->precision = 16; 675 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 676 return (0); 677 default: 678 return (EINVAL); 679 } 680 } 681 682 int 683 auich_set_rate(struct auich_softc *sc, int mode, uint srate) 684 { 685 u_int16_t val, rate, inout; 686 u_int32_t rvalue; 687 688 inout = mode == AUMODE_PLAY ? ICH_PM_PCMO : ICH_PM_PCMI; 689 690 auich_read_codec(sc, AC97_REG_POWER, &val); 691 auich_write_codec(sc, AC97_REG_POWER, val | inout); 692 693 rvalue = srate * FIXED_RATE / sc->sc_ac97rate; 694 if (mode == AUMODE_PLAY) { 695 auich_write_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, rvalue); 696 auich_read_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, &rate); 697 } else { 698 auich_write_codec(sc, AC97_REG_PCM_LR_ADC_RATE, rvalue); 699 auich_read_codec(sc, AC97_REG_PCM_LR_ADC_RATE, &rate); 700 } 701 702 auich_write_codec(sc, AC97_REG_POWER, val); 703 704 /* Cast to avoid integer overflow */ 705 rvalue = (u_int32_t)rate * sc->sc_ac97rate / FIXED_RATE; 706 return rvalue; 707 } 708 709 int 710 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 711 struct audio_params *rec) 712 { 713 struct auich_softc *sc = v; 714 struct audio_params *p; 715 int mode; 716 717 for (mode = AUMODE_RECORD; mode != -1; 718 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 719 if ((setmode & mode) == 0) 720 continue; 721 722 p = mode == AUMODE_PLAY ? play : rec; 723 if (p == NULL) 724 continue; 725 726 if ((p->sample_rate != 8000) && 727 (p->sample_rate != 11025) && 728 (p->sample_rate != 16000) && 729 (p->sample_rate != 22050) && 730 (p->sample_rate != 32000) && 731 (p->sample_rate != 44100) && 732 (p->sample_rate != 48000)) 733 return (EINVAL); 734 735 p->factor = 1; 736 if (p->precision == 8) 737 p->factor *= 2; 738 739 p->sw_code = NULL; 740 /* setup hardware formats */ 741 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 742 p->hw_precision = 16; 743 744 /* If manaural is requested, aurateconv expands a monaural 745 * stream to stereo. */ 746 if (p->channels < 2) 747 p->hw_channels = 2; 748 749 switch (p->encoding) { 750 case AUDIO_ENCODING_SLINEAR_BE: 751 if (p->precision == 16) { 752 p->sw_code = swap_bytes; 753 } else { 754 if (mode == AUMODE_PLAY) 755 p->sw_code = linear8_to_linear16_le; 756 else 757 p->sw_code = linear16_to_linear8_le; 758 } 759 break; 760 761 case AUDIO_ENCODING_SLINEAR_LE: 762 if (p->precision != 16) { 763 if (mode == AUMODE_PLAY) 764 p->sw_code = linear8_to_linear16_le; 765 else 766 p->sw_code = linear16_to_linear8_le; 767 } 768 break; 769 770 case AUDIO_ENCODING_ULINEAR_BE: 771 if (p->precision == 16) { 772 if (mode == AUMODE_PLAY) 773 p->sw_code = 774 swap_bytes_change_sign16_le; 775 else 776 p->sw_code = 777 change_sign16_swap_bytes_le; 778 } else { 779 if (mode == AUMODE_PLAY) 780 p->sw_code = 781 ulinear8_to_slinear16_le; 782 else 783 p->sw_code = 784 slinear16_to_ulinear8_le; 785 } 786 break; 787 788 case AUDIO_ENCODING_ULINEAR_LE: 789 if (p->precision == 16) { 790 p->sw_code = change_sign16_le; 791 } else { 792 if (mode == AUMODE_PLAY) 793 p->sw_code = 794 ulinear8_to_slinear16_le; 795 else 796 p->sw_code = 797 slinear16_to_ulinear8_le; 798 } 799 break; 800 801 case AUDIO_ENCODING_ULAW: 802 if (mode == AUMODE_PLAY) { 803 p->sw_code = mulaw_to_slinear16_le; 804 } else { 805 p->sw_code = slinear16_to_mulaw_le; 806 } 807 break; 808 809 case AUDIO_ENCODING_ALAW: 810 if (mode == AUMODE_PLAY) { 811 p->sw_code = alaw_to_slinear16_le; 812 } else { 813 p->sw_code = slinear16_to_alaw_le; 814 } 815 break; 816 817 default: 818 return (EINVAL); 819 } 820 821 if (sc->sc_fixed_rate) { 822 p->hw_sample_rate = sc->sc_fixed_rate; 823 } else { 824 p->hw_sample_rate = auich_set_rate(sc, mode, 825 p->sample_rate); 826 } 827 /* If hw_sample_rate is different from sample_rate, aurateconv 828 * works. */ 829 } 830 831 return (0); 832 } 833 834 int 835 auich_round_blocksize(void *v, int blk) 836 { 837 838 return (blk & ~0x3f); /* keep good alignment */ 839 } 840 841 int 842 auich_halt_output(void *v) 843 { 844 struct auich_softc *sc = v; 845 846 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 847 848 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 849 850 return (0); 851 } 852 853 int 854 auich_halt_input(void *v) 855 { 856 struct auich_softc *sc = v; 857 858 DPRINTF(ICH_DEBUG_DMA, 859 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 860 861 /* XXX halt both unless known otherwise */ 862 863 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 864 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 865 866 return (0); 867 } 868 869 int 870 auich_getdev(void *v, struct audio_device *adp) 871 { 872 struct auich_softc *sc = v; 873 874 *adp = sc->sc_audev; 875 return (0); 876 } 877 878 int 879 auich_set_port(void *v, mixer_ctrl_t *cp) 880 { 881 struct auich_softc *sc = v; 882 883 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 884 } 885 886 int 887 auich_get_port(void *v, mixer_ctrl_t *cp) 888 { 889 struct auich_softc *sc = v; 890 891 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 892 } 893 894 int 895 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 896 { 897 struct auich_softc *sc = v; 898 899 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 900 } 901 902 void * 903 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 904 { 905 struct auich_softc *sc = v; 906 struct auich_dma *p; 907 int error; 908 909 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 910 return (NULL); 911 912 p = malloc(sizeof(*p), pool, flags|M_ZERO); 913 if (p == NULL) 914 return (NULL); 915 916 error = auich_allocmem(sc, size, 0, p); 917 if (error) { 918 free(p, pool); 919 return (NULL); 920 } 921 922 p->next = sc->sc_dmas; 923 sc->sc_dmas = p; 924 925 return (KERNADDR(p)); 926 } 927 928 void 929 auich_freem(void *v, void *ptr, int pool) 930 { 931 struct auich_softc *sc = v; 932 struct auich_dma *p, **pp; 933 934 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 935 if (KERNADDR(p) == ptr) { 936 auich_freemem(sc, p); 937 *pp = p->next; 938 free(p, pool); 939 return; 940 } 941 } 942 } 943 944 size_t 945 auich_round_buffersize(void *v, int direction, size_t size) 946 { 947 948 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 949 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 950 951 return size; 952 } 953 954 paddr_t 955 auich_mappage(void *v, void *mem, off_t off, int prot) 956 { 957 struct auich_softc *sc = v; 958 struct auich_dma *p; 959 960 if (off < 0) 961 return (-1); 962 963 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 964 ; 965 if (!p) 966 return (-1); 967 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 968 off, prot, BUS_DMA_WAITOK)); 969 } 970 971 int 972 auich_get_props(void *v) 973 { 974 975 return (AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | 976 AUDIO_PROP_FULLDUPLEX); 977 } 978 979 int 980 auich_intr(void *v) 981 { 982 struct auich_softc *sc = v; 983 int ret = 0, sts, gsts, i, qptr; 984 985 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 986 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 987 988 if (gsts & ICH_POINT) { 989 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 990 DPRINTF(ICH_DEBUG_DMA, 991 ("auich_intr: osts=0x%x\n", sts)); 992 993 if (sts & ICH_FIFOE) { 994 printf("%s: fifo underrun # %u\n", 995 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 996 } 997 998 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 999 if (sts & (ICH_LVBCI | ICH_CELV)) { 1000 struct auich_dmalist *q; 1001 1002 qptr = sc->ptr_pcmo; 1003 1004 while (qptr != i) { 1005 q = &sc->dmalist_pcmo[qptr]; 1006 1007 q->base = sc->pcmo_p; 1008 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1009 DPRINTF(ICH_DEBUG_DMA, 1010 ("auich_intr: %p, %p = %x @ 0x%x\n", 1011 &sc->dmalist_pcmo[i], q, 1012 sc->pcmo_blksize / 2, sc->pcmo_p)); 1013 1014 sc->pcmo_p += sc->pcmo_blksize; 1015 if (sc->pcmo_p >= sc->pcmo_end) 1016 sc->pcmo_p = sc->pcmo_start; 1017 1018 if (++qptr == ICH_DMALIST_MAX) 1019 qptr = 0; 1020 } 1021 1022 sc->ptr_pcmo = qptr; 1023 bus_space_write_1(sc->iot, sc->aud_ioh, 1024 ICH_PCMO + ICH_LVI, 1025 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1026 } 1027 1028 if (sts & ICH_BCIS && sc->sc_pintr) 1029 sc->sc_pintr(sc->sc_parg); 1030 1031 /* int ack */ 1032 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1033 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1034 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1035 ret++; 1036 } 1037 1038 if (gsts & ICH_PIINT) { 1039 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1040 DPRINTF(ICH_DEBUG_DMA, 1041 ("auich_intr: ists=0x%x\n", sts)); 1042 1043 if (sts & ICH_FIFOE) { 1044 printf("%s: fifo overrun # %u\n", 1045 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1046 } 1047 1048 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1049 if (sts & (ICH_LVBCI | ICH_CELV)) { 1050 struct auich_dmalist *q; 1051 1052 qptr = sc->ptr_pcmi; 1053 1054 while (qptr != i) { 1055 q = &sc->dmalist_pcmi[qptr]; 1056 1057 q->base = sc->pcmi_p; 1058 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1059 DPRINTF(ICH_DEBUG_DMA, 1060 ("auich_intr: %p, %p = %x @ 0x%x\n", 1061 &sc->dmalist_pcmi[i], q, 1062 sc->pcmi_blksize / 2, sc->pcmi_p)); 1063 1064 sc->pcmi_p += sc->pcmi_blksize; 1065 if (sc->pcmi_p >= sc->pcmi_end) 1066 sc->pcmi_p = sc->pcmi_start; 1067 1068 if (++qptr == ICH_DMALIST_MAX) 1069 qptr = 0; 1070 } 1071 1072 sc->ptr_pcmi = qptr; 1073 bus_space_write_1(sc->iot, sc->aud_ioh, 1074 ICH_PCMI + ICH_LVI, 1075 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1076 } 1077 1078 if (sts & ICH_BCIS && sc->sc_rintr) 1079 sc->sc_rintr(sc->sc_rarg); 1080 1081 /* int ack */ 1082 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1083 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1084 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1085 ret++; 1086 } 1087 1088 if (gsts & ICH_MIINT) { 1089 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1090 DPRINTF(ICH_DEBUG_DMA, 1091 ("auich_intr: ists=0x%x\n", sts)); 1092 if (sts & ICH_FIFOE) 1093 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1094 1095 /* TODO mic input dma */ 1096 1097 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1098 } 1099 1100 return ret; 1101 } 1102 1103 int 1104 auich_trigger_output(void *v, void *start, void *end, int blksize, 1105 void (*intr)(void *), void *arg, struct audio_params *param) 1106 { 1107 struct auich_softc *sc = v; 1108 struct auich_dmalist *q; 1109 struct auich_dma *p; 1110 size_t size; 1111 1112 DPRINTF(ICH_DEBUG_DMA, 1113 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1114 start, end, blksize, intr, arg, param)); 1115 1116 sc->sc_pintr = intr; 1117 sc->sc_parg = arg; 1118 1119 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1120 ; 1121 if (!p) { 1122 printf("auich_trigger_output: bad addr %p\n", start); 1123 return (EINVAL); 1124 } 1125 1126 size = (size_t)((caddr_t)end - (caddr_t)start); 1127 1128 /* 1129 * The logic behind this is: 1130 * setup one buffer to play, then LVI dump out the rest 1131 * to the scatter-gather chain. 1132 */ 1133 sc->pcmo_start = DMAADDR(p); 1134 sc->pcmo_p = sc->pcmo_start + blksize; 1135 sc->pcmo_end = sc->pcmo_start + size; 1136 sc->pcmo_blksize = blksize; 1137 1138 sc->ptr_pcmo = 0; 1139 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1140 q->base = sc->pcmo_start; 1141 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1142 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1143 sc->ptr_pcmo = 0; 1144 1145 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1146 sc->sc_cddma + ICH_PCMO_OFF(0)); 1147 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1148 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1149 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1150 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1151 1152 return (0); 1153 } 1154 1155 int 1156 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1157 void *v; 1158 void *start, *end; 1159 int blksize; 1160 void (*intr)(void *); 1161 void *arg; 1162 struct audio_params *param; 1163 { 1164 struct auich_softc *sc = v; 1165 struct auich_dmalist *q; 1166 struct auich_dma *p; 1167 size_t size; 1168 1169 DPRINTF(ICH_DEBUG_DMA, 1170 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1171 start, end, blksize, intr, arg, param)); 1172 1173 sc->sc_rintr = intr; 1174 sc->sc_rarg = arg; 1175 1176 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1177 ; 1178 if (!p) { 1179 printf("auich_trigger_input: bad addr %p\n", start); 1180 return (EINVAL); 1181 } 1182 1183 size = (size_t)((caddr_t)end - (caddr_t)start); 1184 1185 /* 1186 * The logic behind this is: 1187 * setup one buffer to play, then LVI dump out the rest 1188 * to the scatter-gather chain. 1189 */ 1190 sc->pcmi_start = DMAADDR(p); 1191 sc->pcmi_p = sc->pcmi_start + blksize; 1192 sc->pcmi_end = sc->pcmi_start + size; 1193 sc->pcmi_blksize = blksize; 1194 1195 sc->ptr_pcmi = 0; 1196 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1197 q->base = sc->pcmi_start; 1198 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1199 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1200 sc->ptr_pcmi = 0; 1201 1202 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1203 sc->sc_cddma + ICH_PCMI_OFF(0)); 1204 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1205 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1206 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1207 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1208 1209 return (0); 1210 } 1211 1212 int 1213 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1214 struct auich_dma *p) 1215 { 1216 int error; 1217 1218 p->size = size; 1219 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1220 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1221 &p->nsegs, BUS_DMA_NOWAIT); 1222 if (error) 1223 return (error); 1224 1225 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1226 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1227 if (error) 1228 goto free; 1229 1230 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1231 0, BUS_DMA_NOWAIT, &p->map); 1232 if (error) 1233 goto unmap; 1234 1235 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1236 BUS_DMA_NOWAIT); 1237 if (error) 1238 goto destroy; 1239 return (0); 1240 1241 destroy: 1242 bus_dmamap_destroy(sc->dmat, p->map); 1243 unmap: 1244 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1245 free: 1246 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1247 return (error); 1248 } 1249 1250 int 1251 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1252 { 1253 1254 bus_dmamap_unload(sc->dmat, p->map); 1255 bus_dmamap_destroy(sc->dmat, p->map); 1256 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1257 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1258 return (0); 1259 } 1260 1261 int 1262 auich_alloc_cdata(struct auich_softc *sc) 1263 { 1264 bus_dma_segment_t seg; 1265 int error, rseg; 1266 1267 /* 1268 * Allocate the control data structure, and create and load the 1269 * DMA map for it. 1270 */ 1271 if ((error = bus_dmamem_alloc(sc->dmat, 1272 sizeof(struct auich_cdata), 1273 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1274 printf("%s: unable to allocate control data, error = %d\n", 1275 sc->sc_dev.dv_xname, error); 1276 goto fail_0; 1277 } 1278 1279 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1280 sizeof(struct auich_cdata), 1281 (caddr_t *) &sc->sc_cdata, 1282 BUS_DMA_COHERENT)) != 0) { 1283 printf("%s: unable to map control data, error = %d\n", 1284 sc->sc_dev.dv_xname, error); 1285 goto fail_1; 1286 } 1287 1288 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1289 sizeof(struct auich_cdata), 0, 0, 1290 &sc->sc_cddmamap)) != 0) { 1291 printf("%s: unable to create control data DMA map, " 1292 "error = %d\n", sc->sc_dev.dv_xname, error); 1293 goto fail_2; 1294 } 1295 1296 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1297 sc->sc_cdata, sizeof(struct auich_cdata), 1298 NULL, 0)) != 0) { 1299 printf("%s: unable tp load control data DMA map, " 1300 "error = %d\n", sc->sc_dev.dv_xname, error); 1301 goto fail_3; 1302 } 1303 1304 return (0); 1305 1306 fail_3: 1307 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1308 fail_2: 1309 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1310 sizeof(struct auich_cdata)); 1311 fail_1: 1312 bus_dmamem_free(sc->dmat, &seg, rseg); 1313 fail_0: 1314 return (error); 1315 } 1316 1317 void 1318 auich_powerhook(int why, void *addr) 1319 { 1320 struct auich_softc *sc = (struct auich_softc *)addr; 1321 1322 switch (why) { 1323 case PWR_SUSPEND: 1324 case PWR_STANDBY: 1325 /* Power down */ 1326 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1327 sc->sc_suspend = why; 1328 auich_read_codec(sc, AC97_REG_EXTENDED_STATUS, &sc->ext_status); 1329 break; 1330 1331 case PWR_RESUME: 1332 /* Wake up */ 1333 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1334 if (sc->sc_suspend == PWR_RESUME) { 1335 printf("%s: resume without suspend.\n", 1336 sc->sc_dev.dv_xname); 1337 sc->sc_suspend = why; 1338 return; 1339 } 1340 sc->sc_suspend = why; 1341 auich_reset_codec(sc); 1342 DELAY(1000); 1343 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1344 auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, sc->ext_status); 1345 break; 1346 1347 case PWR_SOFTSUSPEND: 1348 case PWR_SOFTSTANDBY: 1349 case PWR_SOFTRESUME: 1350 break; 1351 } 1352 } 1353 1354 1355 /* -------------------------------------------------------------------- */ 1356 /* Calibrate card (some boards are overclocked and need scaling) */ 1357 1358 unsigned int 1359 auich_calibrate(struct auich_softc *sc) 1360 { 1361 struct timeval t1, t2; 1362 u_int8_t ociv, nciv; 1363 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1364 void *temp_buffer; 1365 struct auich_dma *p; 1366 1367 ac97rate = 48000; 1368 /* 1369 * Grab audio from input for fixed interval and compare how 1370 * much we actually get with what we expect. Interval needs 1371 * to be sufficiently short that no interrupts are 1372 * generated. 1373 */ 1374 1375 /* Setup a buffer */ 1376 bytes = 16000; 1377 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1378 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1379 ; 1380 if (p == NULL) { 1381 printf("auich_calibrate: bad address %p\n", temp_buffer); 1382 return ac97rate; 1383 } 1384 sc->dmalist_pcmi[0].base = DMAADDR(p); 1385 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size) | ICH_DMAF_IOC; 1386 1387 /* 1388 * our data format is stereo, 16 bit so each sample is 4 bytes. 1389 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1390 * we're going to start recording with interrupts disabled and measure 1391 * the time taken for one block to complete. we know the block size, 1392 * we know the time in microseconds, we calculate the sample rate: 1393 * 1394 * actual_rate [bps] = bytes / (time [s] * 4) 1395 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1396 * actual_rate [Hz] = (bytes * 250000) / time [us] 1397 */ 1398 1399 /* prepare */ 1400 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1401 nciv = ociv; 1402 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1403 sc->sc_cddma + ICH_PCMI_OFF(0)); 1404 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1405 (0 - 1) & ICH_LVI_MASK); 1406 1407 /* start */ 1408 microtime(&t1); 1409 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1410 1411 /* wait */ 1412 while (nciv == ociv) { 1413 microtime(&t2); 1414 if (t2.tv_sec - t1.tv_sec > 1) 1415 break; 1416 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1417 ICH_PCMI + ICH_CIV); 1418 } 1419 microtime(&t2); 1420 1421 /* stop */ 1422 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1423 1424 /* reset */ 1425 DELAY(100); 1426 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1427 1428 /* turn time delta into us */ 1429 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1430 1431 auich_freem(sc, temp_buffer, M_DEVBUF); 1432 1433 if (nciv == ociv) { 1434 printf("%s: ac97 link rate calibration timed out after %d us\n", 1435 sc->sc_dev.dv_xname, wait_us); 1436 return ac97rate; 1437 } 1438 1439 actual_48k_rate = (bytes * 250000) / wait_us; 1440 1441 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 1442 ac97rate = actual_48k_rate; 1443 } 1444 1445 if (ac97rate != 48000) { 1446 printf("%s: measured ac97 link rate at %d Hz", 1447 sc->sc_dev.dv_xname, actual_48k_rate); 1448 if (ac97rate != actual_48k_rate) 1449 printf(", will use %d Hz", ac97rate); 1450 printf("\n"); 1451 } 1452 1453 return ac97rate; 1454 } 1455
Indexes created Wed Oct 22 13:09:56 GMT 2025