auich.c revision 1.27
1 /* $NetBSD: auich.c,v 1.27 2002/10/08 10:25:45 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * 107 * TODO: 108 * - Add support for the microphone input. 109 * - 4ch/6ch support. 110 * - auich_calibrate() is called in auich_open(). It causes about 0.1sec 111 * delay in the first open(). auich_calibrate() should be called in 112 * auich_attach(). However microtime() doesn't work in the attach 113 * stage. 114 */ 115 116 #include <sys/cdefs.h> 117 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.27 2002/10/08 10:25:45 kent Exp $"); 118 119 #include <sys/param.h> 120 #include <sys/systm.h> 121 #include <sys/kernel.h> 122 #include <sys/malloc.h> 123 #include <sys/device.h> 124 #include <sys/fcntl.h> 125 #include <sys/proc.h> 126 127 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 128 129 #include <dev/pci/pcidevs.h> 130 #include <dev/pci/pcivar.h> 131 #include <dev/pci/auichreg.h> 132 133 #include <sys/audioio.h> 134 #include <dev/audio_if.h> 135 #include <dev/mulaw.h> 136 #include <dev/auconv.h> 137 138 #include <machine/bus.h> 139 140 #include <dev/ic/ac97reg.h> 141 #include <dev/ic/ac97var.h> 142 143 struct auich_dma { 144 bus_dmamap_t map; 145 caddr_t addr; 146 bus_dma_segment_t segs[1]; 147 int nsegs; 148 size_t size; 149 struct auich_dma *next; 150 }; 151 152 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 153 #define KERNADDR(p) ((void *)((p)->addr)) 154 155 struct auich_cdata { 156 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 157 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 158 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 159 }; 160 161 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 162 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 163 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 164 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 165 166 struct auich_softc { 167 struct device sc_dev; 168 void *sc_ih; 169 170 audio_device_t sc_audev; 171 172 bus_space_tag_t iot; 173 bus_space_handle_t mix_ioh; 174 bus_space_handle_t aud_ioh; 175 bus_dma_tag_t dmat; 176 177 struct ac97_codec_if *codec_if; 178 struct ac97_host_if host_if; 179 180 /* DMA scatter-gather lists. */ 181 bus_dmamap_t sc_cddmamap; 182 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 183 184 struct auich_cdata *sc_cdata; 185 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 186 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 187 #define dmalist_mici sc_cdata->ic_dmalist_mici 188 189 int ptr_pcmo, 190 ptr_pcmi, 191 ptr_mici; 192 193 /* i/o buffer pointers */ 194 u_int32_t pcmo_start, pcmo_p, pcmo_end; 195 int pcmo_blksize, pcmo_fifoe; 196 197 u_int32_t pcmi_start, pcmi_p, pcmi_end; 198 int pcmi_blksize, pcmi_fifoe; 199 200 u_int32_t mici_start, mici_p, mici_end; 201 int mici_blksize, mici_fifoe; 202 203 struct auich_dma *sc_dmas; 204 205 int sc_calibrated; /* sc_ac97rate has correct value */ 206 int sc_ignore_codecready; 207 208 /* SiS 7012 hack */ 209 int sc_sample_size; 210 int sc_sts_reg; 211 212 void (*sc_pintr)(void *); 213 void *sc_parg; 214 215 void (*sc_rintr)(void *); 216 void *sc_rarg; 217 218 /* Power Management */ 219 void *sc_powerhook; 220 int sc_suspend; 221 u_int16_t ext_status; 222 }; 223 224 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 225 & AC97_EXT_AUDIO_VRA) 226 227 /* Debug */ 228 #ifdef AUDIO_DEBUG 229 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 230 int auich_debug = 0xfffe; 231 #define ICH_DEBUG_CODECIO 0x0001 232 #define ICH_DEBUG_DMA 0x0002 233 #define ICH_DEBUG_PARAM 0x0004 234 #else 235 #define DPRINTF(x,y) /* nothing */ 236 #endif 237 238 int auich_match(struct device *, struct cfdata *, void *); 239 void auich_attach(struct device *, struct device *, void *); 240 int auich_intr(void *); 241 242 CFATTACH_DECL(auich, sizeof(struct auich_softc), 243 auich_match, auich_attach, NULL, NULL); 244 245 int auich_open(void *, int); 246 void auich_close(void *); 247 int auich_query_encoding(void *, struct audio_encoding *); 248 int auich_set_params(void *, int, int, struct audio_params *, 249 struct audio_params *); 250 int auich_round_blocksize(void *, int); 251 int auich_halt_output(void *); 252 int auich_halt_input(void *); 253 int auich_getdev(void *, struct audio_device *); 254 int auich_set_port(void *, mixer_ctrl_t *); 255 int auich_get_port(void *, mixer_ctrl_t *); 256 int auich_query_devinfo(void *, mixer_devinfo_t *); 257 void *auich_allocm(void *, int, size_t, int, int); 258 void auich_freem(void *, void *, int); 259 size_t auich_round_buffersize(void *, int, size_t); 260 paddr_t auich_mappage(void *, void *, off_t, int); 261 int auich_get_props(void *); 262 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 263 void *, struct audio_params *); 264 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 265 void *, struct audio_params *); 266 267 int auich_alloc_cdata(struct auich_softc *); 268 269 int auich_allocmem(struct auich_softc *, size_t, size_t, 270 struct auich_dma *); 271 int auich_freemem(struct auich_softc *, struct auich_dma *); 272 273 void auich_powerhook(int, void *); 274 int auich_set_rate(struct auich_softc *sc, int mode, u_long* srate); 275 unsigned int auich_calibrate(struct auich_softc *sc); 276 277 278 struct audio_hw_if auich_hw_if = { 279 auich_open, 280 auich_close, 281 NULL, /* drain */ 282 auich_query_encoding, 283 auich_set_params, 284 auich_round_blocksize, 285 NULL, /* commit_setting */ 286 NULL, /* init_output */ 287 NULL, /* init_input */ 288 NULL, /* start_output */ 289 NULL, /* start_input */ 290 auich_halt_output, 291 auich_halt_input, 292 NULL, /* speaker_ctl */ 293 auich_getdev, 294 NULL, /* getfd */ 295 auich_set_port, 296 auich_get_port, 297 auich_query_devinfo, 298 auich_allocm, 299 auich_freem, 300 auich_round_buffersize, 301 auich_mappage, 302 auich_get_props, 303 auich_trigger_output, 304 auich_trigger_input, 305 NULL, /* dev_ioctl */ 306 }; 307 308 int auich_attach_codec(void *, struct ac97_codec_if *); 309 int auich_read_codec(void *, u_int8_t, u_int16_t *); 310 int auich_write_codec(void *, u_int8_t, u_int16_t); 311 void auich_reset_codec(void *); 312 313 static const struct auich_devtype { 314 int vendor; 315 int product; 316 const char *name; 317 const char *shortname; 318 } auich_devices[] = { 319 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 320 "i82801AA (ICH) AC-97 Audio", "ICH" }, 321 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 322 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, /* i810-L */ 323 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 324 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 325 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 326 "i82440MX AC-97 Audio", "440MX" }, 327 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 328 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, /* i830Mx i845MP/MZ*/ 329 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 330 "i82801DB (ICH4) AC-97 Audio", "ICH4" }, /* i845E i845Gx */ 331 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 332 "SiS 7012 AC-97 Audio", "SiS7012" }, 333 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 334 "nForce MCP AC-97 Audio", "nForce-MCP" }, 335 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 336 "AMD768 AC-97 Audio", "AMD768" }, 337 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 338 "AMD8111 AC-97 Audio", "AMD8111" }, 339 { 0, 340 NULL, NULL }, 341 }; 342 343 static const struct auich_devtype * 344 auich_lookup(struct pci_attach_args *pa) 345 { 346 const struct auich_devtype *d; 347 348 for (d = auich_devices; d->name != NULL; d++) { 349 if (PCI_VENDOR(pa->pa_id) == d->vendor 350 && PCI_PRODUCT(pa->pa_id) == d->product) 351 return (d); 352 } 353 354 return (NULL); 355 } 356 357 int 358 auich_match(struct device *parent, struct cfdata *match, void *aux) 359 { 360 struct pci_attach_args *pa = aux; 361 362 if (auich_lookup(pa) != NULL) 363 return (1); 364 365 return (0); 366 } 367 368 void 369 auich_attach(struct device *parent, struct device *self, void *aux) 370 { 371 struct auich_softc *sc = (struct auich_softc *)self; 372 struct pci_attach_args *pa = aux; 373 pci_intr_handle_t ih; 374 bus_size_t mix_size, aud_size; 375 pcireg_t csr; 376 const char *intrstr; 377 const struct auich_devtype *d; 378 u_int32_t status; 379 380 d = auich_lookup(pa); 381 if (d == NULL) 382 panic("auich_attach: impossible"); 383 384 printf(": %s\n", d->name); 385 386 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 387 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 388 printf("%s: can't map codec i/o space\n", 389 sc->sc_dev.dv_xname); 390 return; 391 } 392 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 393 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 394 printf("%s: can't map device i/o space\n", 395 sc->sc_dev.dv_xname); 396 return; 397 } 398 sc->dmat = pa->pa_dmat; 399 400 /* enable bus mastering */ 401 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 402 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 403 csr | PCI_COMMAND_MASTER_ENABLE); 404 405 /* Map and establish the interrupt. */ 406 if (pci_intr_map(pa, &ih)) { 407 printf("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 408 return; 409 } 410 intrstr = pci_intr_string(pa->pa_pc, ih); 411 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 412 auich_intr, sc); 413 if (sc->sc_ih == NULL) { 414 printf("%s: can't establish interrupt", sc->sc_dev.dv_xname); 415 if (intrstr != NULL) 416 printf(" at %s", intrstr); 417 printf("\n"); 418 return; 419 } 420 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 421 422 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 423 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 424 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 425 426 /* SiS 7012 needs special handling */ 427 if (d->vendor == PCI_VENDOR_SIS 428 && d->product == PCI_PRODUCT_SIS_7012_AC) { 429 sc->sc_sts_reg = ICH_PICB; 430 sc->sc_sample_size = 1; 431 } else { 432 sc->sc_sts_reg = ICH_STS; 433 sc->sc_sample_size = 2; 434 } 435 /* nForce MCP quirk */ 436 if (d->vendor == PCI_VENDOR_NVIDIA 437 && d->product == PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC) { 438 sc->sc_ignore_codecready = TRUE; 439 } 440 441 442 /* Set up DMA lists. */ 443 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 444 auich_alloc_cdata(sc); 445 446 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 447 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 448 449 /* Reset codec and AC'97 */ 450 auich_reset_codec(sc); 451 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 452 if (!(status & ICH_PCR)) { /* reset failure */ 453 if (d->vendor == PCI_VENDOR_INTEL 454 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) { 455 /* MSI 845G Max never return ICH_PCR */ 456 sc->sc_ignore_codecready = TRUE; 457 } else { 458 return; 459 } 460 } 461 /* Print capabilities though there are no supports for now */ 462 if ((status & ICH_SAMPLE_CAP) == ICH_POM20) 463 printf("%s: 20 bit precision support\n", sc->sc_dev.dv_xname); 464 if ((status & ICH_CHAN_CAP) == ICH_PCM4) 465 printf("%s: 4ch PCM output support\n", sc->sc_dev.dv_xname); 466 if ((status & ICH_CHAN_CAP) == ICH_PCM6) 467 printf("%s: 6ch PCM output support\n", sc->sc_dev.dv_xname); 468 469 sc->host_if.arg = sc; 470 sc->host_if.attach = auich_attach_codec; 471 sc->host_if.read = auich_read_codec; 472 sc->host_if.write = auich_write_codec; 473 sc->host_if.reset = auich_reset_codec; 474 475 if (ac97_attach(&sc->host_if) != 0) 476 return; 477 478 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 479 480 /* Watch for power change */ 481 sc->sc_suspend = PWR_RESUME; 482 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 483 } 484 485 #define ICH_CODECIO_INTERVAL 10 486 int 487 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 488 { 489 struct auich_softc *sc = v; 490 int i; 491 uint32_t status; 492 493 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 494 if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) { 495 printf("auich_read_codec: codec is not ready (0x%x)\n", status); 496 *val = 0xffff; 497 return -1; 498 } 499 /* wait for an access semaphore */ 500 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 501 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 502 DELAY(ICH_CODECIO_INTERVAL)); 503 504 if (i > 0) { 505 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 506 DPRINTF(ICH_DEBUG_CODECIO, 507 ("auich_read_codec(%x, %x)\n", reg, *val)); 508 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 509 if (status & ICH_RCS) { 510 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 511 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 512 *val = 0xffff; 513 } 514 return 0; 515 } else { 516 DPRINTF(ICH_DEBUG_CODECIO, 517 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 518 return -1; 519 } 520 } 521 522 int 523 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 524 { 525 struct auich_softc *sc = v; 526 int i; 527 528 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 529 if (!sc->sc_ignore_codecready 530 && !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) { 531 printf("auich_write_codec: codec is not ready."); 532 return -1; 533 } 534 /* wait for an access semaphore */ 535 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 536 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 537 DELAY(ICH_CODECIO_INTERVAL)); 538 539 if (i > 0) { 540 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 541 return 0; 542 } else { 543 DPRINTF(ICH_DEBUG_CODECIO, 544 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 545 return -1; 546 } 547 } 548 549 int 550 auich_attach_codec(void *v, struct ac97_codec_if *cif) 551 { 552 struct auich_softc *sc = v; 553 554 sc->codec_if = cif; 555 return 0; 556 } 557 558 void 559 auich_reset_codec(void *v) 560 { 561 struct auich_softc *sc = v; 562 int i; 563 uint32_t control; 564 565 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 566 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 567 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 568 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 569 570 for (i = 500000; i-- && 571 !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR); 572 DELAY(1)); /* or ICH_SCR? */ 573 if (i <= 0) 574 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 575 } 576 577 int 578 auich_open(void *v, int flags) 579 { 580 struct auich_softc *sc = v; 581 struct ac97_codec_if *codec = sc->codec_if; 582 583 if (!IS_FIXED_RATE(codec) && !sc->sc_calibrated) { 584 codec->vtbl->set_clock(codec, auich_calibrate(sc)); 585 sc->sc_calibrated = TRUE; 586 } 587 return 0; 588 } 589 590 void 591 auich_close(void *v) 592 { 593 struct auich_softc *sc = v; 594 595 auich_halt_output(sc); 596 auich_halt_input(sc); 597 598 sc->sc_pintr = NULL; 599 sc->sc_rintr = NULL; 600 } 601 602 int 603 auich_query_encoding(void *v, struct audio_encoding *aep) 604 { 605 606 switch (aep->index) { 607 case 0: 608 strcpy(aep->name, AudioEulinear); 609 aep->encoding = AUDIO_ENCODING_ULINEAR; 610 aep->precision = 8; 611 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 612 return (0); 613 case 1: 614 strcpy(aep->name, AudioEmulaw); 615 aep->encoding = AUDIO_ENCODING_ULAW; 616 aep->precision = 8; 617 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 618 return (0); 619 case 2: 620 strcpy(aep->name, AudioEalaw); 621 aep->encoding = AUDIO_ENCODING_ALAW; 622 aep->precision = 8; 623 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 624 return (0); 625 case 3: 626 strcpy(aep->name, AudioEslinear); 627 aep->encoding = AUDIO_ENCODING_SLINEAR; 628 aep->precision = 8; 629 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 630 return (0); 631 case 4: 632 strcpy(aep->name, AudioEslinear_le); 633 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 634 aep->precision = 16; 635 aep->flags = 0; 636 return (0); 637 case 5: 638 strcpy(aep->name, AudioEulinear_le); 639 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 640 aep->precision = 16; 641 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 642 return (0); 643 case 6: 644 strcpy(aep->name, AudioEslinear_be); 645 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 646 aep->precision = 16; 647 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 648 return (0); 649 case 7: 650 strcpy(aep->name, AudioEulinear_be); 651 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 652 aep->precision = 16; 653 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 654 return (0); 655 default: 656 return (EINVAL); 657 } 658 } 659 660 int 661 auich_set_rate(struct auich_softc *sc, int mode, u_long* srate) 662 { 663 int reg; 664 665 reg = mode == AUMODE_PLAY 666 ? AC97_REG_PCM_FRONT_DAC_RATE : AC97_REG_PCM_LR_ADC_RATE; 667 return sc->codec_if->vtbl->set_rate(sc->codec_if, reg, srate); 668 } 669 670 int 671 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 672 struct audio_params *rec) 673 { 674 struct auich_softc *sc = v; 675 struct audio_params *p; 676 int mode; 677 678 for (mode = AUMODE_RECORD; mode != -1; 679 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 680 if ((setmode & mode) == 0) 681 continue; 682 683 p = mode == AUMODE_PLAY ? play : rec; 684 if (p == NULL) 685 continue; 686 687 if ((p->sample_rate != 8000) && 688 (p->sample_rate != 11025) && 689 (p->sample_rate != 16000) && 690 (p->sample_rate != 22050) && 691 (p->sample_rate != 32000) && 692 (p->sample_rate != 44100) && 693 (p->sample_rate != 48000)) 694 return (EINVAL); 695 696 p->factor = 1; 697 if (p->precision == 8) 698 p->factor *= 2; 699 700 p->sw_code = NULL; 701 /* setup hardware formats */ 702 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 703 p->hw_precision = 16; 704 705 /* If manaural is requested, aurateconv expands a monaural 706 * stream to stereo. */ 707 if (p->channels < 2) 708 p->hw_channels = 2; 709 710 switch (p->encoding) { 711 case AUDIO_ENCODING_SLINEAR_BE: 712 if (p->precision == 16) { 713 p->sw_code = swap_bytes; 714 } else { 715 if (mode == AUMODE_PLAY) 716 p->sw_code = linear8_to_linear16_le; 717 else 718 p->sw_code = linear16_to_linear8_le; 719 } 720 break; 721 722 case AUDIO_ENCODING_SLINEAR_LE: 723 if (p->precision != 16) { 724 if (mode == AUMODE_PLAY) 725 p->sw_code = linear8_to_linear16_le; 726 else 727 p->sw_code = linear16_to_linear8_le; 728 } 729 break; 730 731 case AUDIO_ENCODING_ULINEAR_BE: 732 if (p->precision == 16) { 733 if (mode == AUMODE_PLAY) 734 p->sw_code = 735 swap_bytes_change_sign16_le; 736 else 737 p->sw_code = 738 change_sign16_swap_bytes_le; 739 } else { 740 if (mode == AUMODE_PLAY) 741 p->sw_code = 742 ulinear8_to_slinear16_le; 743 else 744 p->sw_code = 745 slinear16_to_ulinear8_le; 746 } 747 break; 748 749 case AUDIO_ENCODING_ULINEAR_LE: 750 if (p->precision == 16) { 751 p->sw_code = change_sign16_le; 752 } else { 753 if (mode == AUMODE_PLAY) 754 p->sw_code = 755 ulinear8_to_slinear16_le; 756 else 757 p->sw_code = 758 slinear16_to_ulinear8_le; 759 } 760 break; 761 762 case AUDIO_ENCODING_ULAW: 763 if (mode == AUMODE_PLAY) { 764 p->sw_code = mulaw_to_slinear16_le; 765 } else { 766 p->sw_code = slinear16_to_mulaw_le; 767 } 768 break; 769 770 case AUDIO_ENCODING_ALAW: 771 if (mode == AUMODE_PLAY) { 772 p->sw_code = alaw_to_slinear16_le; 773 } else { 774 p->sw_code = slinear16_to_alaw_le; 775 } 776 break; 777 778 default: 779 return (EINVAL); 780 } 781 782 if (IS_FIXED_RATE(sc->codec_if)) { 783 return auich_set_rate(sc, mode, &p->hw_sample_rate); 784 /* If hw_sample_rate is changed, aurateconv works. */ 785 } else { 786 return auich_set_rate(sc, mode, &p->sample_rate); 787 } 788 } 789 790 return (0); 791 } 792 793 int 794 auich_round_blocksize(void *v, int blk) 795 { 796 797 return (blk & ~0x3f); /* keep good alignment */ 798 } 799 800 int 801 auich_halt_output(void *v) 802 { 803 struct auich_softc *sc = v; 804 805 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 806 807 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 808 809 return (0); 810 } 811 812 int 813 auich_halt_input(void *v) 814 { 815 struct auich_softc *sc = v; 816 817 DPRINTF(ICH_DEBUG_DMA, 818 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 819 820 /* XXX halt both unless known otherwise */ 821 822 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 823 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 824 825 return (0); 826 } 827 828 int 829 auich_getdev(void *v, struct audio_device *adp) 830 { 831 struct auich_softc *sc = v; 832 833 *adp = sc->sc_audev; 834 return (0); 835 } 836 837 int 838 auich_set_port(void *v, mixer_ctrl_t *cp) 839 { 840 struct auich_softc *sc = v; 841 842 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 843 } 844 845 int 846 auich_get_port(void *v, mixer_ctrl_t *cp) 847 { 848 struct auich_softc *sc = v; 849 850 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 851 } 852 853 int 854 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 855 { 856 struct auich_softc *sc = v; 857 858 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 859 } 860 861 void * 862 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 863 { 864 struct auich_softc *sc = v; 865 struct auich_dma *p; 866 int error; 867 868 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 869 return (NULL); 870 871 p = malloc(sizeof(*p), pool, flags|M_ZERO); 872 if (p == NULL) 873 return (NULL); 874 875 error = auich_allocmem(sc, size, 0, p); 876 if (error) { 877 free(p, pool); 878 return (NULL); 879 } 880 881 p->next = sc->sc_dmas; 882 sc->sc_dmas = p; 883 884 return (KERNADDR(p)); 885 } 886 887 void 888 auich_freem(void *v, void *ptr, int pool) 889 { 890 struct auich_softc *sc = v; 891 struct auich_dma *p, **pp; 892 893 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 894 if (KERNADDR(p) == ptr) { 895 auich_freemem(sc, p); 896 *pp = p->next; 897 free(p, pool); 898 return; 899 } 900 } 901 } 902 903 size_t 904 auich_round_buffersize(void *v, int direction, size_t size) 905 { 906 907 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 908 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 909 910 return size; 911 } 912 913 paddr_t 914 auich_mappage(void *v, void *mem, off_t off, int prot) 915 { 916 struct auich_softc *sc = v; 917 struct auich_dma *p; 918 919 if (off < 0) 920 return (-1); 921 922 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 923 ; 924 if (!p) 925 return (-1); 926 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 927 off, prot, BUS_DMA_WAITOK)); 928 } 929 930 int 931 auich_get_props(void *v) 932 { 933 struct auich_softc *sc = v; 934 int props; 935 936 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 937 /* 938 * Even if the codec is fixed-rate, set_param() succeeds for any sample 939 * rate because of aurateconv. Applications can't know what rate the 940 * device can process in the case of mmap(). 941 */ 942 if (!IS_FIXED_RATE(sc->codec_if)) 943 props |= AUDIO_PROP_MMAP; 944 return props; 945 } 946 947 int 948 auich_intr(void *v) 949 { 950 struct auich_softc *sc = v; 951 int ret = 0, sts, gsts, i, qptr; 952 953 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 954 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 955 956 if (gsts & ICH_POINT) { 957 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 958 DPRINTF(ICH_DEBUG_DMA, 959 ("auich_intr: osts=0x%x\n", sts)); 960 961 if (sts & ICH_FIFOE) { 962 printf("%s: fifo underrun # %u\n", 963 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 964 } 965 966 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 967 if (sts & (ICH_LVBCI | ICH_CELV)) { 968 struct auich_dmalist *q; 969 970 qptr = sc->ptr_pcmo; 971 972 while (qptr != i) { 973 q = &sc->dmalist_pcmo[qptr]; 974 975 q->base = sc->pcmo_p; 976 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 977 DPRINTF(ICH_DEBUG_DMA, 978 ("auich_intr: %p, %p = %x @ 0x%x\n", 979 &sc->dmalist_pcmo[i], q, 980 sc->pcmo_blksize / 2, sc->pcmo_p)); 981 982 sc->pcmo_p += sc->pcmo_blksize; 983 if (sc->pcmo_p >= sc->pcmo_end) 984 sc->pcmo_p = sc->pcmo_start; 985 986 if (++qptr == ICH_DMALIST_MAX) 987 qptr = 0; 988 } 989 990 sc->ptr_pcmo = qptr; 991 bus_space_write_1(sc->iot, sc->aud_ioh, 992 ICH_PCMO + ICH_LVI, 993 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 994 } 995 996 if (sts & ICH_BCIS && sc->sc_pintr) 997 sc->sc_pintr(sc->sc_parg); 998 999 /* int ack */ 1000 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1001 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1002 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1003 ret++; 1004 } 1005 1006 if (gsts & ICH_PIINT) { 1007 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1008 DPRINTF(ICH_DEBUG_DMA, 1009 ("auich_intr: ists=0x%x\n", sts)); 1010 1011 if (sts & ICH_FIFOE) { 1012 printf("%s: fifo overrun # %u\n", 1013 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1014 } 1015 1016 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1017 if (sts & (ICH_LVBCI | ICH_CELV)) { 1018 struct auich_dmalist *q; 1019 1020 qptr = sc->ptr_pcmi; 1021 1022 while (qptr != i) { 1023 q = &sc->dmalist_pcmi[qptr]; 1024 1025 q->base = sc->pcmi_p; 1026 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1027 DPRINTF(ICH_DEBUG_DMA, 1028 ("auich_intr: %p, %p = %x @ 0x%x\n", 1029 &sc->dmalist_pcmi[i], q, 1030 sc->pcmi_blksize / 2, sc->pcmi_p)); 1031 1032 sc->pcmi_p += sc->pcmi_blksize; 1033 if (sc->pcmi_p >= sc->pcmi_end) 1034 sc->pcmi_p = sc->pcmi_start; 1035 1036 if (++qptr == ICH_DMALIST_MAX) 1037 qptr = 0; 1038 } 1039 1040 sc->ptr_pcmi = qptr; 1041 bus_space_write_1(sc->iot, sc->aud_ioh, 1042 ICH_PCMI + ICH_LVI, 1043 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1044 } 1045 1046 if (sts & ICH_BCIS && sc->sc_rintr) 1047 sc->sc_rintr(sc->sc_rarg); 1048 1049 /* int ack */ 1050 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1051 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1052 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1053 ret++; 1054 } 1055 1056 if (gsts & ICH_MIINT) { 1057 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1058 DPRINTF(ICH_DEBUG_DMA, 1059 ("auich_intr: ists=0x%x\n", sts)); 1060 if (sts & ICH_FIFOE) 1061 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1062 1063 /* TODO mic input dma */ 1064 1065 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1066 } 1067 1068 return ret; 1069 } 1070 1071 int 1072 auich_trigger_output(void *v, void *start, void *end, int blksize, 1073 void (*intr)(void *), void *arg, struct audio_params *param) 1074 { 1075 struct auich_softc *sc = v; 1076 struct auich_dmalist *q; 1077 struct auich_dma *p; 1078 size_t size; 1079 1080 DPRINTF(ICH_DEBUG_DMA, 1081 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1082 start, end, blksize, intr, arg, param)); 1083 1084 sc->sc_pintr = intr; 1085 sc->sc_parg = arg; 1086 1087 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1088 ; 1089 if (!p) { 1090 printf("auich_trigger_output: bad addr %p\n", start); 1091 return (EINVAL); 1092 } 1093 1094 size = (size_t)((caddr_t)end - (caddr_t)start); 1095 1096 /* 1097 * The logic behind this is: 1098 * setup one buffer to play, then LVI dump out the rest 1099 * to the scatter-gather chain. 1100 */ 1101 sc->pcmo_start = DMAADDR(p); 1102 sc->pcmo_p = sc->pcmo_start + blksize; 1103 sc->pcmo_end = sc->pcmo_start + size; 1104 sc->pcmo_blksize = blksize; 1105 1106 sc->ptr_pcmo = 0; 1107 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1108 q->base = sc->pcmo_start; 1109 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1110 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1111 sc->ptr_pcmo = 0; 1112 1113 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1114 sc->sc_cddma + ICH_PCMO_OFF(0)); 1115 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1116 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1117 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1118 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1119 1120 return (0); 1121 } 1122 1123 int 1124 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1125 void *v; 1126 void *start, *end; 1127 int blksize; 1128 void (*intr)(void *); 1129 void *arg; 1130 struct audio_params *param; 1131 { 1132 struct auich_softc *sc = v; 1133 struct auich_dmalist *q; 1134 struct auich_dma *p; 1135 size_t size; 1136 1137 DPRINTF(ICH_DEBUG_DMA, 1138 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1139 start, end, blksize, intr, arg, param)); 1140 1141 sc->sc_rintr = intr; 1142 sc->sc_rarg = arg; 1143 1144 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1145 ; 1146 if (!p) { 1147 printf("auich_trigger_input: bad addr %p\n", start); 1148 return (EINVAL); 1149 } 1150 1151 size = (size_t)((caddr_t)end - (caddr_t)start); 1152 1153 /* 1154 * The logic behind this is: 1155 * setup one buffer to play, then LVI dump out the rest 1156 * to the scatter-gather chain. 1157 */ 1158 sc->pcmi_start = DMAADDR(p); 1159 sc->pcmi_p = sc->pcmi_start + blksize; 1160 sc->pcmi_end = sc->pcmi_start + size; 1161 sc->pcmi_blksize = blksize; 1162 1163 sc->ptr_pcmi = 0; 1164 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1165 q->base = sc->pcmi_start; 1166 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1167 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1168 sc->ptr_pcmi = 0; 1169 1170 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1171 sc->sc_cddma + ICH_PCMI_OFF(0)); 1172 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1173 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1174 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1175 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1176 1177 return (0); 1178 } 1179 1180 int 1181 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1182 struct auich_dma *p) 1183 { 1184 int error; 1185 1186 p->size = size; 1187 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1188 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1189 &p->nsegs, BUS_DMA_NOWAIT); 1190 if (error) 1191 return (error); 1192 1193 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1194 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1195 if (error) 1196 goto free; 1197 1198 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1199 0, BUS_DMA_NOWAIT, &p->map); 1200 if (error) 1201 goto unmap; 1202 1203 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1204 BUS_DMA_NOWAIT); 1205 if (error) 1206 goto destroy; 1207 return (0); 1208 1209 destroy: 1210 bus_dmamap_destroy(sc->dmat, p->map); 1211 unmap: 1212 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1213 free: 1214 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1215 return (error); 1216 } 1217 1218 int 1219 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1220 { 1221 1222 bus_dmamap_unload(sc->dmat, p->map); 1223 bus_dmamap_destroy(sc->dmat, p->map); 1224 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1225 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1226 return (0); 1227 } 1228 1229 int 1230 auich_alloc_cdata(struct auich_softc *sc) 1231 { 1232 bus_dma_segment_t seg; 1233 int error, rseg; 1234 1235 /* 1236 * Allocate the control data structure, and create and load the 1237 * DMA map for it. 1238 */ 1239 if ((error = bus_dmamem_alloc(sc->dmat, 1240 sizeof(struct auich_cdata), 1241 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1242 printf("%s: unable to allocate control data, error = %d\n", 1243 sc->sc_dev.dv_xname, error); 1244 goto fail_0; 1245 } 1246 1247 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1248 sizeof(struct auich_cdata), 1249 (caddr_t *) &sc->sc_cdata, 1250 BUS_DMA_COHERENT)) != 0) { 1251 printf("%s: unable to map control data, error = %d\n", 1252 sc->sc_dev.dv_xname, error); 1253 goto fail_1; 1254 } 1255 1256 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1257 sizeof(struct auich_cdata), 0, 0, 1258 &sc->sc_cddmamap)) != 0) { 1259 printf("%s: unable to create control data DMA map, " 1260 "error = %d\n", sc->sc_dev.dv_xname, error); 1261 goto fail_2; 1262 } 1263 1264 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1265 sc->sc_cdata, sizeof(struct auich_cdata), 1266 NULL, 0)) != 0) { 1267 printf("%s: unable tp load control data DMA map, " 1268 "error = %d\n", sc->sc_dev.dv_xname, error); 1269 goto fail_3; 1270 } 1271 1272 return (0); 1273 1274 fail_3: 1275 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1276 fail_2: 1277 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1278 sizeof(struct auich_cdata)); 1279 fail_1: 1280 bus_dmamem_free(sc->dmat, &seg, rseg); 1281 fail_0: 1282 return (error); 1283 } 1284 1285 void 1286 auich_powerhook(int why, void *addr) 1287 { 1288 struct auich_softc *sc = (struct auich_softc *)addr; 1289 1290 switch (why) { 1291 case PWR_SUSPEND: 1292 case PWR_STANDBY: 1293 /* Power down */ 1294 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1295 sc->sc_suspend = why; 1296 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1297 break; 1298 1299 case PWR_RESUME: 1300 /* Wake up */ 1301 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1302 if (sc->sc_suspend == PWR_RESUME) { 1303 printf("%s: resume without suspend.\n", 1304 sc->sc_dev.dv_xname); 1305 sc->sc_suspend = why; 1306 return; 1307 } 1308 sc->sc_suspend = why; 1309 auich_reset_codec(sc); 1310 DELAY(1000); 1311 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1312 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1313 break; 1314 1315 case PWR_SOFTSUSPEND: 1316 case PWR_SOFTSTANDBY: 1317 case PWR_SOFTRESUME: 1318 break; 1319 } 1320 } 1321 1322 1323 /* -------------------------------------------------------------------- */ 1324 /* Calibrate card (some boards are overclocked and need scaling) */ 1325 1326 unsigned int 1327 auich_calibrate(struct auich_softc *sc) 1328 { 1329 struct timeval t1, t2; 1330 u_int8_t ociv, nciv; 1331 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1332 void *temp_buffer; 1333 struct auich_dma *p; 1334 1335 ac97rate = 48000; 1336 /* 1337 * Grab audio from input for fixed interval and compare how 1338 * much we actually get with what we expect. Interval needs 1339 * to be sufficiently short that no interrupts are 1340 * generated. 1341 */ 1342 1343 /* Setup a buffer */ 1344 bytes = 16000; 1345 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1346 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1347 ; 1348 if (p == NULL) { 1349 printf("auich_calibrate: bad address %p\n", temp_buffer); 1350 return ac97rate; 1351 } 1352 sc->dmalist_pcmi[0].base = DMAADDR(p); 1353 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size) | ICH_DMAF_IOC; 1354 1355 /* 1356 * our data format is stereo, 16 bit so each sample is 4 bytes. 1357 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1358 * we're going to start recording with interrupts disabled and measure 1359 * the time taken for one block to complete. we know the block size, 1360 * we know the time in microseconds, we calculate the sample rate: 1361 * 1362 * actual_rate [bps] = bytes / (time [s] * 4) 1363 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1364 * actual_rate [Hz] = (bytes * 250000) / time [us] 1365 */ 1366 1367 /* prepare */ 1368 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1369 nciv = ociv; 1370 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1371 sc->sc_cddma + ICH_PCMI_OFF(0)); 1372 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1373 (0 - 1) & ICH_LVI_MASK); 1374 1375 /* start */ 1376 microtime(&t1); 1377 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1378 1379 /* wait */ 1380 while (nciv == ociv) { 1381 microtime(&t2); 1382 if (t2.tv_sec - t1.tv_sec > 1) 1383 break; 1384 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1385 ICH_PCMI + ICH_CIV); 1386 } 1387 microtime(&t2); 1388 1389 /* stop */ 1390 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1391 1392 /* reset */ 1393 DELAY(100); 1394 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1395 1396 /* turn time delta into us */ 1397 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1398 1399 auich_freem(sc, temp_buffer, M_DEVBUF); 1400 1401 if (nciv == ociv) { 1402 printf("%s: ac97 link rate calibration timed out after %d us\n", 1403 sc->sc_dev.dv_xname, wait_us); 1404 return ac97rate; 1405 } 1406 1407 actual_48k_rate = (bytes * 250000) / wait_us; 1408 1409 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 1410 ac97rate = actual_48k_rate; 1411 } 1412 1413 if (ac97rate != 48000) { 1414 printf("%s: measured ac97 link rate at %d Hz", 1415 sc->sc_dev.dv_xname, actual_48k_rate); 1416 if (ac97rate != actual_48k_rate) 1417 printf(", will use %d Hz", ac97rate); 1418 printf("\n"); 1419 } 1420 1421 return ac97rate; 1422 } 1423
Indexes created Thu Oct 23 22:10:10 GMT 2025