auich.c revision 1.3.2.11
1 /* $NetBSD: auich.c,v 1.3.2.11 2003/01/17 16:31:38 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * 107 * TODO: 108 * - Add support for the dedicated microphone input. 109 * - 4ch/6ch support. 110 */ 111 112 #include <sys/cdefs.h> 113 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.3.2.11 2003/01/17 16:31:38 thorpej Exp $"); 114 115 #include <sys/param.h> 116 #include <sys/systm.h> 117 #include <sys/kernel.h> 118 #include <sys/malloc.h> 119 #include <sys/device.h> 120 #include <sys/fcntl.h> 121 #include <sys/proc.h> 122 123 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 124 125 #include <dev/pci/pcidevs.h> 126 #include <dev/pci/pcivar.h> 127 #include <dev/pci/auichreg.h> 128 129 #include <sys/audioio.h> 130 #include <dev/audio_if.h> 131 #include <dev/mulaw.h> 132 #include <dev/auconv.h> 133 134 #include <machine/bus.h> 135 136 #include <dev/ic/ac97reg.h> 137 #include <dev/ic/ac97var.h> 138 139 struct auich_dma { 140 bus_dmamap_t map; 141 caddr_t addr; 142 bus_dma_segment_t segs[1]; 143 int nsegs; 144 size_t size; 145 struct auich_dma *next; 146 }; 147 148 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 149 #define KERNADDR(p) ((void *)((p)->addr)) 150 151 struct auich_cdata { 152 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 153 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 154 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 155 }; 156 157 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 158 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 159 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 160 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 161 162 struct auich_softc { 163 struct device sc_dev; 164 void *sc_ih; 165 166 audio_device_t sc_audev; 167 168 bus_space_tag_t iot; 169 bus_space_handle_t mix_ioh; 170 bus_space_handle_t aud_ioh; 171 bus_dma_tag_t dmat; 172 173 struct ac97_codec_if *codec_if; 174 struct ac97_host_if host_if; 175 176 /* DMA scatter-gather lists. */ 177 bus_dmamap_t sc_cddmamap; 178 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 179 180 struct auich_cdata *sc_cdata; 181 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 182 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 183 #define dmalist_mici sc_cdata->ic_dmalist_mici 184 185 int ptr_pcmo, 186 ptr_pcmi, 187 ptr_mici; 188 189 /* i/o buffer pointers */ 190 u_int32_t pcmo_start, pcmo_p, pcmo_end; 191 int pcmo_blksize, pcmo_fifoe; 192 193 u_int32_t pcmi_start, pcmi_p, pcmi_end; 194 int pcmi_blksize, pcmi_fifoe; 195 196 u_int32_t mici_start, mici_p, mici_end; 197 int mici_blksize, mici_fifoe; 198 199 struct auich_dma *sc_dmas; 200 201 int sc_ignore_codecready; 202 /* SiS 7012 hack */ 203 int sc_sample_size; 204 int sc_sts_reg; 205 206 void (*sc_pintr)(void *); 207 void *sc_parg; 208 209 void (*sc_rintr)(void *); 210 void *sc_rarg; 211 212 /* Power Management */ 213 void *sc_powerhook; 214 int sc_suspend; 215 u_int16_t ext_status; 216 }; 217 218 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 219 & AC97_EXT_AUDIO_VRA) 220 221 /* Debug */ 222 #ifdef AUDIO_DEBUG 223 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 224 int auich_debug = 0xfffe; 225 #define ICH_DEBUG_CODECIO 0x0001 226 #define ICH_DEBUG_DMA 0x0002 227 #define ICH_DEBUG_PARAM 0x0004 228 #else 229 #define DPRINTF(x,y) /* nothing */ 230 #endif 231 232 int auich_match(struct device *, struct cfdata *, void *); 233 void auich_attach(struct device *, struct device *, void *); 234 int auich_intr(void *); 235 236 CFATTACH_DECL(auich, sizeof(struct auich_softc), 237 auich_match, auich_attach, NULL, NULL); 238 239 int auich_open(void *, int); 240 void auich_close(void *); 241 int auich_query_encoding(void *, struct audio_encoding *); 242 int auich_set_params(void *, int, int, struct audio_params *, 243 struct audio_params *); 244 int auich_round_blocksize(void *, int); 245 int auich_halt_output(void *); 246 int auich_halt_input(void *); 247 int auich_getdev(void *, struct audio_device *); 248 int auich_set_port(void *, mixer_ctrl_t *); 249 int auich_get_port(void *, mixer_ctrl_t *); 250 int auich_query_devinfo(void *, mixer_devinfo_t *); 251 void *auich_allocm(void *, int, size_t, int, int); 252 void auich_freem(void *, void *, int); 253 size_t auich_round_buffersize(void *, int, size_t); 254 paddr_t auich_mappage(void *, void *, off_t, int); 255 int auich_get_props(void *); 256 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 257 void *, struct audio_params *); 258 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 259 void *, struct audio_params *); 260 261 int auich_alloc_cdata(struct auich_softc *); 262 263 int auich_allocmem(struct auich_softc *, size_t, size_t, 264 struct auich_dma *); 265 int auich_freemem(struct auich_softc *, struct auich_dma *); 266 267 void auich_powerhook(int, void *); 268 int auich_set_rate(struct auich_softc *, int, u_long); 269 void auich_calibrate(struct device *); 270 271 272 struct audio_hw_if auich_hw_if = { 273 auich_open, 274 auich_close, 275 NULL, /* drain */ 276 auich_query_encoding, 277 auich_set_params, 278 auich_round_blocksize, 279 NULL, /* commit_setting */ 280 NULL, /* init_output */ 281 NULL, /* init_input */ 282 NULL, /* start_output */ 283 NULL, /* start_input */ 284 auich_halt_output, 285 auich_halt_input, 286 NULL, /* speaker_ctl */ 287 auich_getdev, 288 NULL, /* getfd */ 289 auich_set_port, 290 auich_get_port, 291 auich_query_devinfo, 292 auich_allocm, 293 auich_freem, 294 auich_round_buffersize, 295 auich_mappage, 296 auich_get_props, 297 auich_trigger_output, 298 auich_trigger_input, 299 NULL, /* dev_ioctl */ 300 }; 301 302 int auich_attach_codec(void *, struct ac97_codec_if *); 303 int auich_read_codec(void *, u_int8_t, u_int16_t *); 304 int auich_write_codec(void *, u_int8_t, u_int16_t); 305 void auich_reset_codec(void *); 306 307 static const struct auich_devtype { 308 int vendor; 309 int product; 310 const char *name; 311 const char *shortname; 312 } auich_devices[] = { 313 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 314 "i82801AA (ICH) AC-97 Audio", "ICH" }, 315 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 316 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, /* i810-L */ 317 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 318 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 319 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 320 "i82440MX AC-97 Audio", "440MX" }, 321 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 322 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, /* i830Mx i845MP/MZ*/ 323 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 324 "i82801DB (ICH4) AC-97 Audio", "ICH4" }, /* i845E i845Gx */ 325 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 326 "SiS 7012 AC-97 Audio", "SiS7012" }, 327 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 328 "nForce MCP AC-97 Audio", "nForce-MCP" }, 329 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 330 "nForce2 MCP-T AC-97 Audio", "nForce-MCP-T" }, 331 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 332 "AMD768 AC-97 Audio", "AMD768" }, 333 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 334 "AMD8111 AC-97 Audio", "AMD8111" }, 335 { 0, 336 NULL, NULL }, 337 }; 338 339 static const struct auich_devtype * 340 auich_lookup(struct pci_attach_args *pa) 341 { 342 const struct auich_devtype *d; 343 344 for (d = auich_devices; d->name != NULL; d++) { 345 if (PCI_VENDOR(pa->pa_id) == d->vendor 346 && PCI_PRODUCT(pa->pa_id) == d->product) 347 return (d); 348 } 349 350 return (NULL); 351 } 352 353 int 354 auich_match(struct device *parent, struct cfdata *match, void *aux) 355 { 356 struct pci_attach_args *pa = aux; 357 358 if (auich_lookup(pa) != NULL) 359 return (1); 360 361 return (0); 362 } 363 364 void 365 auich_attach(struct device *parent, struct device *self, void *aux) 366 { 367 struct auich_softc *sc = (struct auich_softc *)self; 368 struct pci_attach_args *pa = aux; 369 pci_intr_handle_t ih; 370 bus_size_t mix_size, aud_size; 371 pcireg_t csr; 372 const char *intrstr; 373 const struct auich_devtype *d; 374 u_int32_t status; 375 376 d = auich_lookup(pa); 377 if (d == NULL) 378 panic("auich_attach: impossible"); 379 380 printf(": %s\n", d->name); 381 382 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 383 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 384 printf("%s: can't map codec i/o space\n", 385 sc->sc_dev.dv_xname); 386 return; 387 } 388 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 389 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 390 printf("%s: can't map device i/o space\n", 391 sc->sc_dev.dv_xname); 392 return; 393 } 394 sc->dmat = pa->pa_dmat; 395 396 /* enable bus mastering */ 397 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 398 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 399 csr | PCI_COMMAND_MASTER_ENABLE); 400 401 /* Map and establish the interrupt. */ 402 if (pci_intr_map(pa, &ih)) { 403 printf("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 404 return; 405 } 406 intrstr = pci_intr_string(pa->pa_pc, ih); 407 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 408 auich_intr, sc); 409 if (sc->sc_ih == NULL) { 410 printf("%s: can't establish interrupt", sc->sc_dev.dv_xname); 411 if (intrstr != NULL) 412 printf(" at %s", intrstr); 413 printf("\n"); 414 return; 415 } 416 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 417 418 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 419 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 420 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 421 422 /* SiS 7012 needs special handling */ 423 if (d->vendor == PCI_VENDOR_SIS 424 && d->product == PCI_PRODUCT_SIS_7012_AC) { 425 sc->sc_sts_reg = ICH_PICB; 426 sc->sc_sample_size = 1; 427 } else { 428 sc->sc_sts_reg = ICH_STS; 429 sc->sc_sample_size = 2; 430 } 431 /* nForce MCP quirk */ 432 if (d->vendor == PCI_VENDOR_NVIDIA 433 && d->product == PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC) { 434 sc->sc_ignore_codecready = TRUE; 435 } 436 437 438 /* Set up DMA lists. */ 439 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 440 auich_alloc_cdata(sc); 441 442 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 443 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 444 445 /* Reset codec and AC'97 */ 446 auich_reset_codec(sc); 447 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 448 if (!(status & ICH_PCR)) { /* reset failure */ 449 if (d->vendor == PCI_VENDOR_INTEL 450 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) { 451 /* MSI 845G Max never return ICH_PCR */ 452 sc->sc_ignore_codecready = TRUE; 453 } else { 454 return; 455 } 456 } 457 /* Print capabilities though there are no supports for now */ 458 if ((status & ICH_SAMPLE_CAP) == ICH_POM20) 459 printf("%s: 20 bit precision support\n", sc->sc_dev.dv_xname); 460 if ((status & ICH_CHAN_CAP) == ICH_PCM4) 461 printf("%s: 4ch PCM output support\n", sc->sc_dev.dv_xname); 462 if ((status & ICH_CHAN_CAP) == ICH_PCM6) 463 printf("%s: 6ch PCM output support\n", sc->sc_dev.dv_xname); 464 465 sc->host_if.arg = sc; 466 sc->host_if.attach = auich_attach_codec; 467 sc->host_if.read = auich_read_codec; 468 sc->host_if.write = auich_write_codec; 469 sc->host_if.reset = auich_reset_codec; 470 471 if (ac97_attach(&sc->host_if) != 0) 472 return; 473 474 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 475 476 /* Watch for power change */ 477 sc->sc_suspend = PWR_RESUME; 478 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 479 480 if (!IS_FIXED_RATE(sc->codec_if)) { 481 config_interrupts(self, auich_calibrate); 482 } 483 } 484 485 #define ICH_CODECIO_INTERVAL 10 486 int 487 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 488 { 489 struct auich_softc *sc = v; 490 int i; 491 uint32_t status; 492 493 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 494 if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) { 495 printf("auich_read_codec: codec is not ready (0x%x)\n", status); 496 *val = 0xffff; 497 return -1; 498 } 499 /* wait for an access semaphore */ 500 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 501 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 502 DELAY(ICH_CODECIO_INTERVAL)); 503 504 if (i > 0) { 505 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 506 DPRINTF(ICH_DEBUG_CODECIO, 507 ("auich_read_codec(%x, %x)\n", reg, *val)); 508 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 509 if (status & ICH_RCS) { 510 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 511 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 512 *val = 0xffff; 513 } 514 return 0; 515 } else { 516 DPRINTF(ICH_DEBUG_CODECIO, 517 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 518 return -1; 519 } 520 } 521 522 int 523 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 524 { 525 struct auich_softc *sc = v; 526 int i; 527 528 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 529 if (!sc->sc_ignore_codecready 530 && !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) { 531 printf("auich_write_codec: codec is not ready."); 532 return -1; 533 } 534 /* wait for an access semaphore */ 535 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 536 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 537 DELAY(ICH_CODECIO_INTERVAL)); 538 539 if (i > 0) { 540 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 541 return 0; 542 } else { 543 DPRINTF(ICH_DEBUG_CODECIO, 544 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 545 return -1; 546 } 547 } 548 549 int 550 auich_attach_codec(void *v, struct ac97_codec_if *cif) 551 { 552 struct auich_softc *sc = v; 553 554 sc->codec_if = cif; 555 return 0; 556 } 557 558 void 559 auich_reset_codec(void *v) 560 { 561 struct auich_softc *sc = v; 562 int i; 563 uint32_t control; 564 565 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 566 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 567 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 568 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 569 570 for (i = 500000; i-- && 571 !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR); 572 DELAY(1)); /* or ICH_SCR? */ 573 if (i <= 0) 574 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 575 } 576 577 int 578 auich_open(void *v, int flags) 579 { 580 return 0; 581 } 582 583 void 584 auich_close(void *v) 585 { 586 struct auich_softc *sc = v; 587 588 auich_halt_output(sc); 589 auich_halt_input(sc); 590 591 sc->sc_pintr = NULL; 592 sc->sc_rintr = NULL; 593 } 594 595 int 596 auich_query_encoding(void *v, struct audio_encoding *aep) 597 { 598 599 switch (aep->index) { 600 case 0: 601 strcpy(aep->name, AudioEulinear); 602 aep->encoding = AUDIO_ENCODING_ULINEAR; 603 aep->precision = 8; 604 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 605 return (0); 606 case 1: 607 strcpy(aep->name, AudioEmulaw); 608 aep->encoding = AUDIO_ENCODING_ULAW; 609 aep->precision = 8; 610 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 611 return (0); 612 case 2: 613 strcpy(aep->name, AudioEalaw); 614 aep->encoding = AUDIO_ENCODING_ALAW; 615 aep->precision = 8; 616 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 617 return (0); 618 case 3: 619 strcpy(aep->name, AudioEslinear); 620 aep->encoding = AUDIO_ENCODING_SLINEAR; 621 aep->precision = 8; 622 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 623 return (0); 624 case 4: 625 strcpy(aep->name, AudioEslinear_le); 626 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 627 aep->precision = 16; 628 aep->flags = 0; 629 return (0); 630 case 5: 631 strcpy(aep->name, AudioEulinear_le); 632 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 633 aep->precision = 16; 634 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 635 return (0); 636 case 6: 637 strcpy(aep->name, AudioEslinear_be); 638 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 639 aep->precision = 16; 640 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 641 return (0); 642 case 7: 643 strcpy(aep->name, AudioEulinear_be); 644 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 645 aep->precision = 16; 646 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 647 return (0); 648 default: 649 return (EINVAL); 650 } 651 } 652 653 int 654 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 655 { 656 int reg; 657 u_long ratetmp; 658 659 ratetmp = srate; 660 reg = mode == AUMODE_PLAY 661 ? AC97_REG_PCM_FRONT_DAC_RATE : AC97_REG_PCM_LR_ADC_RATE; 662 return sc->codec_if->vtbl->set_rate(sc->codec_if, reg, &ratetmp); 663 } 664 665 int 666 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 667 struct audio_params *rec) 668 { 669 struct auich_softc *sc = v; 670 struct audio_params *p; 671 int mode; 672 673 for (mode = AUMODE_RECORD; mode != -1; 674 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 675 if ((setmode & mode) == 0) 676 continue; 677 678 p = mode == AUMODE_PLAY ? play : rec; 679 if (p == NULL) 680 continue; 681 682 if ((p->sample_rate != 8000) && 683 (p->sample_rate != 11025) && 684 (p->sample_rate != 16000) && 685 (p->sample_rate != 22050) && 686 (p->sample_rate != 32000) && 687 (p->sample_rate != 44100) && 688 (p->sample_rate != 48000)) 689 return (EINVAL); 690 691 p->factor = 1; 692 if (p->precision == 8) 693 p->factor *= 2; 694 695 p->sw_code = NULL; 696 /* setup hardware formats */ 697 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 698 p->hw_precision = 16; 699 700 /* If monaural is requested, aurateconv expands a monaural 701 * stream to stereo. */ 702 if (p->channels < 2) 703 p->hw_channels = 2; 704 705 switch (p->encoding) { 706 case AUDIO_ENCODING_SLINEAR_BE: 707 if (p->precision == 16) { 708 p->sw_code = swap_bytes; 709 } else { 710 if (mode == AUMODE_PLAY) 711 p->sw_code = linear8_to_linear16_le; 712 else 713 p->sw_code = linear16_to_linear8_le; 714 } 715 break; 716 717 case AUDIO_ENCODING_SLINEAR_LE: 718 if (p->precision != 16) { 719 if (mode == AUMODE_PLAY) 720 p->sw_code = linear8_to_linear16_le; 721 else 722 p->sw_code = linear16_to_linear8_le; 723 } 724 break; 725 726 case AUDIO_ENCODING_ULINEAR_BE: 727 if (p->precision == 16) { 728 if (mode == AUMODE_PLAY) 729 p->sw_code = 730 swap_bytes_change_sign16_le; 731 else 732 p->sw_code = 733 change_sign16_swap_bytes_le; 734 } else { 735 if (mode == AUMODE_PLAY) 736 p->sw_code = 737 ulinear8_to_slinear16_le; 738 else 739 p->sw_code = 740 slinear16_to_ulinear8_le; 741 } 742 break; 743 744 case AUDIO_ENCODING_ULINEAR_LE: 745 if (p->precision == 16) { 746 p->sw_code = change_sign16_le; 747 } else { 748 if (mode == AUMODE_PLAY) 749 p->sw_code = 750 ulinear8_to_slinear16_le; 751 else 752 p->sw_code = 753 slinear16_to_ulinear8_le; 754 } 755 break; 756 757 case AUDIO_ENCODING_ULAW: 758 if (mode == AUMODE_PLAY) { 759 p->sw_code = mulaw_to_slinear16_le; 760 } else { 761 p->sw_code = slinear16_to_mulaw_le; 762 } 763 break; 764 765 case AUDIO_ENCODING_ALAW: 766 if (mode == AUMODE_PLAY) { 767 p->sw_code = alaw_to_slinear16_le; 768 } else { 769 p->sw_code = slinear16_to_alaw_le; 770 } 771 break; 772 773 default: 774 return (EINVAL); 775 } 776 777 if (IS_FIXED_RATE(sc->codec_if)) { 778 p->hw_sample_rate = AC97_SINGLE_RATE; 779 /* If hw_sample_rate is changed, aurateconv works. */ 780 } else { 781 if (auich_set_rate(sc, mode, p->sample_rate)) 782 return EINVAL; 783 } 784 } 785 786 return (0); 787 } 788 789 int 790 auich_round_blocksize(void *v, int blk) 791 { 792 793 return (blk & ~0x3f); /* keep good alignment */ 794 } 795 796 int 797 auich_halt_output(void *v) 798 { 799 struct auich_softc *sc = v; 800 801 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 802 803 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 804 805 return (0); 806 } 807 808 int 809 auich_halt_input(void *v) 810 { 811 struct auich_softc *sc = v; 812 813 DPRINTF(ICH_DEBUG_DMA, 814 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 815 816 /* XXX halt both unless known otherwise */ 817 818 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 819 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 820 821 return (0); 822 } 823 824 int 825 auich_getdev(void *v, struct audio_device *adp) 826 { 827 struct auich_softc *sc = v; 828 829 *adp = sc->sc_audev; 830 return (0); 831 } 832 833 int 834 auich_set_port(void *v, mixer_ctrl_t *cp) 835 { 836 struct auich_softc *sc = v; 837 838 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 839 } 840 841 int 842 auich_get_port(void *v, mixer_ctrl_t *cp) 843 { 844 struct auich_softc *sc = v; 845 846 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 847 } 848 849 int 850 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 851 { 852 struct auich_softc *sc = v; 853 854 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 855 } 856 857 void * 858 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 859 { 860 struct auich_softc *sc = v; 861 struct auich_dma *p; 862 int error; 863 864 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 865 return (NULL); 866 867 p = malloc(sizeof(*p), pool, flags|M_ZERO); 868 if (p == NULL) 869 return (NULL); 870 871 error = auich_allocmem(sc, size, 0, p); 872 if (error) { 873 free(p, pool); 874 return (NULL); 875 } 876 877 p->next = sc->sc_dmas; 878 sc->sc_dmas = p; 879 880 return (KERNADDR(p)); 881 } 882 883 void 884 auich_freem(void *v, void *ptr, int pool) 885 { 886 struct auich_softc *sc = v; 887 struct auich_dma *p, **pp; 888 889 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 890 if (KERNADDR(p) == ptr) { 891 auich_freemem(sc, p); 892 *pp = p->next; 893 free(p, pool); 894 return; 895 } 896 } 897 } 898 899 size_t 900 auich_round_buffersize(void *v, int direction, size_t size) 901 { 902 903 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 904 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 905 906 return size; 907 } 908 909 paddr_t 910 auich_mappage(void *v, void *mem, off_t off, int prot) 911 { 912 struct auich_softc *sc = v; 913 struct auich_dma *p; 914 915 if (off < 0) 916 return (-1); 917 918 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 919 ; 920 if (!p) 921 return (-1); 922 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 923 off, prot, BUS_DMA_WAITOK)); 924 } 925 926 int 927 auich_get_props(void *v) 928 { 929 struct auich_softc *sc = v; 930 int props; 931 932 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 933 /* 934 * Even if the codec is fixed-rate, set_param() succeeds for any sample 935 * rate because of aurateconv. Applications can't know what rate the 936 * device can process in the case of mmap(). 937 */ 938 if (!IS_FIXED_RATE(sc->codec_if)) 939 props |= AUDIO_PROP_MMAP; 940 return props; 941 } 942 943 int 944 auich_intr(void *v) 945 { 946 struct auich_softc *sc = v; 947 int ret = 0, sts, gsts, i, qptr; 948 949 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 950 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 951 952 if (gsts & ICH_POINT) { 953 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 954 DPRINTF(ICH_DEBUG_DMA, 955 ("auich_intr: osts=0x%x\n", sts)); 956 957 if (sts & ICH_FIFOE) { 958 printf("%s: fifo underrun # %u\n", 959 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 960 } 961 962 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 963 if (sts & (ICH_LVBCI | ICH_CELV)) { 964 struct auich_dmalist *q; 965 966 qptr = sc->ptr_pcmo; 967 968 while (qptr != i) { 969 q = &sc->dmalist_pcmo[qptr]; 970 971 q->base = sc->pcmo_p; 972 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 973 DPRINTF(ICH_DEBUG_DMA, 974 ("auich_intr: %p, %p = %x @ 0x%x\n", 975 &sc->dmalist_pcmo[i], q, 976 sc->pcmo_blksize / 2, sc->pcmo_p)); 977 978 sc->pcmo_p += sc->pcmo_blksize; 979 if (sc->pcmo_p >= sc->pcmo_end) 980 sc->pcmo_p = sc->pcmo_start; 981 982 if (++qptr == ICH_DMALIST_MAX) 983 qptr = 0; 984 } 985 986 sc->ptr_pcmo = qptr; 987 bus_space_write_1(sc->iot, sc->aud_ioh, 988 ICH_PCMO + ICH_LVI, 989 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 990 } 991 992 if (sts & ICH_BCIS && sc->sc_pintr) 993 sc->sc_pintr(sc->sc_parg); 994 995 /* int ack */ 996 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 997 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 998 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 999 ret++; 1000 } 1001 1002 if (gsts & ICH_PIINT) { 1003 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1004 DPRINTF(ICH_DEBUG_DMA, 1005 ("auich_intr: ists=0x%x\n", sts)); 1006 1007 if (sts & ICH_FIFOE) { 1008 printf("%s: fifo overrun # %u\n", 1009 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1010 } 1011 1012 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1013 if (sts & (ICH_LVBCI | ICH_CELV)) { 1014 struct auich_dmalist *q; 1015 1016 qptr = sc->ptr_pcmi; 1017 1018 while (qptr != i) { 1019 q = &sc->dmalist_pcmi[qptr]; 1020 1021 q->base = sc->pcmi_p; 1022 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1023 DPRINTF(ICH_DEBUG_DMA, 1024 ("auich_intr: %p, %p = %x @ 0x%x\n", 1025 &sc->dmalist_pcmi[i], q, 1026 sc->pcmi_blksize / 2, sc->pcmi_p)); 1027 1028 sc->pcmi_p += sc->pcmi_blksize; 1029 if (sc->pcmi_p >= sc->pcmi_end) 1030 sc->pcmi_p = sc->pcmi_start; 1031 1032 if (++qptr == ICH_DMALIST_MAX) 1033 qptr = 0; 1034 } 1035 1036 sc->ptr_pcmi = qptr; 1037 bus_space_write_1(sc->iot, sc->aud_ioh, 1038 ICH_PCMI + ICH_LVI, 1039 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1040 } 1041 1042 if (sts & ICH_BCIS && sc->sc_rintr) 1043 sc->sc_rintr(sc->sc_rarg); 1044 1045 /* int ack */ 1046 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1047 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1048 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1049 ret++; 1050 } 1051 1052 if (gsts & ICH_MIINT) { 1053 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1054 DPRINTF(ICH_DEBUG_DMA, 1055 ("auich_intr: ists=0x%x\n", sts)); 1056 if (sts & ICH_FIFOE) 1057 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1058 1059 /* TODO mic input dma */ 1060 1061 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1062 } 1063 1064 return ret; 1065 } 1066 1067 int 1068 auich_trigger_output(void *v, void *start, void *end, int blksize, 1069 void (*intr)(void *), void *arg, struct audio_params *param) 1070 { 1071 struct auich_softc *sc = v; 1072 struct auich_dmalist *q; 1073 struct auich_dma *p; 1074 size_t size; 1075 1076 DPRINTF(ICH_DEBUG_DMA, 1077 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1078 start, end, blksize, intr, arg, param)); 1079 1080 sc->sc_pintr = intr; 1081 sc->sc_parg = arg; 1082 1083 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1084 ; 1085 if (!p) { 1086 printf("auich_trigger_output: bad addr %p\n", start); 1087 return (EINVAL); 1088 } 1089 1090 size = (size_t)((caddr_t)end - (caddr_t)start); 1091 1092 /* 1093 * The logic behind this is: 1094 * setup one buffer to play, then LVI dump out the rest 1095 * to the scatter-gather chain. 1096 */ 1097 sc->pcmo_start = DMAADDR(p); 1098 sc->pcmo_p = sc->pcmo_start + blksize; 1099 sc->pcmo_end = sc->pcmo_start + size; 1100 sc->pcmo_blksize = blksize; 1101 1102 sc->ptr_pcmo = 0; 1103 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1104 q->base = sc->pcmo_start; 1105 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1106 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1107 sc->ptr_pcmo = 0; 1108 1109 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1110 sc->sc_cddma + ICH_PCMO_OFF(0)); 1111 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1112 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1113 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1114 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1115 1116 return (0); 1117 } 1118 1119 int 1120 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1121 void *v; 1122 void *start, *end; 1123 int blksize; 1124 void (*intr)(void *); 1125 void *arg; 1126 struct audio_params *param; 1127 { 1128 struct auich_softc *sc = v; 1129 struct auich_dmalist *q; 1130 struct auich_dma *p; 1131 size_t size; 1132 1133 DPRINTF(ICH_DEBUG_DMA, 1134 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1135 start, end, blksize, intr, arg, param)); 1136 1137 sc->sc_rintr = intr; 1138 sc->sc_rarg = arg; 1139 1140 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1141 ; 1142 if (!p) { 1143 printf("auich_trigger_input: bad addr %p\n", start); 1144 return (EINVAL); 1145 } 1146 1147 size = (size_t)((caddr_t)end - (caddr_t)start); 1148 1149 /* 1150 * The logic behind this is: 1151 * setup one buffer to play, then LVI dump out the rest 1152 * to the scatter-gather chain. 1153 */ 1154 sc->pcmi_start = DMAADDR(p); 1155 sc->pcmi_p = sc->pcmi_start + blksize; 1156 sc->pcmi_end = sc->pcmi_start + size; 1157 sc->pcmi_blksize = blksize; 1158 1159 sc->ptr_pcmi = 0; 1160 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1161 q->base = sc->pcmi_start; 1162 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1163 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1164 sc->ptr_pcmi = 0; 1165 1166 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1167 sc->sc_cddma + ICH_PCMI_OFF(0)); 1168 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1169 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1170 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1171 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1172 1173 return (0); 1174 } 1175 1176 int 1177 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1178 struct auich_dma *p) 1179 { 1180 int error; 1181 1182 p->size = size; 1183 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1184 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1185 &p->nsegs, BUS_DMA_NOWAIT); 1186 if (error) 1187 return (error); 1188 1189 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1190 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1191 if (error) 1192 goto free; 1193 1194 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1195 0, BUS_DMA_NOWAIT, &p->map); 1196 if (error) 1197 goto unmap; 1198 1199 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1200 BUS_DMA_NOWAIT); 1201 if (error) 1202 goto destroy; 1203 return (0); 1204 1205 destroy: 1206 bus_dmamap_destroy(sc->dmat, p->map); 1207 unmap: 1208 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1209 free: 1210 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1211 return (error); 1212 } 1213 1214 int 1215 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1216 { 1217 1218 bus_dmamap_unload(sc->dmat, p->map); 1219 bus_dmamap_destroy(sc->dmat, p->map); 1220 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1221 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1222 return (0); 1223 } 1224 1225 int 1226 auich_alloc_cdata(struct auich_softc *sc) 1227 { 1228 bus_dma_segment_t seg; 1229 int error, rseg; 1230 1231 /* 1232 * Allocate the control data structure, and create and load the 1233 * DMA map for it. 1234 */ 1235 if ((error = bus_dmamem_alloc(sc->dmat, 1236 sizeof(struct auich_cdata), 1237 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1238 printf("%s: unable to allocate control data, error = %d\n", 1239 sc->sc_dev.dv_xname, error); 1240 goto fail_0; 1241 } 1242 1243 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1244 sizeof(struct auich_cdata), 1245 (caddr_t *) &sc->sc_cdata, 1246 BUS_DMA_COHERENT)) != 0) { 1247 printf("%s: unable to map control data, error = %d\n", 1248 sc->sc_dev.dv_xname, error); 1249 goto fail_1; 1250 } 1251 1252 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1253 sizeof(struct auich_cdata), 0, 0, 1254 &sc->sc_cddmamap)) != 0) { 1255 printf("%s: unable to create control data DMA map, " 1256 "error = %d\n", sc->sc_dev.dv_xname, error); 1257 goto fail_2; 1258 } 1259 1260 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1261 sc->sc_cdata, sizeof(struct auich_cdata), 1262 NULL, 0)) != 0) { 1263 printf("%s: unable tp load control data DMA map, " 1264 "error = %d\n", sc->sc_dev.dv_xname, error); 1265 goto fail_3; 1266 } 1267 1268 return (0); 1269 1270 fail_3: 1271 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1272 fail_2: 1273 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1274 sizeof(struct auich_cdata)); 1275 fail_1: 1276 bus_dmamem_free(sc->dmat, &seg, rseg); 1277 fail_0: 1278 return (error); 1279 } 1280 1281 void 1282 auich_powerhook(int why, void *addr) 1283 { 1284 struct auich_softc *sc = (struct auich_softc *)addr; 1285 1286 switch (why) { 1287 case PWR_SUSPEND: 1288 case PWR_STANDBY: 1289 /* Power down */ 1290 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1291 sc->sc_suspend = why; 1292 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1293 break; 1294 1295 case PWR_RESUME: 1296 /* Wake up */ 1297 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1298 if (sc->sc_suspend == PWR_RESUME) { 1299 printf("%s: resume without suspend.\n", 1300 sc->sc_dev.dv_xname); 1301 sc->sc_suspend = why; 1302 return; 1303 } 1304 sc->sc_suspend = why; 1305 auich_reset_codec(sc); 1306 DELAY(1000); 1307 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1308 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1309 break; 1310 1311 case PWR_SOFTSUSPEND: 1312 case PWR_SOFTSTANDBY: 1313 case PWR_SOFTRESUME: 1314 break; 1315 } 1316 } 1317 1318 1319 /* -------------------------------------------------------------------- */ 1320 /* Calibrate card (some boards are overclocked and need scaling) */ 1321 1322 void 1323 auich_calibrate(struct device *self) 1324 { 1325 struct auich_softc *sc; 1326 struct timeval t1, t2; 1327 u_int8_t ociv, nciv; 1328 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1329 void *temp_buffer; 1330 struct auich_dma *p; 1331 1332 sc = (struct auich_softc*)self; 1333 /* 1334 * Grab audio from input for fixed interval and compare how 1335 * much we actually get with what we expect. Interval needs 1336 * to be sufficiently short that no interrupts are 1337 * generated. 1338 */ 1339 1340 /* Setup a buffer */ 1341 bytes = 16000; 1342 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1343 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1344 ; 1345 if (p == NULL) { 1346 printf("auich_calibrate: bad address %p\n", temp_buffer); 1347 return; 1348 } 1349 sc->dmalist_pcmi[0].base = DMAADDR(p); 1350 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size) | ICH_DMAF_IOC; 1351 1352 /* 1353 * our data format is stereo, 16 bit so each sample is 4 bytes. 1354 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1355 * we're going to start recording with interrupts disabled and measure 1356 * the time taken for one block to complete. we know the block size, 1357 * we know the time in microseconds, we calculate the sample rate: 1358 * 1359 * actual_rate [bps] = bytes / (time [s] * 4) 1360 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1361 * actual_rate [Hz] = (bytes * 250000) / time [us] 1362 */ 1363 1364 /* prepare */ 1365 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1366 nciv = ociv; 1367 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1368 sc->sc_cddma + ICH_PCMI_OFF(0)); 1369 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1370 (0 - 1) & ICH_LVI_MASK); 1371 1372 /* start */ 1373 microtime(&t1); 1374 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1375 1376 /* wait */ 1377 while (nciv == ociv) { 1378 microtime(&t2); 1379 if (t2.tv_sec - t1.tv_sec > 1) 1380 break; 1381 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1382 ICH_PCMI + ICH_CIV); 1383 } 1384 microtime(&t2); 1385 1386 /* stop */ 1387 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1388 1389 /* reset */ 1390 DELAY(100); 1391 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1392 1393 /* turn time delta into us */ 1394 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1395 1396 auich_freem(sc, temp_buffer, M_DEVBUF); 1397 1398 if (nciv == ociv) { 1399 printf("%s: ac97 link rate calibration timed out after %d us\n", 1400 sc->sc_dev.dv_xname, wait_us); 1401 return; 1402 } 1403 1404 actual_48k_rate = (bytes * 250000U) / wait_us; 1405 1406 if (actual_48k_rate <= 48500) 1407 ac97rate = 48000; 1408 else 1409 ac97rate = actual_48k_rate; 1410 1411 printf("%s: measured ac97 link rate at %d Hz", 1412 sc->sc_dev.dv_xname, actual_48k_rate); 1413 if (ac97rate != actual_48k_rate) 1414 printf(", will use %d Hz", ac97rate); 1415 printf("\n"); 1416 1417 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1418 } 1419
Indexes created Thu Oct 23 18:09:57 GMT 2025