auich.c revision 1.3.2.6
1 /* $NetBSD: auich.c,v 1.3.2.6 2002/08/13 02:19:35 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * 107 * TODO: 108 * - Add support for the microphone input. 109 * - 4ch/6ch support. 110 * - auich_calibrate() is called in auich_open(). It causes about 0.1sec 111 * delay in the first open(). auich_calibrate() should be called in 112 * auich_attach(). However microtime() doesn't work in the attach 113 * stage. 114 */ 115 116 #include <sys/cdefs.h> 117 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.3.2.6 2002/08/13 02:19:35 nathanw Exp $"); 118 119 #include <sys/param.h> 120 #include <sys/systm.h> 121 #include <sys/kernel.h> 122 #include <sys/malloc.h> 123 #include <sys/device.h> 124 #include <sys/fcntl.h> 125 #include <sys/proc.h> 126 127 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 128 129 #include <dev/pci/pcidevs.h> 130 #include <dev/pci/pcivar.h> 131 #include <dev/pci/auichreg.h> 132 133 #include <sys/audioio.h> 134 #include <dev/audio_if.h> 135 #include <dev/mulaw.h> 136 #include <dev/auconv.h> 137 138 #include <machine/bus.h> 139 140 #include <dev/ic/ac97reg.h> 141 #include <dev/ic/ac97var.h> 142 143 struct auich_dma { 144 bus_dmamap_t map; 145 caddr_t addr; 146 bus_dma_segment_t segs[1]; 147 int nsegs; 148 size_t size; 149 struct auich_dma *next; 150 }; 151 152 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 153 #define KERNADDR(p) ((void *)((p)->addr)) 154 155 struct auich_cdata { 156 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 157 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 158 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 159 }; 160 161 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 162 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 163 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 164 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 165 166 struct auich_softc { 167 struct device sc_dev; 168 void *sc_ih; 169 170 audio_device_t sc_audev; 171 172 bus_space_tag_t iot; 173 bus_space_handle_t mix_ioh; 174 bus_space_handle_t aud_ioh; 175 bus_dma_tag_t dmat; 176 177 struct ac97_codec_if *codec_if; 178 struct ac97_host_if host_if; 179 180 /* DMA scatter-gather lists. */ 181 bus_dmamap_t sc_cddmamap; 182 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 183 184 struct auich_cdata *sc_cdata; 185 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 186 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 187 #define dmalist_mici sc_cdata->ic_dmalist_mici 188 189 int ptr_pcmo, 190 ptr_pcmi, 191 ptr_mici; 192 193 /* i/o buffer pointers */ 194 u_int32_t pcmo_start, pcmo_p, pcmo_end; 195 int pcmo_blksize, pcmo_fifoe; 196 197 u_int32_t pcmi_start, pcmi_p, pcmi_end; 198 int pcmi_blksize, pcmi_fifoe; 199 200 u_int32_t mici_start, mici_p, mici_end; 201 int mici_blksize, mici_fifoe; 202 203 struct auich_dma *sc_dmas; 204 205 int sc_fixed_rate; 206 int sc_ac97rate; 207 int sc_ignore_codecready; 208 209 /* SiS 7012 hack */ 210 int sc_sample_size; 211 int sc_sts_reg; 212 213 void (*sc_pintr)(void *); 214 void *sc_parg; 215 216 void (*sc_rintr)(void *); 217 void *sc_rarg; 218 219 /* Power Management */ 220 void *sc_powerhook; 221 int sc_suspend; 222 u_int16_t ext_status; 223 }; 224 225 #define FIXED_RATE 48000 226 227 /* Debug */ 228 #ifdef AUDIO_DEBUG 229 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 230 int auich_debug = 0xfffe; 231 #define ICH_DEBUG_CODECIO 0x0001 232 #define ICH_DEBUG_DMA 0x0002 233 #define ICH_DEBUG_PARAM 0x0004 234 #else 235 #define DPRINTF(x,y) /* nothing */ 236 #endif 237 238 int auich_match(struct device *, struct cfdata *, void *); 239 void auich_attach(struct device *, struct device *, void *); 240 int auich_intr(void *); 241 242 struct cfattach auich_ca = { 243 sizeof(struct auich_softc), auich_match, auich_attach 244 }; 245 246 int auich_open(void *, int); 247 void auich_close(void *); 248 int auich_query_encoding(void *, struct audio_encoding *); 249 int auich_set_params(void *, int, int, struct audio_params *, 250 struct audio_params *); 251 int auich_round_blocksize(void *, int); 252 int auich_halt_output(void *); 253 int auich_halt_input(void *); 254 int auich_getdev(void *, struct audio_device *); 255 int auich_set_port(void *, mixer_ctrl_t *); 256 int auich_get_port(void *, mixer_ctrl_t *); 257 int auich_query_devinfo(void *, mixer_devinfo_t *); 258 void *auich_allocm(void *, int, size_t, int, int); 259 void auich_freem(void *, void *, int); 260 size_t auich_round_buffersize(void *, int, size_t); 261 paddr_t auich_mappage(void *, void *, off_t, int); 262 int auich_get_props(void *); 263 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 264 void *, struct audio_params *); 265 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 266 void *, struct audio_params *); 267 268 int auich_alloc_cdata(struct auich_softc *); 269 270 int auich_allocmem(struct auich_softc *, size_t, size_t, 271 struct auich_dma *); 272 int auich_freemem(struct auich_softc *, struct auich_dma *); 273 274 void auich_powerhook(int, void *); 275 int auich_set_rate(struct auich_softc *sc, int mode, uint srate); 276 unsigned int auich_calibrate(struct auich_softc *sc); 277 278 279 struct audio_hw_if auich_hw_if = { 280 auich_open, 281 auich_close, 282 NULL, /* drain */ 283 auich_query_encoding, 284 auich_set_params, 285 auich_round_blocksize, 286 NULL, /* commit_setting */ 287 NULL, /* init_output */ 288 NULL, /* init_input */ 289 NULL, /* start_output */ 290 NULL, /* start_input */ 291 auich_halt_output, 292 auich_halt_input, 293 NULL, /* speaker_ctl */ 294 auich_getdev, 295 NULL, /* getfd */ 296 auich_set_port, 297 auich_get_port, 298 auich_query_devinfo, 299 auich_allocm, 300 auich_freem, 301 auich_round_buffersize, 302 auich_mappage, 303 auich_get_props, 304 auich_trigger_output, 305 auich_trigger_input, 306 NULL, /* dev_ioctl */ 307 }; 308 309 int auich_attach_codec(void *, struct ac97_codec_if *); 310 int auich_read_codec(void *, u_int8_t, u_int16_t *); 311 int auich_write_codec(void *, u_int8_t, u_int16_t); 312 void auich_reset_codec(void *); 313 314 static const struct auich_devtype { 315 int vendor; 316 int product; 317 const char *name; 318 const char *shortname; 319 } auich_devices[] = { 320 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 321 "i82801AA (ICH) AC-97 Audio", "ICH" }, 322 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 323 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, /* i810-L */ 324 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 325 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 326 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 327 "i82440MX AC-97 Audio", "440MX" }, 328 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 329 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, /* i830Mx i845MP/MZ*/ 330 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 331 "i82801DB (ICH4) AC-97 Audio", "ICH4" }, /* i845E i845Gx */ 332 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 333 "SiS 7012 AC-97 Audio", "SiS7012" }, 334 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 335 "nForce MCP AC-97 Audio", "nForce-MCP" }, 336 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 337 "AMD768 AC-97 Audio", "AMD768" }, 338 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 339 "AMD8111 AC-97 Audio", "AMD8111" }, 340 { 0, 341 NULL, NULL }, 342 }; 343 344 static const struct auich_devtype * 345 auich_lookup(struct pci_attach_args *pa) 346 { 347 const struct auich_devtype *d; 348 349 for (d = auich_devices; d->name != NULL; d++) { 350 if (PCI_VENDOR(pa->pa_id) == d->vendor 351 && PCI_PRODUCT(pa->pa_id) == d->product) 352 return (d); 353 } 354 355 return (NULL); 356 } 357 358 int 359 auich_match(struct device *parent, struct cfdata *match, void *aux) 360 { 361 struct pci_attach_args *pa = aux; 362 363 if (auich_lookup(pa) != NULL) 364 return (1); 365 366 return (0); 367 } 368 369 void 370 auich_attach(struct device *parent, struct device *self, void *aux) 371 { 372 struct auich_softc *sc = (struct auich_softc *)self; 373 struct pci_attach_args *pa = aux; 374 pci_intr_handle_t ih; 375 bus_size_t mix_size, aud_size; 376 pcireg_t csr; 377 const char *intrstr; 378 const struct auich_devtype *d; 379 u_int16_t ext_id, ext_status; 380 u_int32_t status; 381 382 d = auich_lookup(pa); 383 if (d == NULL) 384 panic("auich_attach: impossible"); 385 386 printf(": %s\n", d->name); 387 388 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 389 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 390 printf("%s: can't map codec i/o space\n", 391 sc->sc_dev.dv_xname); 392 return; 393 } 394 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 395 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 396 printf("%s: can't map device i/o space\n", 397 sc->sc_dev.dv_xname); 398 return; 399 } 400 sc->dmat = pa->pa_dmat; 401 402 /* enable bus mastering */ 403 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 404 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 405 csr | PCI_COMMAND_MASTER_ENABLE); 406 407 /* Map and establish the interrupt. */ 408 if (pci_intr_map(pa, &ih)) { 409 printf("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 410 return; 411 } 412 intrstr = pci_intr_string(pa->pa_pc, ih); 413 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 414 auich_intr, sc); 415 if (sc->sc_ih == NULL) { 416 printf("%s: can't establish interrupt", sc->sc_dev.dv_xname); 417 if (intrstr != NULL) 418 printf(" at %s", intrstr); 419 printf("\n"); 420 return; 421 } 422 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 423 424 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 425 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 426 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 427 428 /* SiS 7012 needs special handling */ 429 if (d->vendor == PCI_VENDOR_SIS 430 && d->product == PCI_PRODUCT_SIS_7012_AC) { 431 sc->sc_sts_reg = ICH_PICB; 432 sc->sc_sample_size = 1; 433 } else { 434 sc->sc_sts_reg = ICH_STS; 435 sc->sc_sample_size = 2; 436 } 437 438 /* Set up DMA lists. */ 439 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 440 auich_alloc_cdata(sc); 441 442 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 443 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 444 445 /* Reset codec and AC'97 */ 446 auich_reset_codec(sc); 447 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 448 if (!(status & ICH_PCR)) { /* reset failure */ 449 if (d->vendor == PCI_VENDOR_INTEL 450 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) { 451 /* MSI 845G Max never return ICH_PCR */ 452 sc->sc_ignore_codecready = TRUE; 453 } else { 454 return; 455 } 456 } 457 /* Print capabilities though there are no supports for now */ 458 if ((status & ICH_SAMPLE_CAP) == ICH_POM20) 459 printf("%s: 20 bit precision support\n", sc->sc_dev.dv_xname); 460 if ((status & ICH_CHAN_CAP) == ICH_PCM4) 461 printf("%s: 4ch PCM output support\n", sc->sc_dev.dv_xname); 462 if ((status & ICH_CHAN_CAP) == ICH_PCM6) 463 printf("%s: 6ch PCM output support\n", sc->sc_dev.dv_xname); 464 465 sc->host_if.arg = sc; 466 sc->host_if.attach = auich_attach_codec; 467 sc->host_if.read = auich_read_codec; 468 sc->host_if.write = auich_write_codec; 469 sc->host_if.reset = auich_reset_codec; 470 471 if (ac97_attach(&sc->host_if) != 0) 472 return; 473 474 auich_read_codec(sc, AC97_REG_EXTENDED_ID, &ext_id); 475 if ((ext_id & (AC97_CODEC_DOES_VRA | AC97_CODEC_DOES_MICVRA)) != 0) { 476 auich_read_codec(sc, AC97_REG_EXTENDED_STATUS, &ext_status); 477 if ((ext_id & AC97_CODEC_DOES_VRA) !=0) 478 ext_status |= AC97_ENAB_VRA; 479 if ((ext_id & AC97_CODEC_DOES_MICVRA) !=0) 480 ext_status |= AC97_ENAB_MICVRA; 481 auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, ext_status); 482 483 /* so it claims to do variable rate, let's make sure */ 484 sc->sc_ac97rate = FIXED_RATE; 485 if (auich_set_rate(sc, AUMODE_PLAY, 44100) == 44100) 486 sc->sc_fixed_rate = 0; 487 else 488 sc->sc_fixed_rate = FIXED_RATE; 489 sc->sc_ac97rate = 0; 490 } else { 491 sc->sc_fixed_rate = FIXED_RATE; 492 } 493 if (sc->sc_fixed_rate) 494 printf("%s: warning, fixed rate codec\n", sc->sc_dev.dv_xname); 495 496 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 497 498 /* Watch for power change */ 499 sc->sc_suspend = PWR_RESUME; 500 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 501 } 502 503 #define ICH_CODECIO_INTERVAL 10 504 int 505 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 506 { 507 struct auich_softc *sc = v; 508 int i; 509 uint32_t status; 510 511 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 512 if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) { 513 printf("auich_read_codec: codec is not ready (0x%x)\n", status); 514 *val = 0xffff; 515 return -1; 516 } 517 /* wait for an access semaphore */ 518 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 519 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 520 DELAY(ICH_CODECIO_INTERVAL)); 521 522 if (i > 0) { 523 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 524 DPRINTF(ICH_DEBUG_CODECIO, 525 ("auich_read_codec(%x, %x)\n", reg, *val)); 526 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 527 if (status & ICH_RCS) { 528 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 529 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 530 *val = 0xffff; 531 } 532 return 0; 533 } else { 534 DPRINTF(ICH_DEBUG_CODECIO, 535 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 536 return -1; 537 } 538 } 539 540 int 541 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 542 { 543 struct auich_softc *sc = v; 544 int i; 545 546 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 547 if (!sc->sc_ignore_codecready 548 && !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) { 549 printf("auich_write_codec: codec is not ready."); 550 return -1; 551 } 552 /* wait for an access semaphore */ 553 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 554 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 555 DELAY(ICH_CODECIO_INTERVAL)); 556 557 if (i > 0) { 558 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 559 return 0; 560 } else { 561 DPRINTF(ICH_DEBUG_CODECIO, 562 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 563 return -1; 564 } 565 } 566 567 int 568 auich_attach_codec(void *v, struct ac97_codec_if *cif) 569 { 570 struct auich_softc *sc = v; 571 572 sc->codec_if = cif; 573 return 0; 574 } 575 576 void 577 auich_reset_codec(void *v) 578 { 579 struct auich_softc *sc = v; 580 int i; 581 uint32_t control; 582 583 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 584 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 585 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 586 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 587 588 for (i = 500000; i-- && 589 !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR); 590 DELAY(1)); /* or ICH_SCR? */ 591 if (i <= 0) 592 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 593 } 594 595 int 596 auich_open(void *v, int flags) 597 { 598 struct auich_softc *sc = v; 599 600 if (!sc->sc_fixed_rate && sc->sc_ac97rate == 0) 601 sc->sc_ac97rate = auich_calibrate(sc); 602 return 0; 603 } 604 605 void 606 auich_close(void *v) 607 { 608 struct auich_softc *sc = v; 609 610 auich_halt_output(sc); 611 auich_halt_input(sc); 612 613 sc->sc_pintr = NULL; 614 sc->sc_rintr = NULL; 615 } 616 617 int 618 auich_query_encoding(void *v, struct audio_encoding *aep) 619 { 620 621 switch (aep->index) { 622 case 0: 623 strcpy(aep->name, AudioEulinear); 624 aep->encoding = AUDIO_ENCODING_ULINEAR; 625 aep->precision = 8; 626 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 627 return (0); 628 case 1: 629 strcpy(aep->name, AudioEmulaw); 630 aep->encoding = AUDIO_ENCODING_ULAW; 631 aep->precision = 8; 632 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 633 return (0); 634 case 2: 635 strcpy(aep->name, AudioEalaw); 636 aep->encoding = AUDIO_ENCODING_ALAW; 637 aep->precision = 8; 638 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 639 return (0); 640 case 3: 641 strcpy(aep->name, AudioEslinear); 642 aep->encoding = AUDIO_ENCODING_SLINEAR; 643 aep->precision = 8; 644 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 645 return (0); 646 case 4: 647 strcpy(aep->name, AudioEslinear_le); 648 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 649 aep->precision = 16; 650 aep->flags = 0; 651 return (0); 652 case 5: 653 strcpy(aep->name, AudioEulinear_le); 654 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 655 aep->precision = 16; 656 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 657 return (0); 658 case 6: 659 strcpy(aep->name, AudioEslinear_be); 660 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 661 aep->precision = 16; 662 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 663 return (0); 664 case 7: 665 strcpy(aep->name, AudioEulinear_be); 666 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 667 aep->precision = 16; 668 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 669 return (0); 670 default: 671 return (EINVAL); 672 } 673 } 674 675 int 676 auich_set_rate(struct auich_softc *sc, int mode, uint srate) 677 { 678 u_int16_t val, rate, inout; 679 u_int32_t rvalue; 680 681 inout = mode == AUMODE_PLAY ? ICH_PM_PCMO : ICH_PM_PCMI; 682 683 auich_read_codec(sc, AC97_REG_POWER, &val); 684 auich_write_codec(sc, AC97_REG_POWER, val | inout); 685 686 rvalue = srate * FIXED_RATE / sc->sc_ac97rate; 687 if (mode == AUMODE_PLAY) { 688 auich_write_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, rvalue); 689 auich_read_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, &rate); 690 } else { 691 auich_write_codec(sc, AC97_REG_PCM_LR_ADC_RATE, rvalue); 692 auich_read_codec(sc, AC97_REG_PCM_LR_ADC_RATE, &rate); 693 } 694 695 auich_write_codec(sc, AC97_REG_POWER, val); 696 697 rvalue = rate * sc->sc_ac97rate / FIXED_RATE; 698 return rvalue; 699 } 700 701 int 702 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 703 struct audio_params *rec) 704 { 705 struct auich_softc *sc = v; 706 struct audio_params *p; 707 int mode; 708 709 for (mode = AUMODE_RECORD; mode != -1; 710 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 711 if ((setmode & mode) == 0) 712 continue; 713 714 p = mode == AUMODE_PLAY ? play : rec; 715 if (p == NULL) 716 continue; 717 718 if ((p->sample_rate != 8000) && 719 (p->sample_rate != 11025) && 720 (p->sample_rate != 16000) && 721 (p->sample_rate != 22050) && 722 (p->sample_rate != 32000) && 723 (p->sample_rate != 44100) && 724 (p->sample_rate != 48000)) 725 return (EINVAL); 726 727 p->factor = 1; 728 if (p->precision == 8) 729 p->factor *= 2; 730 731 p->sw_code = NULL; 732 /* setup hardware formats */ 733 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 734 p->hw_precision = 16; 735 736 /* If manaural is requested, aurateconv expands a monaural 737 * stream to stereo. */ 738 if (p->channels < 2) 739 p->hw_channels = 2; 740 741 switch (p->encoding) { 742 case AUDIO_ENCODING_SLINEAR_BE: 743 if (p->precision == 16) { 744 p->sw_code = swap_bytes; 745 } else { 746 if (mode == AUMODE_PLAY) 747 p->sw_code = linear8_to_linear16_le; 748 else 749 p->sw_code = linear16_to_linear8_le; 750 } 751 break; 752 753 case AUDIO_ENCODING_SLINEAR_LE: 754 if (p->precision != 16) { 755 if (mode == AUMODE_PLAY) 756 p->sw_code = linear8_to_linear16_le; 757 else 758 p->sw_code = linear16_to_linear8_le; 759 } 760 break; 761 762 case AUDIO_ENCODING_ULINEAR_BE: 763 if (p->precision == 16) { 764 if (mode == AUMODE_PLAY) 765 p->sw_code = 766 swap_bytes_change_sign16_le; 767 else 768 p->sw_code = 769 change_sign16_swap_bytes_le; 770 } else { 771 if (mode == AUMODE_PLAY) 772 p->sw_code = 773 ulinear8_to_slinear16_le; 774 else 775 p->sw_code = 776 slinear16_to_ulinear8_le; 777 } 778 break; 779 780 case AUDIO_ENCODING_ULINEAR_LE: 781 if (p->precision == 16) { 782 p->sw_code = change_sign16_le; 783 } else { 784 if (mode == AUMODE_PLAY) 785 p->sw_code = 786 ulinear8_to_slinear16_le; 787 else 788 p->sw_code = 789 slinear16_to_ulinear8_le; 790 } 791 break; 792 793 case AUDIO_ENCODING_ULAW: 794 if (mode == AUMODE_PLAY) { 795 p->sw_code = mulaw_to_slinear16_le; 796 } else { 797 p->sw_code = slinear16_to_mulaw_le; 798 } 799 break; 800 801 case AUDIO_ENCODING_ALAW: 802 if (mode == AUMODE_PLAY) { 803 p->sw_code = alaw_to_slinear16_le; 804 } else { 805 p->sw_code = slinear16_to_alaw_le; 806 } 807 break; 808 809 default: 810 return (EINVAL); 811 } 812 813 if (sc->sc_fixed_rate) { 814 p->hw_sample_rate = sc->sc_fixed_rate; 815 } else { 816 p->hw_sample_rate = auich_set_rate(sc, mode, 817 p->sample_rate); 818 } 819 /* If hw_sample_rate is different from sample_rate, aurateconv 820 * works. */ 821 } 822 823 return (0); 824 } 825 826 int 827 auich_round_blocksize(void *v, int blk) 828 { 829 830 return (blk & ~0x3f); /* keep good alignment */ 831 } 832 833 int 834 auich_halt_output(void *v) 835 { 836 struct auich_softc *sc = v; 837 838 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 839 840 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 841 842 return (0); 843 } 844 845 int 846 auich_halt_input(void *v) 847 { 848 struct auich_softc *sc = v; 849 850 DPRINTF(ICH_DEBUG_DMA, 851 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 852 853 /* XXX halt both unless known otherwise */ 854 855 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 856 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 857 858 return (0); 859 } 860 861 int 862 auich_getdev(void *v, struct audio_device *adp) 863 { 864 struct auich_softc *sc = v; 865 866 *adp = sc->sc_audev; 867 return (0); 868 } 869 870 int 871 auich_set_port(void *v, mixer_ctrl_t *cp) 872 { 873 struct auich_softc *sc = v; 874 875 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 876 } 877 878 int 879 auich_get_port(void *v, mixer_ctrl_t *cp) 880 { 881 struct auich_softc *sc = v; 882 883 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 884 } 885 886 int 887 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 888 { 889 struct auich_softc *sc = v; 890 891 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 892 } 893 894 void * 895 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 896 { 897 struct auich_softc *sc = v; 898 struct auich_dma *p; 899 int error; 900 901 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 902 return (NULL); 903 904 p = malloc(sizeof(*p), pool, flags|M_ZERO); 905 if (p == NULL) 906 return (NULL); 907 908 error = auich_allocmem(sc, size, 0, p); 909 if (error) { 910 free(p, pool); 911 return (NULL); 912 } 913 914 p->next = sc->sc_dmas; 915 sc->sc_dmas = p; 916 917 return (KERNADDR(p)); 918 } 919 920 void 921 auich_freem(void *v, void *ptr, int pool) 922 { 923 struct auich_softc *sc = v; 924 struct auich_dma *p, **pp; 925 926 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 927 if (KERNADDR(p) == ptr) { 928 auich_freemem(sc, p); 929 *pp = p->next; 930 free(p, pool); 931 return; 932 } 933 } 934 } 935 936 size_t 937 auich_round_buffersize(void *v, int direction, size_t size) 938 { 939 940 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 941 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 942 943 return size; 944 } 945 946 paddr_t 947 auich_mappage(void *v, void *mem, off_t off, int prot) 948 { 949 struct auich_softc *sc = v; 950 struct auich_dma *p; 951 952 if (off < 0) 953 return (-1); 954 955 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 956 ; 957 if (!p) 958 return (-1); 959 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 960 off, prot, BUS_DMA_WAITOK)); 961 } 962 963 int 964 auich_get_props(void *v) 965 { 966 967 return (AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | 968 AUDIO_PROP_FULLDUPLEX); 969 } 970 971 int 972 auich_intr(void *v) 973 { 974 struct auich_softc *sc = v; 975 int ret = 0, sts, gsts, i, qptr; 976 977 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 978 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 979 980 if (gsts & ICH_POINT) { 981 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 982 DPRINTF(ICH_DEBUG_DMA, 983 ("auich_intr: osts=0x%x\n", sts)); 984 985 if (sts & ICH_FIFOE) { 986 printf("%s: fifo underrun # %u\n", 987 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 988 } 989 990 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 991 if (sts & (ICH_LVBCI | ICH_CELV)) { 992 struct auich_dmalist *q; 993 994 qptr = sc->ptr_pcmo; 995 996 while (qptr != i) { 997 q = &sc->dmalist_pcmo[qptr]; 998 999 q->base = sc->pcmo_p; 1000 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1001 DPRINTF(ICH_DEBUG_DMA, 1002 ("auich_intr: %p, %p = %x @ 0x%x\n", 1003 &sc->dmalist_pcmo[i], q, 1004 sc->pcmo_blksize / 2, sc->pcmo_p)); 1005 1006 sc->pcmo_p += sc->pcmo_blksize; 1007 if (sc->pcmo_p >= sc->pcmo_end) 1008 sc->pcmo_p = sc->pcmo_start; 1009 1010 if (++qptr == ICH_DMALIST_MAX) 1011 qptr = 0; 1012 } 1013 1014 sc->ptr_pcmo = qptr; 1015 bus_space_write_1(sc->iot, sc->aud_ioh, 1016 ICH_PCMO + ICH_LVI, 1017 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1018 } 1019 1020 if (sts & ICH_BCIS && sc->sc_pintr) 1021 sc->sc_pintr(sc->sc_parg); 1022 1023 /* int ack */ 1024 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1025 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1026 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1027 ret++; 1028 } 1029 1030 if (gsts & ICH_PIINT) { 1031 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1032 DPRINTF(ICH_DEBUG_DMA, 1033 ("auich_intr: ists=0x%x\n", sts)); 1034 1035 if (sts & ICH_FIFOE) { 1036 printf("%s: fifo overrun # %u\n", 1037 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1038 } 1039 1040 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1041 if (sts & (ICH_LVBCI | ICH_CELV)) { 1042 struct auich_dmalist *q; 1043 1044 qptr = sc->ptr_pcmi; 1045 1046 while (qptr != i) { 1047 q = &sc->dmalist_pcmi[qptr]; 1048 1049 q->base = sc->pcmi_p; 1050 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1051 DPRINTF(ICH_DEBUG_DMA, 1052 ("auich_intr: %p, %p = %x @ 0x%x\n", 1053 &sc->dmalist_pcmi[i], q, 1054 sc->pcmi_blksize / 2, sc->pcmi_p)); 1055 1056 sc->pcmi_p += sc->pcmi_blksize; 1057 if (sc->pcmi_p >= sc->pcmi_end) 1058 sc->pcmi_p = sc->pcmi_start; 1059 1060 if (++qptr == ICH_DMALIST_MAX) 1061 qptr = 0; 1062 } 1063 1064 sc->ptr_pcmi = qptr; 1065 bus_space_write_1(sc->iot, sc->aud_ioh, 1066 ICH_PCMI + ICH_LVI, 1067 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1068 } 1069 1070 if (sts & ICH_BCIS && sc->sc_rintr) 1071 sc->sc_rintr(sc->sc_rarg); 1072 1073 /* int ack */ 1074 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1075 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1076 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1077 ret++; 1078 } 1079 1080 if (gsts & ICH_MIINT) { 1081 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1082 DPRINTF(ICH_DEBUG_DMA, 1083 ("auich_intr: ists=0x%x\n", sts)); 1084 if (sts & ICH_FIFOE) 1085 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1086 1087 /* TODO mic input dma */ 1088 1089 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1090 } 1091 1092 return ret; 1093 } 1094 1095 int 1096 auich_trigger_output(void *v, void *start, void *end, int blksize, 1097 void (*intr)(void *), void *arg, struct audio_params *param) 1098 { 1099 struct auich_softc *sc = v; 1100 struct auich_dmalist *q; 1101 struct auich_dma *p; 1102 size_t size; 1103 1104 DPRINTF(ICH_DEBUG_DMA, 1105 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1106 start, end, blksize, intr, arg, param)); 1107 1108 sc->sc_pintr = intr; 1109 sc->sc_parg = arg; 1110 1111 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1112 ; 1113 if (!p) { 1114 printf("auich_trigger_output: bad addr %p\n", start); 1115 return (EINVAL); 1116 } 1117 1118 size = (size_t)((caddr_t)end - (caddr_t)start); 1119 1120 /* 1121 * The logic behind this is: 1122 * setup one buffer to play, then LVI dump out the rest 1123 * to the scatter-gather chain. 1124 */ 1125 sc->pcmo_start = DMAADDR(p); 1126 sc->pcmo_p = sc->pcmo_start + blksize; 1127 sc->pcmo_end = sc->pcmo_start + size; 1128 sc->pcmo_blksize = blksize; 1129 1130 sc->ptr_pcmo = 0; 1131 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1132 q->base = sc->pcmo_start; 1133 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1134 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1135 sc->ptr_pcmo = 0; 1136 1137 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1138 sc->sc_cddma + ICH_PCMO_OFF(0)); 1139 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1140 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1141 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1142 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1143 1144 return (0); 1145 } 1146 1147 int 1148 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1149 void *v; 1150 void *start, *end; 1151 int blksize; 1152 void (*intr)(void *); 1153 void *arg; 1154 struct audio_params *param; 1155 { 1156 struct auich_softc *sc = v; 1157 struct auich_dmalist *q; 1158 struct auich_dma *p; 1159 size_t size; 1160 1161 DPRINTF(ICH_DEBUG_DMA, 1162 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1163 start, end, blksize, intr, arg, param)); 1164 1165 sc->sc_rintr = intr; 1166 sc->sc_rarg = arg; 1167 1168 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1169 ; 1170 if (!p) { 1171 printf("auich_trigger_input: bad addr %p\n", start); 1172 return (EINVAL); 1173 } 1174 1175 size = (size_t)((caddr_t)end - (caddr_t)start); 1176 1177 /* 1178 * The logic behind this is: 1179 * setup one buffer to play, then LVI dump out the rest 1180 * to the scatter-gather chain. 1181 */ 1182 sc->pcmi_start = DMAADDR(p); 1183 sc->pcmi_p = sc->pcmi_start + blksize; 1184 sc->pcmi_end = sc->pcmi_start + size; 1185 sc->pcmi_blksize = blksize; 1186 1187 sc->ptr_pcmi = 0; 1188 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1189 q->base = sc->pcmi_start; 1190 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1191 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1192 sc->ptr_pcmi = 0; 1193 1194 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1195 sc->sc_cddma + ICH_PCMI_OFF(0)); 1196 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1197 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1198 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1199 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1200 1201 return (0); 1202 } 1203 1204 int 1205 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1206 struct auich_dma *p) 1207 { 1208 int error; 1209 1210 p->size = size; 1211 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1212 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1213 &p->nsegs, BUS_DMA_NOWAIT); 1214 if (error) 1215 return (error); 1216 1217 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1218 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1219 if (error) 1220 goto free; 1221 1222 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1223 0, BUS_DMA_NOWAIT, &p->map); 1224 if (error) 1225 goto unmap; 1226 1227 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1228 BUS_DMA_NOWAIT); 1229 if (error) 1230 goto destroy; 1231 return (0); 1232 1233 destroy: 1234 bus_dmamap_destroy(sc->dmat, p->map); 1235 unmap: 1236 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1237 free: 1238 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1239 return (error); 1240 } 1241 1242 int 1243 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1244 { 1245 1246 bus_dmamap_unload(sc->dmat, p->map); 1247 bus_dmamap_destroy(sc->dmat, p->map); 1248 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1249 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1250 return (0); 1251 } 1252 1253 int 1254 auich_alloc_cdata(struct auich_softc *sc) 1255 { 1256 bus_dma_segment_t seg; 1257 int error, rseg; 1258 1259 /* 1260 * Allocate the control data structure, and create and load the 1261 * DMA map for it. 1262 */ 1263 if ((error = bus_dmamem_alloc(sc->dmat, 1264 sizeof(struct auich_cdata), 1265 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1266 printf("%s: unable to allocate control data, error = %d\n", 1267 sc->sc_dev.dv_xname, error); 1268 goto fail_0; 1269 } 1270 1271 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1272 sizeof(struct auich_cdata), 1273 (caddr_t *) &sc->sc_cdata, 1274 BUS_DMA_COHERENT)) != 0) { 1275 printf("%s: unable to map control data, error = %d\n", 1276 sc->sc_dev.dv_xname, error); 1277 goto fail_1; 1278 } 1279 1280 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1281 sizeof(struct auich_cdata), 0, 0, 1282 &sc->sc_cddmamap)) != 0) { 1283 printf("%s: unable to create control data DMA map, " 1284 "error = %d\n", sc->sc_dev.dv_xname, error); 1285 goto fail_2; 1286 } 1287 1288 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1289 sc->sc_cdata, sizeof(struct auich_cdata), 1290 NULL, 0)) != 0) { 1291 printf("%s: unable tp load control data DMA map, " 1292 "error = %d\n", sc->sc_dev.dv_xname, error); 1293 goto fail_3; 1294 } 1295 1296 return (0); 1297 1298 fail_3: 1299 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1300 fail_2: 1301 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1302 sizeof(struct auich_cdata)); 1303 fail_1: 1304 bus_dmamem_free(sc->dmat, &seg, rseg); 1305 fail_0: 1306 return (error); 1307 } 1308 1309 void 1310 auich_powerhook(int why, void *addr) 1311 { 1312 struct auich_softc *sc = (struct auich_softc *)addr; 1313 1314 switch (why) { 1315 case PWR_SUSPEND: 1316 case PWR_STANDBY: 1317 /* Power down */ 1318 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1319 sc->sc_suspend = why; 1320 auich_read_codec(sc, AC97_REG_EXTENDED_STATUS, &sc->ext_status); 1321 break; 1322 1323 case PWR_RESUME: 1324 /* Wake up */ 1325 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1326 if (sc->sc_suspend == PWR_RESUME) { 1327 printf("%s: resume without suspend.\n", 1328 sc->sc_dev.dv_xname); 1329 sc->sc_suspend = why; 1330 return; 1331 } 1332 sc->sc_suspend = why; 1333 auich_reset_codec(sc); 1334 DELAY(1000); 1335 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1336 auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, sc->ext_status); 1337 break; 1338 1339 case PWR_SOFTSUSPEND: 1340 case PWR_SOFTSTANDBY: 1341 case PWR_SOFTRESUME: 1342 break; 1343 } 1344 } 1345 1346 1347 /* -------------------------------------------------------------------- */ 1348 /* Calibrate card (some boards are overclocked and need scaling) */ 1349 1350 unsigned int 1351 auich_calibrate(struct auich_softc *sc) 1352 { 1353 struct timeval t1, t2; 1354 u_int8_t ociv, nciv; 1355 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1356 void *temp_buffer; 1357 struct auich_dma *p; 1358 1359 ac97rate = 48000; 1360 /* 1361 * Grab audio from input for fixed interval and compare how 1362 * much we actually get with what we expect. Interval needs 1363 * to be sufficiently short that no interrupts are 1364 * generated. 1365 */ 1366 1367 /* Setup a buffer */ 1368 bytes = 16000; 1369 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1370 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1371 ; 1372 if (p == NULL) { 1373 printf("auich_calibrate: bad address %p\n", temp_buffer); 1374 return ac97rate; 1375 } 1376 sc->dmalist_pcmi[0].base = DMAADDR(p); 1377 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size) | ICH_DMAF_IOC; 1378 1379 /* 1380 * our data format is stereo, 16 bit so each sample is 4 bytes. 1381 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1382 * we're going to start recording with interrupts disabled and measure 1383 * the time taken for one block to complete. we know the block size, 1384 * we know the time in microseconds, we calculate the sample rate: 1385 * 1386 * actual_rate [bps] = bytes / (time [s] * 4) 1387 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1388 * actual_rate [Hz] = (bytes * 250000) / time [us] 1389 */ 1390 1391 /* prepare */ 1392 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1393 nciv = ociv; 1394 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1395 sc->sc_cddma + ICH_PCMI_OFF(0)); 1396 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1397 (0 - 1) & ICH_LVI_MASK); 1398 1399 /* start */ 1400 microtime(&t1); 1401 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1402 1403 /* wait */ 1404 while (nciv == ociv) { 1405 microtime(&t2); 1406 if (t2.tv_sec - t1.tv_sec > 1) 1407 break; 1408 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1409 ICH_PCMI + ICH_CIV); 1410 } 1411 microtime(&t2); 1412 1413 /* stop */ 1414 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1415 1416 /* reset */ 1417 DELAY(100); 1418 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1419 1420 /* turn time delta into us */ 1421 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1422 1423 auich_freem(sc, temp_buffer, M_DEVBUF); 1424 1425 if (nciv == ociv) { 1426 printf("%s: ac97 link rate calibration timed out after %d us\n", 1427 sc->sc_dev.dv_xname, wait_us); 1428 return ac97rate; 1429 } 1430 1431 actual_48k_rate = (bytes * 250000) / wait_us; 1432 1433 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 1434 ac97rate = actual_48k_rate; 1435 } 1436 1437 if (ac97rate != 48000) { 1438 printf("%s: measured ac97 link rate at %d Hz", 1439 sc->sc_dev.dv_xname, actual_48k_rate); 1440 if (ac97rate != actual_48k_rate) 1441 printf(", will use %d Hz", ac97rate); 1442 printf("\n"); 1443 } 1444 1445 return ac97rate; 1446 } 1447
Indexes created Thu Oct 23 22:10:10 GMT 2025