auich.c revision 1.3.4.6
1 /* $NetBSD: auich.c,v 1.3.4.6 2002/10/10 18:40:25 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * 107 * TODO: 108 * - Add support for the microphone input. 109 * - 4ch/6ch support. 110 * - auich_calibrate() is called in auich_open(). It causes about 0.1sec 111 * delay in the first open(). auich_calibrate() should be called in 112 * auich_attach(). However microtime() doesn't work in the attach 113 * stage. 114 */ 115 116 #include <sys/cdefs.h> 117 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.3.4.6 2002/10/10 18:40:25 jdolecek Exp $"); 118 119 #include <sys/param.h> 120 #include <sys/systm.h> 121 #include <sys/kernel.h> 122 #include <sys/malloc.h> 123 #include <sys/device.h> 124 #include <sys/fcntl.h> 125 #include <sys/proc.h> 126 127 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 128 129 #include <dev/pci/pcidevs.h> 130 #include <dev/pci/pcivar.h> 131 #include <dev/pci/auichreg.h> 132 133 #include <sys/audioio.h> 134 #include <dev/audio_if.h> 135 #include <dev/mulaw.h> 136 #include <dev/auconv.h> 137 138 #include <machine/bus.h> 139 140 #include <dev/ic/ac97reg.h> 141 #include <dev/ic/ac97var.h> 142 143 struct auich_dma { 144 bus_dmamap_t map; 145 caddr_t addr; 146 bus_dma_segment_t segs[1]; 147 int nsegs; 148 size_t size; 149 struct auich_dma *next; 150 }; 151 152 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 153 #define KERNADDR(p) ((void *)((p)->addr)) 154 155 struct auich_cdata { 156 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 157 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 158 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 159 }; 160 161 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 162 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 163 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 164 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 165 166 struct auich_softc { 167 struct device sc_dev; 168 void *sc_ih; 169 170 audio_device_t sc_audev; 171 172 bus_space_tag_t iot; 173 bus_space_handle_t mix_ioh; 174 bus_space_handle_t aud_ioh; 175 bus_dma_tag_t dmat; 176 177 struct ac97_codec_if *codec_if; 178 struct ac97_host_if host_if; 179 180 /* DMA scatter-gather lists. */ 181 bus_dmamap_t sc_cddmamap; 182 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 183 184 struct auich_cdata *sc_cdata; 185 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 186 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 187 #define dmalist_mici sc_cdata->ic_dmalist_mici 188 189 int ptr_pcmo, 190 ptr_pcmi, 191 ptr_mici; 192 193 /* i/o buffer pointers */ 194 u_int32_t pcmo_start, pcmo_p, pcmo_end; 195 int pcmo_blksize, pcmo_fifoe; 196 197 u_int32_t pcmi_start, pcmi_p, pcmi_end; 198 int pcmi_blksize, pcmi_fifoe; 199 200 u_int32_t mici_start, mici_p, mici_end; 201 int mici_blksize, mici_fifoe; 202 203 struct auich_dma *sc_dmas; 204 205 int sc_fixed_rate; 206 int sc_calibrated; /* sc_ac97rate has correct value */ 207 int sc_ac97rate; 208 int sc_ignore_codecready; 209 210 /* SiS 7012 hack */ 211 int sc_sample_size; 212 int sc_sts_reg; 213 214 void (*sc_pintr)(void *); 215 void *sc_parg; 216 217 void (*sc_rintr)(void *); 218 void *sc_rarg; 219 220 /* Power Management */ 221 void *sc_powerhook; 222 int sc_suspend; 223 u_int16_t ext_status; 224 }; 225 226 #define FIXED_RATE 48000 227 228 /* Debug */ 229 #ifdef AUDIO_DEBUG 230 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 231 int auich_debug = 0xfffe; 232 #define ICH_DEBUG_CODECIO 0x0001 233 #define ICH_DEBUG_DMA 0x0002 234 #define ICH_DEBUG_PARAM 0x0004 235 #else 236 #define DPRINTF(x,y) /* nothing */ 237 #endif 238 239 int auich_match(struct device *, struct cfdata *, void *); 240 void auich_attach(struct device *, struct device *, void *); 241 int auich_intr(void *); 242 243 CFATTACH_DECL(auich, sizeof(struct auich_softc), 244 auich_match, auich_attach, NULL, NULL); 245 246 int auich_open(void *, int); 247 void auich_close(void *); 248 int auich_query_encoding(void *, struct audio_encoding *); 249 int auich_set_params(void *, int, int, struct audio_params *, 250 struct audio_params *); 251 int auich_round_blocksize(void *, int); 252 int auich_halt_output(void *); 253 int auich_halt_input(void *); 254 int auich_getdev(void *, struct audio_device *); 255 int auich_set_port(void *, mixer_ctrl_t *); 256 int auich_get_port(void *, mixer_ctrl_t *); 257 int auich_query_devinfo(void *, mixer_devinfo_t *); 258 void *auich_allocm(void *, int, size_t, int, int); 259 void auich_freem(void *, void *, int); 260 size_t auich_round_buffersize(void *, int, size_t); 261 paddr_t auich_mappage(void *, void *, off_t, int); 262 int auich_get_props(void *); 263 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 264 void *, struct audio_params *); 265 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 266 void *, struct audio_params *); 267 268 int auich_alloc_cdata(struct auich_softc *); 269 270 int auich_allocmem(struct auich_softc *, size_t, size_t, 271 struct auich_dma *); 272 int auich_freemem(struct auich_softc *, struct auich_dma *); 273 274 void auich_powerhook(int, void *); 275 int auich_set_rate(struct auich_softc *sc, int mode, uint srate); 276 unsigned int auich_calibrate(struct auich_softc *sc); 277 278 279 struct audio_hw_if auich_hw_if = { 280 auich_open, 281 auich_close, 282 NULL, /* drain */ 283 auich_query_encoding, 284 auich_set_params, 285 auich_round_blocksize, 286 NULL, /* commit_setting */ 287 NULL, /* init_output */ 288 NULL, /* init_input */ 289 NULL, /* start_output */ 290 NULL, /* start_input */ 291 auich_halt_output, 292 auich_halt_input, 293 NULL, /* speaker_ctl */ 294 auich_getdev, 295 NULL, /* getfd */ 296 auich_set_port, 297 auich_get_port, 298 auich_query_devinfo, 299 auich_allocm, 300 auich_freem, 301 auich_round_buffersize, 302 auich_mappage, 303 auich_get_props, 304 auich_trigger_output, 305 auich_trigger_input, 306 NULL, /* dev_ioctl */ 307 }; 308 309 int auich_attach_codec(void *, struct ac97_codec_if *); 310 int auich_read_codec(void *, u_int8_t, u_int16_t *); 311 int auich_write_codec(void *, u_int8_t, u_int16_t); 312 void auich_reset_codec(void *); 313 314 static const struct auich_devtype { 315 int vendor; 316 int product; 317 const char *name; 318 const char *shortname; 319 } auich_devices[] = { 320 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 321 "i82801AA (ICH) AC-97 Audio", "ICH" }, 322 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 323 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, /* i810-L */ 324 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 325 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 326 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 327 "i82440MX AC-97 Audio", "440MX" }, 328 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 329 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, /* i830Mx i845MP/MZ*/ 330 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 331 "i82801DB (ICH4) AC-97 Audio", "ICH4" }, /* i845E i845Gx */ 332 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 333 "SiS 7012 AC-97 Audio", "SiS7012" }, 334 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 335 "nForce MCP AC-97 Audio", "nForce-MCP" }, 336 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 337 "AMD768 AC-97 Audio", "AMD768" }, 338 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 339 "AMD8111 AC-97 Audio", "AMD8111" }, 340 { 0, 341 NULL, NULL }, 342 }; 343 344 static const struct auich_devtype * 345 auich_lookup(struct pci_attach_args *pa) 346 { 347 const struct auich_devtype *d; 348 349 for (d = auich_devices; d->name != NULL; d++) { 350 if (PCI_VENDOR(pa->pa_id) == d->vendor 351 && PCI_PRODUCT(pa->pa_id) == d->product) 352 return (d); 353 } 354 355 return (NULL); 356 } 357 358 int 359 auich_match(struct device *parent, struct cfdata *match, void *aux) 360 { 361 struct pci_attach_args *pa = aux; 362 363 if (auich_lookup(pa) != NULL) 364 return (1); 365 366 return (0); 367 } 368 369 void 370 auich_attach(struct device *parent, struct device *self, void *aux) 371 { 372 struct auich_softc *sc = (struct auich_softc *)self; 373 struct pci_attach_args *pa = aux; 374 pci_intr_handle_t ih; 375 bus_size_t mix_size, aud_size; 376 pcireg_t csr; 377 const char *intrstr; 378 const struct auich_devtype *d; 379 u_int16_t ext_id, ext_status; 380 u_int32_t status; 381 382 d = auich_lookup(pa); 383 if (d == NULL) 384 panic("auich_attach: impossible"); 385 386 printf(": %s\n", d->name); 387 388 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 389 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 390 printf("%s: can't map codec i/o space\n", 391 sc->sc_dev.dv_xname); 392 return; 393 } 394 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 395 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 396 printf("%s: can't map device i/o space\n", 397 sc->sc_dev.dv_xname); 398 return; 399 } 400 sc->dmat = pa->pa_dmat; 401 402 /* enable bus mastering */ 403 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 404 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 405 csr | PCI_COMMAND_MASTER_ENABLE); 406 407 /* Map and establish the interrupt. */ 408 if (pci_intr_map(pa, &ih)) { 409 printf("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 410 return; 411 } 412 intrstr = pci_intr_string(pa->pa_pc, ih); 413 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 414 auich_intr, sc); 415 if (sc->sc_ih == NULL) { 416 printf("%s: can't establish interrupt", sc->sc_dev.dv_xname); 417 if (intrstr != NULL) 418 printf(" at %s", intrstr); 419 printf("\n"); 420 return; 421 } 422 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 423 424 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 425 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 426 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 427 428 /* SiS 7012 needs special handling */ 429 if (d->vendor == PCI_VENDOR_SIS 430 && d->product == PCI_PRODUCT_SIS_7012_AC) { 431 sc->sc_sts_reg = ICH_PICB; 432 sc->sc_sample_size = 1; 433 } else { 434 sc->sc_sts_reg = ICH_STS; 435 sc->sc_sample_size = 2; 436 } 437 438 /* Set up DMA lists. */ 439 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 440 auich_alloc_cdata(sc); 441 442 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 443 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 444 445 sc->sc_ac97rate = FIXED_RATE; 446 /* Reset codec and AC'97 */ 447 auich_reset_codec(sc); 448 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 449 if (!(status & ICH_PCR)) { /* reset failure */ 450 if (d->vendor == PCI_VENDOR_INTEL 451 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) { 452 /* MSI 845G Max never return ICH_PCR */ 453 sc->sc_ignore_codecready = TRUE; 454 } else { 455 return; 456 } 457 } 458 /* Print capabilities though there are no supports for now */ 459 if ((status & ICH_SAMPLE_CAP) == ICH_POM20) 460 printf("%s: 20 bit precision support\n", sc->sc_dev.dv_xname); 461 if ((status & ICH_CHAN_CAP) == ICH_PCM4) 462 printf("%s: 4ch PCM output support\n", sc->sc_dev.dv_xname); 463 if ((status & ICH_CHAN_CAP) == ICH_PCM6) 464 printf("%s: 6ch PCM output support\n", sc->sc_dev.dv_xname); 465 466 sc->host_if.arg = sc; 467 sc->host_if.attach = auich_attach_codec; 468 sc->host_if.read = auich_read_codec; 469 sc->host_if.write = auich_write_codec; 470 sc->host_if.reset = auich_reset_codec; 471 472 if (ac97_attach(&sc->host_if) != 0) 473 return; 474 475 auich_read_codec(sc, AC97_REG_EXTENDED_ID, &ext_id); 476 if ((ext_id & (AC97_CODEC_DOES_VRA | AC97_CODEC_DOES_MICVRA)) != 0) { 477 auich_read_codec(sc, AC97_REG_EXTENDED_STATUS, &ext_status); 478 if ((ext_id & AC97_CODEC_DOES_VRA) !=0) 479 ext_status |= AC97_ENAB_VRA; 480 if ((ext_id & AC97_CODEC_DOES_MICVRA) !=0) 481 ext_status |= AC97_ENAB_MICVRA; 482 auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, ext_status); 483 484 /* so it claims to do variable rate, let's make sure */ 485 if (auich_set_rate(sc, AUMODE_PLAY, 44100) == 44100) 486 sc->sc_fixed_rate = 0; 487 else 488 sc->sc_fixed_rate = FIXED_RATE; 489 } else { 490 sc->sc_fixed_rate = FIXED_RATE; 491 } 492 if (sc->sc_fixed_rate) 493 printf("%s: warning, fixed rate codec\n", sc->sc_dev.dv_xname); 494 495 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 496 497 /* Watch for power change */ 498 sc->sc_suspend = PWR_RESUME; 499 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 500 } 501 502 #define ICH_CODECIO_INTERVAL 10 503 int 504 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 505 { 506 struct auich_softc *sc = v; 507 int i; 508 uint32_t status; 509 510 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 511 if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) { 512 printf("auich_read_codec: codec is not ready (0x%x)\n", status); 513 *val = 0xffff; 514 return -1; 515 } 516 /* wait for an access semaphore */ 517 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 518 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 519 DELAY(ICH_CODECIO_INTERVAL)); 520 521 if (i > 0) { 522 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 523 DPRINTF(ICH_DEBUG_CODECIO, 524 ("auich_read_codec(%x, %x)\n", reg, *val)); 525 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 526 if (status & ICH_RCS) { 527 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 528 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 529 *val = 0xffff; 530 } 531 return 0; 532 } else { 533 DPRINTF(ICH_DEBUG_CODECIO, 534 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 535 return -1; 536 } 537 } 538 539 int 540 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 541 { 542 struct auich_softc *sc = v; 543 int i; 544 545 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 546 if (!sc->sc_ignore_codecready 547 && !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) { 548 printf("auich_write_codec: codec is not ready."); 549 return -1; 550 } 551 /* wait for an access semaphore */ 552 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 553 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 554 DELAY(ICH_CODECIO_INTERVAL)); 555 556 if (i > 0) { 557 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 558 return 0; 559 } else { 560 DPRINTF(ICH_DEBUG_CODECIO, 561 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 562 return -1; 563 } 564 } 565 566 int 567 auich_attach_codec(void *v, struct ac97_codec_if *cif) 568 { 569 struct auich_softc *sc = v; 570 571 sc->codec_if = cif; 572 return 0; 573 } 574 575 void 576 auich_reset_codec(void *v) 577 { 578 struct auich_softc *sc = v; 579 int i; 580 uint32_t control; 581 582 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 583 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 584 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 585 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 586 587 for (i = 500000; i-- && 588 !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR); 589 DELAY(1)); /* or ICH_SCR? */ 590 if (i <= 0) 591 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 592 } 593 594 int 595 auich_open(void *v, int flags) 596 { 597 struct auich_softc *sc = v; 598 599 if (!sc->sc_fixed_rate && !sc->sc_calibrated) { 600 sc->sc_ac97rate = auich_calibrate(sc); 601 sc->sc_calibrated = TRUE; 602 } 603 return 0; 604 } 605 606 void 607 auich_close(void *v) 608 { 609 struct auich_softc *sc = v; 610 611 auich_halt_output(sc); 612 auich_halt_input(sc); 613 614 sc->sc_pintr = NULL; 615 sc->sc_rintr = NULL; 616 } 617 618 int 619 auich_query_encoding(void *v, struct audio_encoding *aep) 620 { 621 622 switch (aep->index) { 623 case 0: 624 strcpy(aep->name, AudioEulinear); 625 aep->encoding = AUDIO_ENCODING_ULINEAR; 626 aep->precision = 8; 627 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 628 return (0); 629 case 1: 630 strcpy(aep->name, AudioEmulaw); 631 aep->encoding = AUDIO_ENCODING_ULAW; 632 aep->precision = 8; 633 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 634 return (0); 635 case 2: 636 strcpy(aep->name, AudioEalaw); 637 aep->encoding = AUDIO_ENCODING_ALAW; 638 aep->precision = 8; 639 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 640 return (0); 641 case 3: 642 strcpy(aep->name, AudioEslinear); 643 aep->encoding = AUDIO_ENCODING_SLINEAR; 644 aep->precision = 8; 645 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 646 return (0); 647 case 4: 648 strcpy(aep->name, AudioEslinear_le); 649 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 650 aep->precision = 16; 651 aep->flags = 0; 652 return (0); 653 case 5: 654 strcpy(aep->name, AudioEulinear_le); 655 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 656 aep->precision = 16; 657 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 658 return (0); 659 case 6: 660 strcpy(aep->name, AudioEslinear_be); 661 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 662 aep->precision = 16; 663 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 664 return (0); 665 case 7: 666 strcpy(aep->name, AudioEulinear_be); 667 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 668 aep->precision = 16; 669 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 670 return (0); 671 default: 672 return (EINVAL); 673 } 674 } 675 676 int 677 auich_set_rate(struct auich_softc *sc, int mode, uint srate) 678 { 679 u_int16_t val, rate, inout; 680 u_int32_t rvalue; 681 682 inout = mode == AUMODE_PLAY ? ICH_PM_PCMO : ICH_PM_PCMI; 683 684 auich_read_codec(sc, AC97_REG_POWER, &val); 685 auich_write_codec(sc, AC97_REG_POWER, val | inout); 686 687 rvalue = srate * FIXED_RATE / sc->sc_ac97rate; 688 if (mode == AUMODE_PLAY) { 689 auich_write_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, rvalue); 690 auich_read_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, &rate); 691 } else { 692 auich_write_codec(sc, AC97_REG_PCM_LR_ADC_RATE, rvalue); 693 auich_read_codec(sc, AC97_REG_PCM_LR_ADC_RATE, &rate); 694 } 695 696 auich_write_codec(sc, AC97_REG_POWER, val); 697 698 /* Cast to avoid integer overflow */ 699 rvalue = (u_int32_t)rate * sc->sc_ac97rate / FIXED_RATE; 700 return rvalue; 701 } 702 703 int 704 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 705 struct audio_params *rec) 706 { 707 struct auich_softc *sc = v; 708 struct audio_params *p; 709 int mode; 710 711 for (mode = AUMODE_RECORD; mode != -1; 712 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 713 if ((setmode & mode) == 0) 714 continue; 715 716 p = mode == AUMODE_PLAY ? play : rec; 717 if (p == NULL) 718 continue; 719 720 if ((p->sample_rate != 8000) && 721 (p->sample_rate != 11025) && 722 (p->sample_rate != 16000) && 723 (p->sample_rate != 22050) && 724 (p->sample_rate != 32000) && 725 (p->sample_rate != 44100) && 726 (p->sample_rate != 48000)) 727 return (EINVAL); 728 729 p->factor = 1; 730 if (p->precision == 8) 731 p->factor *= 2; 732 733 p->sw_code = NULL; 734 /* setup hardware formats */ 735 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 736 p->hw_precision = 16; 737 738 /* If manaural is requested, aurateconv expands a monaural 739 * stream to stereo. */ 740 if (p->channels < 2) 741 p->hw_channels = 2; 742 743 switch (p->encoding) { 744 case AUDIO_ENCODING_SLINEAR_BE: 745 if (p->precision == 16) { 746 p->sw_code = swap_bytes; 747 } else { 748 if (mode == AUMODE_PLAY) 749 p->sw_code = linear8_to_linear16_le; 750 else 751 p->sw_code = linear16_to_linear8_le; 752 } 753 break; 754 755 case AUDIO_ENCODING_SLINEAR_LE: 756 if (p->precision != 16) { 757 if (mode == AUMODE_PLAY) 758 p->sw_code = linear8_to_linear16_le; 759 else 760 p->sw_code = linear16_to_linear8_le; 761 } 762 break; 763 764 case AUDIO_ENCODING_ULINEAR_BE: 765 if (p->precision == 16) { 766 if (mode == AUMODE_PLAY) 767 p->sw_code = 768 swap_bytes_change_sign16_le; 769 else 770 p->sw_code = 771 change_sign16_swap_bytes_le; 772 } else { 773 if (mode == AUMODE_PLAY) 774 p->sw_code = 775 ulinear8_to_slinear16_le; 776 else 777 p->sw_code = 778 slinear16_to_ulinear8_le; 779 } 780 break; 781 782 case AUDIO_ENCODING_ULINEAR_LE: 783 if (p->precision == 16) { 784 p->sw_code = change_sign16_le; 785 } else { 786 if (mode == AUMODE_PLAY) 787 p->sw_code = 788 ulinear8_to_slinear16_le; 789 else 790 p->sw_code = 791 slinear16_to_ulinear8_le; 792 } 793 break; 794 795 case AUDIO_ENCODING_ULAW: 796 if (mode == AUMODE_PLAY) { 797 p->sw_code = mulaw_to_slinear16_le; 798 } else { 799 p->sw_code = slinear16_to_mulaw_le; 800 } 801 break; 802 803 case AUDIO_ENCODING_ALAW: 804 if (mode == AUMODE_PLAY) { 805 p->sw_code = alaw_to_slinear16_le; 806 } else { 807 p->sw_code = slinear16_to_alaw_le; 808 } 809 break; 810 811 default: 812 return (EINVAL); 813 } 814 815 if (sc->sc_fixed_rate) { 816 p->hw_sample_rate = sc->sc_fixed_rate; 817 } else { 818 p->hw_sample_rate = auich_set_rate(sc, mode, 819 p->sample_rate); 820 } 821 /* If hw_sample_rate is different from sample_rate, aurateconv 822 * works. */ 823 } 824 825 return (0); 826 } 827 828 int 829 auich_round_blocksize(void *v, int blk) 830 { 831 832 return (blk & ~0x3f); /* keep good alignment */ 833 } 834 835 int 836 auich_halt_output(void *v) 837 { 838 struct auich_softc *sc = v; 839 840 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 841 842 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 843 844 return (0); 845 } 846 847 int 848 auich_halt_input(void *v) 849 { 850 struct auich_softc *sc = v; 851 852 DPRINTF(ICH_DEBUG_DMA, 853 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 854 855 /* XXX halt both unless known otherwise */ 856 857 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 858 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 859 860 return (0); 861 } 862 863 int 864 auich_getdev(void *v, struct audio_device *adp) 865 { 866 struct auich_softc *sc = v; 867 868 *adp = sc->sc_audev; 869 return (0); 870 } 871 872 int 873 auich_set_port(void *v, mixer_ctrl_t *cp) 874 { 875 struct auich_softc *sc = v; 876 877 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 878 } 879 880 int 881 auich_get_port(void *v, mixer_ctrl_t *cp) 882 { 883 struct auich_softc *sc = v; 884 885 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 886 } 887 888 int 889 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 890 { 891 struct auich_softc *sc = v; 892 893 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 894 } 895 896 void * 897 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 898 { 899 struct auich_softc *sc = v; 900 struct auich_dma *p; 901 int error; 902 903 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 904 return (NULL); 905 906 p = malloc(sizeof(*p), pool, flags|M_ZERO); 907 if (p == NULL) 908 return (NULL); 909 910 error = auich_allocmem(sc, size, 0, p); 911 if (error) { 912 free(p, pool); 913 return (NULL); 914 } 915 916 p->next = sc->sc_dmas; 917 sc->sc_dmas = p; 918 919 return (KERNADDR(p)); 920 } 921 922 void 923 auich_freem(void *v, void *ptr, int pool) 924 { 925 struct auich_softc *sc = v; 926 struct auich_dma *p, **pp; 927 928 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 929 if (KERNADDR(p) == ptr) { 930 auich_freemem(sc, p); 931 *pp = p->next; 932 free(p, pool); 933 return; 934 } 935 } 936 } 937 938 size_t 939 auich_round_buffersize(void *v, int direction, size_t size) 940 { 941 942 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 943 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 944 945 return size; 946 } 947 948 paddr_t 949 auich_mappage(void *v, void *mem, off_t off, int prot) 950 { 951 struct auich_softc *sc = v; 952 struct auich_dma *p; 953 954 if (off < 0) 955 return (-1); 956 957 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 958 ; 959 if (!p) 960 return (-1); 961 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 962 off, prot, BUS_DMA_WAITOK)); 963 } 964 965 int 966 auich_get_props(void *v) 967 { 968 969 return (AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | 970 AUDIO_PROP_FULLDUPLEX); 971 } 972 973 int 974 auich_intr(void *v) 975 { 976 struct auich_softc *sc = v; 977 int ret = 0, sts, gsts, i, qptr; 978 979 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 980 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 981 982 if (gsts & ICH_POINT) { 983 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 984 DPRINTF(ICH_DEBUG_DMA, 985 ("auich_intr: osts=0x%x\n", sts)); 986 987 if (sts & ICH_FIFOE) { 988 printf("%s: fifo underrun # %u\n", 989 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 990 } 991 992 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 993 if (sts & (ICH_LVBCI | ICH_CELV)) { 994 struct auich_dmalist *q; 995 996 qptr = sc->ptr_pcmo; 997 998 while (qptr != i) { 999 q = &sc->dmalist_pcmo[qptr]; 1000 1001 q->base = sc->pcmo_p; 1002 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1003 DPRINTF(ICH_DEBUG_DMA, 1004 ("auich_intr: %p, %p = %x @ 0x%x\n", 1005 &sc->dmalist_pcmo[i], q, 1006 sc->pcmo_blksize / 2, sc->pcmo_p)); 1007 1008 sc->pcmo_p += sc->pcmo_blksize; 1009 if (sc->pcmo_p >= sc->pcmo_end) 1010 sc->pcmo_p = sc->pcmo_start; 1011 1012 if (++qptr == ICH_DMALIST_MAX) 1013 qptr = 0; 1014 } 1015 1016 sc->ptr_pcmo = qptr; 1017 bus_space_write_1(sc->iot, sc->aud_ioh, 1018 ICH_PCMO + ICH_LVI, 1019 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1020 } 1021 1022 if (sts & ICH_BCIS && sc->sc_pintr) 1023 sc->sc_pintr(sc->sc_parg); 1024 1025 /* int ack */ 1026 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1027 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1028 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1029 ret++; 1030 } 1031 1032 if (gsts & ICH_PIINT) { 1033 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1034 DPRINTF(ICH_DEBUG_DMA, 1035 ("auich_intr: ists=0x%x\n", sts)); 1036 1037 if (sts & ICH_FIFOE) { 1038 printf("%s: fifo overrun # %u\n", 1039 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1040 } 1041 1042 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1043 if (sts & (ICH_LVBCI | ICH_CELV)) { 1044 struct auich_dmalist *q; 1045 1046 qptr = sc->ptr_pcmi; 1047 1048 while (qptr != i) { 1049 q = &sc->dmalist_pcmi[qptr]; 1050 1051 q->base = sc->pcmi_p; 1052 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1053 DPRINTF(ICH_DEBUG_DMA, 1054 ("auich_intr: %p, %p = %x @ 0x%x\n", 1055 &sc->dmalist_pcmi[i], q, 1056 sc->pcmi_blksize / 2, sc->pcmi_p)); 1057 1058 sc->pcmi_p += sc->pcmi_blksize; 1059 if (sc->pcmi_p >= sc->pcmi_end) 1060 sc->pcmi_p = sc->pcmi_start; 1061 1062 if (++qptr == ICH_DMALIST_MAX) 1063 qptr = 0; 1064 } 1065 1066 sc->ptr_pcmi = qptr; 1067 bus_space_write_1(sc->iot, sc->aud_ioh, 1068 ICH_PCMI + ICH_LVI, 1069 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1070 } 1071 1072 if (sts & ICH_BCIS && sc->sc_rintr) 1073 sc->sc_rintr(sc->sc_rarg); 1074 1075 /* int ack */ 1076 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1077 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1078 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1079 ret++; 1080 } 1081 1082 if (gsts & ICH_MIINT) { 1083 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1084 DPRINTF(ICH_DEBUG_DMA, 1085 ("auich_intr: ists=0x%x\n", sts)); 1086 if (sts & ICH_FIFOE) 1087 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1088 1089 /* TODO mic input dma */ 1090 1091 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1092 } 1093 1094 return ret; 1095 } 1096 1097 int 1098 auich_trigger_output(void *v, void *start, void *end, int blksize, 1099 void (*intr)(void *), void *arg, struct audio_params *param) 1100 { 1101 struct auich_softc *sc = v; 1102 struct auich_dmalist *q; 1103 struct auich_dma *p; 1104 size_t size; 1105 1106 DPRINTF(ICH_DEBUG_DMA, 1107 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1108 start, end, blksize, intr, arg, param)); 1109 1110 sc->sc_pintr = intr; 1111 sc->sc_parg = arg; 1112 1113 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1114 ; 1115 if (!p) { 1116 printf("auich_trigger_output: bad addr %p\n", start); 1117 return (EINVAL); 1118 } 1119 1120 size = (size_t)((caddr_t)end - (caddr_t)start); 1121 1122 /* 1123 * The logic behind this is: 1124 * setup one buffer to play, then LVI dump out the rest 1125 * to the scatter-gather chain. 1126 */ 1127 sc->pcmo_start = DMAADDR(p); 1128 sc->pcmo_p = sc->pcmo_start + blksize; 1129 sc->pcmo_end = sc->pcmo_start + size; 1130 sc->pcmo_blksize = blksize; 1131 1132 sc->ptr_pcmo = 0; 1133 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1134 q->base = sc->pcmo_start; 1135 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1136 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1137 sc->ptr_pcmo = 0; 1138 1139 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1140 sc->sc_cddma + ICH_PCMO_OFF(0)); 1141 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1142 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1143 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1144 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1145 1146 return (0); 1147 } 1148 1149 int 1150 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1151 void *v; 1152 void *start, *end; 1153 int blksize; 1154 void (*intr)(void *); 1155 void *arg; 1156 struct audio_params *param; 1157 { 1158 struct auich_softc *sc = v; 1159 struct auich_dmalist *q; 1160 struct auich_dma *p; 1161 size_t size; 1162 1163 DPRINTF(ICH_DEBUG_DMA, 1164 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1165 start, end, blksize, intr, arg, param)); 1166 1167 sc->sc_rintr = intr; 1168 sc->sc_rarg = arg; 1169 1170 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1171 ; 1172 if (!p) { 1173 printf("auich_trigger_input: bad addr %p\n", start); 1174 return (EINVAL); 1175 } 1176 1177 size = (size_t)((caddr_t)end - (caddr_t)start); 1178 1179 /* 1180 * The logic behind this is: 1181 * setup one buffer to play, then LVI dump out the rest 1182 * to the scatter-gather chain. 1183 */ 1184 sc->pcmi_start = DMAADDR(p); 1185 sc->pcmi_p = sc->pcmi_start + blksize; 1186 sc->pcmi_end = sc->pcmi_start + size; 1187 sc->pcmi_blksize = blksize; 1188 1189 sc->ptr_pcmi = 0; 1190 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1191 q->base = sc->pcmi_start; 1192 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1193 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1194 sc->ptr_pcmi = 0; 1195 1196 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1197 sc->sc_cddma + ICH_PCMI_OFF(0)); 1198 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1199 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1200 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1201 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1202 1203 return (0); 1204 } 1205 1206 int 1207 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1208 struct auich_dma *p) 1209 { 1210 int error; 1211 1212 p->size = size; 1213 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1214 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1215 &p->nsegs, BUS_DMA_NOWAIT); 1216 if (error) 1217 return (error); 1218 1219 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1220 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1221 if (error) 1222 goto free; 1223 1224 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1225 0, BUS_DMA_NOWAIT, &p->map); 1226 if (error) 1227 goto unmap; 1228 1229 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1230 BUS_DMA_NOWAIT); 1231 if (error) 1232 goto destroy; 1233 return (0); 1234 1235 destroy: 1236 bus_dmamap_destroy(sc->dmat, p->map); 1237 unmap: 1238 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1239 free: 1240 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1241 return (error); 1242 } 1243 1244 int 1245 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1246 { 1247 1248 bus_dmamap_unload(sc->dmat, p->map); 1249 bus_dmamap_destroy(sc->dmat, p->map); 1250 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1251 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1252 return (0); 1253 } 1254 1255 int 1256 auich_alloc_cdata(struct auich_softc *sc) 1257 { 1258 bus_dma_segment_t seg; 1259 int error, rseg; 1260 1261 /* 1262 * Allocate the control data structure, and create and load the 1263 * DMA map for it. 1264 */ 1265 if ((error = bus_dmamem_alloc(sc->dmat, 1266 sizeof(struct auich_cdata), 1267 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1268 printf("%s: unable to allocate control data, error = %d\n", 1269 sc->sc_dev.dv_xname, error); 1270 goto fail_0; 1271 } 1272 1273 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1274 sizeof(struct auich_cdata), 1275 (caddr_t *) &sc->sc_cdata, 1276 BUS_DMA_COHERENT)) != 0) { 1277 printf("%s: unable to map control data, error = %d\n", 1278 sc->sc_dev.dv_xname, error); 1279 goto fail_1; 1280 } 1281 1282 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1283 sizeof(struct auich_cdata), 0, 0, 1284 &sc->sc_cddmamap)) != 0) { 1285 printf("%s: unable to create control data DMA map, " 1286 "error = %d\n", sc->sc_dev.dv_xname, error); 1287 goto fail_2; 1288 } 1289 1290 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1291 sc->sc_cdata, sizeof(struct auich_cdata), 1292 NULL, 0)) != 0) { 1293 printf("%s: unable tp load control data DMA map, " 1294 "error = %d\n", sc->sc_dev.dv_xname, error); 1295 goto fail_3; 1296 } 1297 1298 return (0); 1299 1300 fail_3: 1301 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1302 fail_2: 1303 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1304 sizeof(struct auich_cdata)); 1305 fail_1: 1306 bus_dmamem_free(sc->dmat, &seg, rseg); 1307 fail_0: 1308 return (error); 1309 } 1310 1311 void 1312 auich_powerhook(int why, void *addr) 1313 { 1314 struct auich_softc *sc = (struct auich_softc *)addr; 1315 1316 switch (why) { 1317 case PWR_SUSPEND: 1318 case PWR_STANDBY: 1319 /* Power down */ 1320 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1321 sc->sc_suspend = why; 1322 auich_read_codec(sc, AC97_REG_EXTENDED_STATUS, &sc->ext_status); 1323 break; 1324 1325 case PWR_RESUME: 1326 /* Wake up */ 1327 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1328 if (sc->sc_suspend == PWR_RESUME) { 1329 printf("%s: resume without suspend.\n", 1330 sc->sc_dev.dv_xname); 1331 sc->sc_suspend = why; 1332 return; 1333 } 1334 sc->sc_suspend = why; 1335 auich_reset_codec(sc); 1336 DELAY(1000); 1337 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1338 auich_write_codec(sc, AC97_REG_EXTENDED_STATUS, sc->ext_status); 1339 break; 1340 1341 case PWR_SOFTSUSPEND: 1342 case PWR_SOFTSTANDBY: 1343 case PWR_SOFTRESUME: 1344 break; 1345 } 1346 } 1347 1348 1349 /* -------------------------------------------------------------------- */ 1350 /* Calibrate card (some boards are overclocked and need scaling) */ 1351 1352 unsigned int 1353 auich_calibrate(struct auich_softc *sc) 1354 { 1355 struct timeval t1, t2; 1356 u_int8_t ociv, nciv; 1357 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1358 void *temp_buffer; 1359 struct auich_dma *p; 1360 1361 ac97rate = 48000; 1362 /* 1363 * Grab audio from input for fixed interval and compare how 1364 * much we actually get with what we expect. Interval needs 1365 * to be sufficiently short that no interrupts are 1366 * generated. 1367 */ 1368 1369 /* Setup a buffer */ 1370 bytes = 16000; 1371 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1372 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1373 ; 1374 if (p == NULL) { 1375 printf("auich_calibrate: bad address %p\n", temp_buffer); 1376 return ac97rate; 1377 } 1378 sc->dmalist_pcmi[0].base = DMAADDR(p); 1379 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size) | ICH_DMAF_IOC; 1380 1381 /* 1382 * our data format is stereo, 16 bit so each sample is 4 bytes. 1383 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1384 * we're going to start recording with interrupts disabled and measure 1385 * the time taken for one block to complete. we know the block size, 1386 * we know the time in microseconds, we calculate the sample rate: 1387 * 1388 * actual_rate [bps] = bytes / (time [s] * 4) 1389 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1390 * actual_rate [Hz] = (bytes * 250000) / time [us] 1391 */ 1392 1393 /* prepare */ 1394 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1395 nciv = ociv; 1396 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1397 sc->sc_cddma + ICH_PCMI_OFF(0)); 1398 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1399 (0 - 1) & ICH_LVI_MASK); 1400 1401 /* start */ 1402 microtime(&t1); 1403 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1404 1405 /* wait */ 1406 while (nciv == ociv) { 1407 microtime(&t2); 1408 if (t2.tv_sec - t1.tv_sec > 1) 1409 break; 1410 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1411 ICH_PCMI + ICH_CIV); 1412 } 1413 microtime(&t2); 1414 1415 /* stop */ 1416 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1417 1418 /* reset */ 1419 DELAY(100); 1420 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1421 1422 /* turn time delta into us */ 1423 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1424 1425 auich_freem(sc, temp_buffer, M_DEVBUF); 1426 1427 if (nciv == ociv) { 1428 printf("%s: ac97 link rate calibration timed out after %d us\n", 1429 sc->sc_dev.dv_xname, wait_us); 1430 return ac97rate; 1431 } 1432 1433 actual_48k_rate = (bytes * 250000) / wait_us; 1434 1435 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 1436 ac97rate = actual_48k_rate; 1437 } 1438 1439 if (ac97rate != 48000) { 1440 printf("%s: measured ac97 link rate at %d Hz", 1441 sc->sc_dev.dv_xname, actual_48k_rate); 1442 if (ac97rate != actual_48k_rate) 1443 printf(", will use %d Hz", ac97rate); 1444 printf("\n"); 1445 } 1446 1447 return ac97rate; 1448 } 1449
Indexes created Thu Oct 23 22:10:10 GMT 2025