auich.c revision 1.30
1 /* $NetBSD: auich.c,v 1.30 2002/10/12 19:45:54 wiz Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * 107 * TODO: 108 * - Add support for the dedicated microphone input. 109 * - 4ch/6ch support. 110 */ 111 112 #include <sys/cdefs.h> 113 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.30 2002/10/12 19:45:54 wiz Exp $"); 114 115 #include <sys/param.h> 116 #include <sys/systm.h> 117 #include <sys/kernel.h> 118 #include <sys/malloc.h> 119 #include <sys/device.h> 120 #include <sys/fcntl.h> 121 #include <sys/proc.h> 122 123 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 124 125 #include <dev/pci/pcidevs.h> 126 #include <dev/pci/pcivar.h> 127 #include <dev/pci/auichreg.h> 128 129 #include <sys/audioio.h> 130 #include <dev/audio_if.h> 131 #include <dev/mulaw.h> 132 #include <dev/auconv.h> 133 134 #include <machine/bus.h> 135 136 #include <dev/ic/ac97reg.h> 137 #include <dev/ic/ac97var.h> 138 139 struct auich_dma { 140 bus_dmamap_t map; 141 caddr_t addr; 142 bus_dma_segment_t segs[1]; 143 int nsegs; 144 size_t size; 145 struct auich_dma *next; 146 }; 147 148 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 149 #define KERNADDR(p) ((void *)((p)->addr)) 150 151 struct auich_cdata { 152 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 153 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 154 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 155 }; 156 157 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 158 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 159 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 160 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 161 162 struct auich_softc { 163 struct device sc_dev; 164 void *sc_ih; 165 166 audio_device_t sc_audev; 167 168 bus_space_tag_t iot; 169 bus_space_handle_t mix_ioh; 170 bus_space_handle_t aud_ioh; 171 bus_dma_tag_t dmat; 172 173 struct ac97_codec_if *codec_if; 174 struct ac97_host_if host_if; 175 176 /* DMA scatter-gather lists. */ 177 bus_dmamap_t sc_cddmamap; 178 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 179 180 struct auich_cdata *sc_cdata; 181 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 182 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 183 #define dmalist_mici sc_cdata->ic_dmalist_mici 184 185 int ptr_pcmo, 186 ptr_pcmi, 187 ptr_mici; 188 189 /* i/o buffer pointers */ 190 u_int32_t pcmo_start, pcmo_p, pcmo_end; 191 int pcmo_blksize, pcmo_fifoe; 192 193 u_int32_t pcmi_start, pcmi_p, pcmi_end; 194 int pcmi_blksize, pcmi_fifoe; 195 196 u_int32_t mici_start, mici_p, mici_end; 197 int mici_blksize, mici_fifoe; 198 199 struct auich_dma *sc_dmas; 200 201 int sc_ignore_codecready; 202 /* SiS 7012 hack */ 203 int sc_sample_size; 204 int sc_sts_reg; 205 206 void (*sc_pintr)(void *); 207 void *sc_parg; 208 209 void (*sc_rintr)(void *); 210 void *sc_rarg; 211 212 /* Power Management */ 213 void *sc_powerhook; 214 int sc_suspend; 215 u_int16_t ext_status; 216 }; 217 218 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 219 & AC97_EXT_AUDIO_VRA) 220 221 /* Debug */ 222 #ifdef AUDIO_DEBUG 223 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 224 int auich_debug = 0xfffe; 225 #define ICH_DEBUG_CODECIO 0x0001 226 #define ICH_DEBUG_DMA 0x0002 227 #define ICH_DEBUG_PARAM 0x0004 228 #else 229 #define DPRINTF(x,y) /* nothing */ 230 #endif 231 232 int auich_match(struct device *, struct cfdata *, void *); 233 void auich_attach(struct device *, struct device *, void *); 234 int auich_intr(void *); 235 236 CFATTACH_DECL(auich, sizeof(struct auich_softc), 237 auich_match, auich_attach, NULL, NULL); 238 239 int auich_open(void *, int); 240 void auich_close(void *); 241 int auich_query_encoding(void *, struct audio_encoding *); 242 int auich_set_params(void *, int, int, struct audio_params *, 243 struct audio_params *); 244 int auich_round_blocksize(void *, int); 245 int auich_halt_output(void *); 246 int auich_halt_input(void *); 247 int auich_getdev(void *, struct audio_device *); 248 int auich_set_port(void *, mixer_ctrl_t *); 249 int auich_get_port(void *, mixer_ctrl_t *); 250 int auich_query_devinfo(void *, mixer_devinfo_t *); 251 void *auich_allocm(void *, int, size_t, int, int); 252 void auich_freem(void *, void *, int); 253 size_t auich_round_buffersize(void *, int, size_t); 254 paddr_t auich_mappage(void *, void *, off_t, int); 255 int auich_get_props(void *); 256 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 257 void *, struct audio_params *); 258 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 259 void *, struct audio_params *); 260 261 int auich_alloc_cdata(struct auich_softc *); 262 263 int auich_allocmem(struct auich_softc *, size_t, size_t, 264 struct auich_dma *); 265 int auich_freemem(struct auich_softc *, struct auich_dma *); 266 267 void auich_powerhook(int, void *); 268 int auich_set_rate(struct auich_softc *, int, u_long*); 269 void auich_calibrate(struct device *); 270 271 272 struct audio_hw_if auich_hw_if = { 273 auich_open, 274 auich_close, 275 NULL, /* drain */ 276 auich_query_encoding, 277 auich_set_params, 278 auich_round_blocksize, 279 NULL, /* commit_setting */ 280 NULL, /* init_output */ 281 NULL, /* init_input */ 282 NULL, /* start_output */ 283 NULL, /* start_input */ 284 auich_halt_output, 285 auich_halt_input, 286 NULL, /* speaker_ctl */ 287 auich_getdev, 288 NULL, /* getfd */ 289 auich_set_port, 290 auich_get_port, 291 auich_query_devinfo, 292 auich_allocm, 293 auich_freem, 294 auich_round_buffersize, 295 auich_mappage, 296 auich_get_props, 297 auich_trigger_output, 298 auich_trigger_input, 299 NULL, /* dev_ioctl */ 300 }; 301 302 int auich_attach_codec(void *, struct ac97_codec_if *); 303 int auich_read_codec(void *, u_int8_t, u_int16_t *); 304 int auich_write_codec(void *, u_int8_t, u_int16_t); 305 void auich_reset_codec(void *); 306 307 static const struct auich_devtype { 308 int vendor; 309 int product; 310 const char *name; 311 const char *shortname; 312 } auich_devices[] = { 313 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 314 "i82801AA (ICH) AC-97 Audio", "ICH" }, 315 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 316 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, /* i810-L */ 317 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 318 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 319 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 320 "i82440MX AC-97 Audio", "440MX" }, 321 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 322 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, /* i830Mx i845MP/MZ*/ 323 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 324 "i82801DB (ICH4) AC-97 Audio", "ICH4" }, /* i845E i845Gx */ 325 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 326 "SiS 7012 AC-97 Audio", "SiS7012" }, 327 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 328 "nForce MCP AC-97 Audio", "nForce-MCP" }, 329 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 330 "AMD768 AC-97 Audio", "AMD768" }, 331 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 332 "AMD8111 AC-97 Audio", "AMD8111" }, 333 { 0, 334 NULL, NULL }, 335 }; 336 337 static const struct auich_devtype * 338 auich_lookup(struct pci_attach_args *pa) 339 { 340 const struct auich_devtype *d; 341 342 for (d = auich_devices; d->name != NULL; d++) { 343 if (PCI_VENDOR(pa->pa_id) == d->vendor 344 && PCI_PRODUCT(pa->pa_id) == d->product) 345 return (d); 346 } 347 348 return (NULL); 349 } 350 351 int 352 auich_match(struct device *parent, struct cfdata *match, void *aux) 353 { 354 struct pci_attach_args *pa = aux; 355 356 if (auich_lookup(pa) != NULL) 357 return (1); 358 359 return (0); 360 } 361 362 void 363 auich_attach(struct device *parent, struct device *self, void *aux) 364 { 365 struct auich_softc *sc = (struct auich_softc *)self; 366 struct pci_attach_args *pa = aux; 367 pci_intr_handle_t ih; 368 bus_size_t mix_size, aud_size; 369 pcireg_t csr; 370 const char *intrstr; 371 const struct auich_devtype *d; 372 u_int32_t status; 373 374 d = auich_lookup(pa); 375 if (d == NULL) 376 panic("auich_attach: impossible"); 377 378 printf(": %s\n", d->name); 379 380 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 381 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 382 printf("%s: can't map codec i/o space\n", 383 sc->sc_dev.dv_xname); 384 return; 385 } 386 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 387 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 388 printf("%s: can't map device i/o space\n", 389 sc->sc_dev.dv_xname); 390 return; 391 } 392 sc->dmat = pa->pa_dmat; 393 394 /* enable bus mastering */ 395 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 396 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 397 csr | PCI_COMMAND_MASTER_ENABLE); 398 399 /* Map and establish the interrupt. */ 400 if (pci_intr_map(pa, &ih)) { 401 printf("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 402 return; 403 } 404 intrstr = pci_intr_string(pa->pa_pc, ih); 405 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 406 auich_intr, sc); 407 if (sc->sc_ih == NULL) { 408 printf("%s: can't establish interrupt", sc->sc_dev.dv_xname); 409 if (intrstr != NULL) 410 printf(" at %s", intrstr); 411 printf("\n"); 412 return; 413 } 414 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 415 416 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 417 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 418 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 419 420 /* SiS 7012 needs special handling */ 421 if (d->vendor == PCI_VENDOR_SIS 422 && d->product == PCI_PRODUCT_SIS_7012_AC) { 423 sc->sc_sts_reg = ICH_PICB; 424 sc->sc_sample_size = 1; 425 } else { 426 sc->sc_sts_reg = ICH_STS; 427 sc->sc_sample_size = 2; 428 } 429 /* nForce MCP quirk */ 430 if (d->vendor == PCI_VENDOR_NVIDIA 431 && d->product == PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC) { 432 sc->sc_ignore_codecready = TRUE; 433 } 434 435 436 /* Set up DMA lists. */ 437 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 438 auich_alloc_cdata(sc); 439 440 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 441 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 442 443 /* Reset codec and AC'97 */ 444 auich_reset_codec(sc); 445 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 446 if (!(status & ICH_PCR)) { /* reset failure */ 447 if (d->vendor == PCI_VENDOR_INTEL 448 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) { 449 /* MSI 845G Max never return ICH_PCR */ 450 sc->sc_ignore_codecready = TRUE; 451 } else { 452 return; 453 } 454 } 455 /* Print capabilities though there are no supports for now */ 456 if ((status & ICH_SAMPLE_CAP) == ICH_POM20) 457 printf("%s: 20 bit precision support\n", sc->sc_dev.dv_xname); 458 if ((status & ICH_CHAN_CAP) == ICH_PCM4) 459 printf("%s: 4ch PCM output support\n", sc->sc_dev.dv_xname); 460 if ((status & ICH_CHAN_CAP) == ICH_PCM6) 461 printf("%s: 6ch PCM output support\n", sc->sc_dev.dv_xname); 462 463 sc->host_if.arg = sc; 464 sc->host_if.attach = auich_attach_codec; 465 sc->host_if.read = auich_read_codec; 466 sc->host_if.write = auich_write_codec; 467 sc->host_if.reset = auich_reset_codec; 468 469 if (ac97_attach(&sc->host_if) != 0) 470 return; 471 472 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 473 474 /* Watch for power change */ 475 sc->sc_suspend = PWR_RESUME; 476 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 477 478 if (!IS_FIXED_RATE(sc->codec_if)) { 479 config_interrupts(self, auich_calibrate); 480 } 481 } 482 483 #define ICH_CODECIO_INTERVAL 10 484 int 485 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 486 { 487 struct auich_softc *sc = v; 488 int i; 489 uint32_t status; 490 491 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 492 if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) { 493 printf("auich_read_codec: codec is not ready (0x%x)\n", status); 494 *val = 0xffff; 495 return -1; 496 } 497 /* wait for an access semaphore */ 498 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 499 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 500 DELAY(ICH_CODECIO_INTERVAL)); 501 502 if (i > 0) { 503 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 504 DPRINTF(ICH_DEBUG_CODECIO, 505 ("auich_read_codec(%x, %x)\n", reg, *val)); 506 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 507 if (status & ICH_RCS) { 508 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 509 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 510 *val = 0xffff; 511 } 512 return 0; 513 } else { 514 DPRINTF(ICH_DEBUG_CODECIO, 515 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 516 return -1; 517 } 518 } 519 520 int 521 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 522 { 523 struct auich_softc *sc = v; 524 int i; 525 526 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 527 if (!sc->sc_ignore_codecready 528 && !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) { 529 printf("auich_write_codec: codec is not ready."); 530 return -1; 531 } 532 /* wait for an access semaphore */ 533 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 534 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 535 DELAY(ICH_CODECIO_INTERVAL)); 536 537 if (i > 0) { 538 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 539 return 0; 540 } else { 541 DPRINTF(ICH_DEBUG_CODECIO, 542 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 543 return -1; 544 } 545 } 546 547 int 548 auich_attach_codec(void *v, struct ac97_codec_if *cif) 549 { 550 struct auich_softc *sc = v; 551 552 sc->codec_if = cif; 553 return 0; 554 } 555 556 void 557 auich_reset_codec(void *v) 558 { 559 struct auich_softc *sc = v; 560 int i; 561 uint32_t control; 562 563 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 564 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 565 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 566 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 567 568 for (i = 500000; i-- && 569 !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR); 570 DELAY(1)); /* or ICH_SCR? */ 571 if (i <= 0) 572 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 573 } 574 575 int 576 auich_open(void *v, int flags) 577 { 578 return 0; 579 } 580 581 void 582 auich_close(void *v) 583 { 584 struct auich_softc *sc = v; 585 586 auich_halt_output(sc); 587 auich_halt_input(sc); 588 589 sc->sc_pintr = NULL; 590 sc->sc_rintr = NULL; 591 } 592 593 int 594 auich_query_encoding(void *v, struct audio_encoding *aep) 595 { 596 597 switch (aep->index) { 598 case 0: 599 strcpy(aep->name, AudioEulinear); 600 aep->encoding = AUDIO_ENCODING_ULINEAR; 601 aep->precision = 8; 602 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 603 return (0); 604 case 1: 605 strcpy(aep->name, AudioEmulaw); 606 aep->encoding = AUDIO_ENCODING_ULAW; 607 aep->precision = 8; 608 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 609 return (0); 610 case 2: 611 strcpy(aep->name, AudioEalaw); 612 aep->encoding = AUDIO_ENCODING_ALAW; 613 aep->precision = 8; 614 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 615 return (0); 616 case 3: 617 strcpy(aep->name, AudioEslinear); 618 aep->encoding = AUDIO_ENCODING_SLINEAR; 619 aep->precision = 8; 620 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 621 return (0); 622 case 4: 623 strcpy(aep->name, AudioEslinear_le); 624 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 625 aep->precision = 16; 626 aep->flags = 0; 627 return (0); 628 case 5: 629 strcpy(aep->name, AudioEulinear_le); 630 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 631 aep->precision = 16; 632 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 633 return (0); 634 case 6: 635 strcpy(aep->name, AudioEslinear_be); 636 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 637 aep->precision = 16; 638 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 639 return (0); 640 case 7: 641 strcpy(aep->name, AudioEulinear_be); 642 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 643 aep->precision = 16; 644 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 645 return (0); 646 default: 647 return (EINVAL); 648 } 649 } 650 651 int 652 auich_set_rate(struct auich_softc *sc, int mode, u_long* srate) 653 { 654 int reg; 655 656 reg = mode == AUMODE_PLAY 657 ? AC97_REG_PCM_FRONT_DAC_RATE : AC97_REG_PCM_LR_ADC_RATE; 658 return sc->codec_if->vtbl->set_rate(sc->codec_if, reg, srate); 659 } 660 661 int 662 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 663 struct audio_params *rec) 664 { 665 struct auich_softc *sc = v; 666 struct audio_params *p; 667 int mode; 668 669 for (mode = AUMODE_RECORD; mode != -1; 670 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 671 if ((setmode & mode) == 0) 672 continue; 673 674 p = mode == AUMODE_PLAY ? play : rec; 675 if (p == NULL) 676 continue; 677 678 if ((p->sample_rate != 8000) && 679 (p->sample_rate != 11025) && 680 (p->sample_rate != 16000) && 681 (p->sample_rate != 22050) && 682 (p->sample_rate != 32000) && 683 (p->sample_rate != 44100) && 684 (p->sample_rate != 48000)) 685 return (EINVAL); 686 687 p->factor = 1; 688 if (p->precision == 8) 689 p->factor *= 2; 690 691 p->sw_code = NULL; 692 /* setup hardware formats */ 693 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 694 p->hw_precision = 16; 695 696 /* If monaural is requested, aurateconv expands a monaural 697 * stream to stereo. */ 698 if (p->channels < 2) 699 p->hw_channels = 2; 700 701 switch (p->encoding) { 702 case AUDIO_ENCODING_SLINEAR_BE: 703 if (p->precision == 16) { 704 p->sw_code = swap_bytes; 705 } else { 706 if (mode == AUMODE_PLAY) 707 p->sw_code = linear8_to_linear16_le; 708 else 709 p->sw_code = linear16_to_linear8_le; 710 } 711 break; 712 713 case AUDIO_ENCODING_SLINEAR_LE: 714 if (p->precision != 16) { 715 if (mode == AUMODE_PLAY) 716 p->sw_code = linear8_to_linear16_le; 717 else 718 p->sw_code = linear16_to_linear8_le; 719 } 720 break; 721 722 case AUDIO_ENCODING_ULINEAR_BE: 723 if (p->precision == 16) { 724 if (mode == AUMODE_PLAY) 725 p->sw_code = 726 swap_bytes_change_sign16_le; 727 else 728 p->sw_code = 729 change_sign16_swap_bytes_le; 730 } else { 731 if (mode == AUMODE_PLAY) 732 p->sw_code = 733 ulinear8_to_slinear16_le; 734 else 735 p->sw_code = 736 slinear16_to_ulinear8_le; 737 } 738 break; 739 740 case AUDIO_ENCODING_ULINEAR_LE: 741 if (p->precision == 16) { 742 p->sw_code = change_sign16_le; 743 } else { 744 if (mode == AUMODE_PLAY) 745 p->sw_code = 746 ulinear8_to_slinear16_le; 747 else 748 p->sw_code = 749 slinear16_to_ulinear8_le; 750 } 751 break; 752 753 case AUDIO_ENCODING_ULAW: 754 if (mode == AUMODE_PLAY) { 755 p->sw_code = mulaw_to_slinear16_le; 756 } else { 757 p->sw_code = slinear16_to_mulaw_le; 758 } 759 break; 760 761 case AUDIO_ENCODING_ALAW: 762 if (mode == AUMODE_PLAY) { 763 p->sw_code = alaw_to_slinear16_le; 764 } else { 765 p->sw_code = slinear16_to_alaw_le; 766 } 767 break; 768 769 default: 770 return (EINVAL); 771 } 772 773 if (IS_FIXED_RATE(sc->codec_if)) { 774 p->hw_sample_rate = AC97_SINGLE_RATE; 775 /* If hw_sample_rate is changed, aurateconv works. */ 776 } else { 777 if (auich_set_rate(sc, mode, &p->sample_rate)) 778 return EINVAL; 779 } 780 } 781 782 return (0); 783 } 784 785 int 786 auich_round_blocksize(void *v, int blk) 787 { 788 789 return (blk & ~0x3f); /* keep good alignment */ 790 } 791 792 int 793 auich_halt_output(void *v) 794 { 795 struct auich_softc *sc = v; 796 797 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 798 799 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 800 801 return (0); 802 } 803 804 int 805 auich_halt_input(void *v) 806 { 807 struct auich_softc *sc = v; 808 809 DPRINTF(ICH_DEBUG_DMA, 810 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 811 812 /* XXX halt both unless known otherwise */ 813 814 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 815 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 816 817 return (0); 818 } 819 820 int 821 auich_getdev(void *v, struct audio_device *adp) 822 { 823 struct auich_softc *sc = v; 824 825 *adp = sc->sc_audev; 826 return (0); 827 } 828 829 int 830 auich_set_port(void *v, mixer_ctrl_t *cp) 831 { 832 struct auich_softc *sc = v; 833 834 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 835 } 836 837 int 838 auich_get_port(void *v, mixer_ctrl_t *cp) 839 { 840 struct auich_softc *sc = v; 841 842 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 843 } 844 845 int 846 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 847 { 848 struct auich_softc *sc = v; 849 850 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 851 } 852 853 void * 854 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 855 { 856 struct auich_softc *sc = v; 857 struct auich_dma *p; 858 int error; 859 860 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 861 return (NULL); 862 863 p = malloc(sizeof(*p), pool, flags|M_ZERO); 864 if (p == NULL) 865 return (NULL); 866 867 error = auich_allocmem(sc, size, 0, p); 868 if (error) { 869 free(p, pool); 870 return (NULL); 871 } 872 873 p->next = sc->sc_dmas; 874 sc->sc_dmas = p; 875 876 return (KERNADDR(p)); 877 } 878 879 void 880 auich_freem(void *v, void *ptr, int pool) 881 { 882 struct auich_softc *sc = v; 883 struct auich_dma *p, **pp; 884 885 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 886 if (KERNADDR(p) == ptr) { 887 auich_freemem(sc, p); 888 *pp = p->next; 889 free(p, pool); 890 return; 891 } 892 } 893 } 894 895 size_t 896 auich_round_buffersize(void *v, int direction, size_t size) 897 { 898 899 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 900 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 901 902 return size; 903 } 904 905 paddr_t 906 auich_mappage(void *v, void *mem, off_t off, int prot) 907 { 908 struct auich_softc *sc = v; 909 struct auich_dma *p; 910 911 if (off < 0) 912 return (-1); 913 914 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 915 ; 916 if (!p) 917 return (-1); 918 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 919 off, prot, BUS_DMA_WAITOK)); 920 } 921 922 int 923 auich_get_props(void *v) 924 { 925 struct auich_softc *sc = v; 926 int props; 927 928 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 929 /* 930 * Even if the codec is fixed-rate, set_param() succeeds for any sample 931 * rate because of aurateconv. Applications can't know what rate the 932 * device can process in the case of mmap(). 933 */ 934 if (!IS_FIXED_RATE(sc->codec_if)) 935 props |= AUDIO_PROP_MMAP; 936 return props; 937 } 938 939 int 940 auich_intr(void *v) 941 { 942 struct auich_softc *sc = v; 943 int ret = 0, sts, gsts, i, qptr; 944 945 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 946 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 947 948 if (gsts & ICH_POINT) { 949 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 950 DPRINTF(ICH_DEBUG_DMA, 951 ("auich_intr: osts=0x%x\n", sts)); 952 953 if (sts & ICH_FIFOE) { 954 printf("%s: fifo underrun # %u\n", 955 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 956 } 957 958 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 959 if (sts & (ICH_LVBCI | ICH_CELV)) { 960 struct auich_dmalist *q; 961 962 qptr = sc->ptr_pcmo; 963 964 while (qptr != i) { 965 q = &sc->dmalist_pcmo[qptr]; 966 967 q->base = sc->pcmo_p; 968 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 969 DPRINTF(ICH_DEBUG_DMA, 970 ("auich_intr: %p, %p = %x @ 0x%x\n", 971 &sc->dmalist_pcmo[i], q, 972 sc->pcmo_blksize / 2, sc->pcmo_p)); 973 974 sc->pcmo_p += sc->pcmo_blksize; 975 if (sc->pcmo_p >= sc->pcmo_end) 976 sc->pcmo_p = sc->pcmo_start; 977 978 if (++qptr == ICH_DMALIST_MAX) 979 qptr = 0; 980 } 981 982 sc->ptr_pcmo = qptr; 983 bus_space_write_1(sc->iot, sc->aud_ioh, 984 ICH_PCMO + ICH_LVI, 985 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 986 } 987 988 if (sts & ICH_BCIS && sc->sc_pintr) 989 sc->sc_pintr(sc->sc_parg); 990 991 /* int ack */ 992 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 993 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 994 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 995 ret++; 996 } 997 998 if (gsts & ICH_PIINT) { 999 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1000 DPRINTF(ICH_DEBUG_DMA, 1001 ("auich_intr: ists=0x%x\n", sts)); 1002 1003 if (sts & ICH_FIFOE) { 1004 printf("%s: fifo overrun # %u\n", 1005 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1006 } 1007 1008 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1009 if (sts & (ICH_LVBCI | ICH_CELV)) { 1010 struct auich_dmalist *q; 1011 1012 qptr = sc->ptr_pcmi; 1013 1014 while (qptr != i) { 1015 q = &sc->dmalist_pcmi[qptr]; 1016 1017 q->base = sc->pcmi_p; 1018 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1019 DPRINTF(ICH_DEBUG_DMA, 1020 ("auich_intr: %p, %p = %x @ 0x%x\n", 1021 &sc->dmalist_pcmi[i], q, 1022 sc->pcmi_blksize / 2, sc->pcmi_p)); 1023 1024 sc->pcmi_p += sc->pcmi_blksize; 1025 if (sc->pcmi_p >= sc->pcmi_end) 1026 sc->pcmi_p = sc->pcmi_start; 1027 1028 if (++qptr == ICH_DMALIST_MAX) 1029 qptr = 0; 1030 } 1031 1032 sc->ptr_pcmi = qptr; 1033 bus_space_write_1(sc->iot, sc->aud_ioh, 1034 ICH_PCMI + ICH_LVI, 1035 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1036 } 1037 1038 if (sts & ICH_BCIS && sc->sc_rintr) 1039 sc->sc_rintr(sc->sc_rarg); 1040 1041 /* int ack */ 1042 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1043 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1044 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1045 ret++; 1046 } 1047 1048 if (gsts & ICH_MIINT) { 1049 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1050 DPRINTF(ICH_DEBUG_DMA, 1051 ("auich_intr: ists=0x%x\n", sts)); 1052 if (sts & ICH_FIFOE) 1053 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1054 1055 /* TODO mic input dma */ 1056 1057 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1058 } 1059 1060 return ret; 1061 } 1062 1063 int 1064 auich_trigger_output(void *v, void *start, void *end, int blksize, 1065 void (*intr)(void *), void *arg, struct audio_params *param) 1066 { 1067 struct auich_softc *sc = v; 1068 struct auich_dmalist *q; 1069 struct auich_dma *p; 1070 size_t size; 1071 1072 DPRINTF(ICH_DEBUG_DMA, 1073 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1074 start, end, blksize, intr, arg, param)); 1075 1076 sc->sc_pintr = intr; 1077 sc->sc_parg = arg; 1078 1079 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1080 ; 1081 if (!p) { 1082 printf("auich_trigger_output: bad addr %p\n", start); 1083 return (EINVAL); 1084 } 1085 1086 size = (size_t)((caddr_t)end - (caddr_t)start); 1087 1088 /* 1089 * The logic behind this is: 1090 * setup one buffer to play, then LVI dump out the rest 1091 * to the scatter-gather chain. 1092 */ 1093 sc->pcmo_start = DMAADDR(p); 1094 sc->pcmo_p = sc->pcmo_start + blksize; 1095 sc->pcmo_end = sc->pcmo_start + size; 1096 sc->pcmo_blksize = blksize; 1097 1098 sc->ptr_pcmo = 0; 1099 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1100 q->base = sc->pcmo_start; 1101 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1102 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1103 sc->ptr_pcmo = 0; 1104 1105 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1106 sc->sc_cddma + ICH_PCMO_OFF(0)); 1107 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1108 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1109 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1110 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1111 1112 return (0); 1113 } 1114 1115 int 1116 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1117 void *v; 1118 void *start, *end; 1119 int blksize; 1120 void (*intr)(void *); 1121 void *arg; 1122 struct audio_params *param; 1123 { 1124 struct auich_softc *sc = v; 1125 struct auich_dmalist *q; 1126 struct auich_dma *p; 1127 size_t size; 1128 1129 DPRINTF(ICH_DEBUG_DMA, 1130 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1131 start, end, blksize, intr, arg, param)); 1132 1133 sc->sc_rintr = intr; 1134 sc->sc_rarg = arg; 1135 1136 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1137 ; 1138 if (!p) { 1139 printf("auich_trigger_input: bad addr %p\n", start); 1140 return (EINVAL); 1141 } 1142 1143 size = (size_t)((caddr_t)end - (caddr_t)start); 1144 1145 /* 1146 * The logic behind this is: 1147 * setup one buffer to play, then LVI dump out the rest 1148 * to the scatter-gather chain. 1149 */ 1150 sc->pcmi_start = DMAADDR(p); 1151 sc->pcmi_p = sc->pcmi_start + blksize; 1152 sc->pcmi_end = sc->pcmi_start + size; 1153 sc->pcmi_blksize = blksize; 1154 1155 sc->ptr_pcmi = 0; 1156 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1157 q->base = sc->pcmi_start; 1158 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1159 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1160 sc->ptr_pcmi = 0; 1161 1162 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1163 sc->sc_cddma + ICH_PCMI_OFF(0)); 1164 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1165 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1166 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1167 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1168 1169 return (0); 1170 } 1171 1172 int 1173 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1174 struct auich_dma *p) 1175 { 1176 int error; 1177 1178 p->size = size; 1179 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1180 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1181 &p->nsegs, BUS_DMA_NOWAIT); 1182 if (error) 1183 return (error); 1184 1185 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1186 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1187 if (error) 1188 goto free; 1189 1190 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1191 0, BUS_DMA_NOWAIT, &p->map); 1192 if (error) 1193 goto unmap; 1194 1195 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1196 BUS_DMA_NOWAIT); 1197 if (error) 1198 goto destroy; 1199 return (0); 1200 1201 destroy: 1202 bus_dmamap_destroy(sc->dmat, p->map); 1203 unmap: 1204 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1205 free: 1206 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1207 return (error); 1208 } 1209 1210 int 1211 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1212 { 1213 1214 bus_dmamap_unload(sc->dmat, p->map); 1215 bus_dmamap_destroy(sc->dmat, p->map); 1216 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1217 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1218 return (0); 1219 } 1220 1221 int 1222 auich_alloc_cdata(struct auich_softc *sc) 1223 { 1224 bus_dma_segment_t seg; 1225 int error, rseg; 1226 1227 /* 1228 * Allocate the control data structure, and create and load the 1229 * DMA map for it. 1230 */ 1231 if ((error = bus_dmamem_alloc(sc->dmat, 1232 sizeof(struct auich_cdata), 1233 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1234 printf("%s: unable to allocate control data, error = %d\n", 1235 sc->sc_dev.dv_xname, error); 1236 goto fail_0; 1237 } 1238 1239 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1240 sizeof(struct auich_cdata), 1241 (caddr_t *) &sc->sc_cdata, 1242 BUS_DMA_COHERENT)) != 0) { 1243 printf("%s: unable to map control data, error = %d\n", 1244 sc->sc_dev.dv_xname, error); 1245 goto fail_1; 1246 } 1247 1248 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1249 sizeof(struct auich_cdata), 0, 0, 1250 &sc->sc_cddmamap)) != 0) { 1251 printf("%s: unable to create control data DMA map, " 1252 "error = %d\n", sc->sc_dev.dv_xname, error); 1253 goto fail_2; 1254 } 1255 1256 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1257 sc->sc_cdata, sizeof(struct auich_cdata), 1258 NULL, 0)) != 0) { 1259 printf("%s: unable tp load control data DMA map, " 1260 "error = %d\n", sc->sc_dev.dv_xname, error); 1261 goto fail_3; 1262 } 1263 1264 return (0); 1265 1266 fail_3: 1267 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1268 fail_2: 1269 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1270 sizeof(struct auich_cdata)); 1271 fail_1: 1272 bus_dmamem_free(sc->dmat, &seg, rseg); 1273 fail_0: 1274 return (error); 1275 } 1276 1277 void 1278 auich_powerhook(int why, void *addr) 1279 { 1280 struct auich_softc *sc = (struct auich_softc *)addr; 1281 1282 switch (why) { 1283 case PWR_SUSPEND: 1284 case PWR_STANDBY: 1285 /* Power down */ 1286 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1287 sc->sc_suspend = why; 1288 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1289 break; 1290 1291 case PWR_RESUME: 1292 /* Wake up */ 1293 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1294 if (sc->sc_suspend == PWR_RESUME) { 1295 printf("%s: resume without suspend.\n", 1296 sc->sc_dev.dv_xname); 1297 sc->sc_suspend = why; 1298 return; 1299 } 1300 sc->sc_suspend = why; 1301 auich_reset_codec(sc); 1302 DELAY(1000); 1303 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1304 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1305 break; 1306 1307 case PWR_SOFTSUSPEND: 1308 case PWR_SOFTSTANDBY: 1309 case PWR_SOFTRESUME: 1310 break; 1311 } 1312 } 1313 1314 1315 /* -------------------------------------------------------------------- */ 1316 /* Calibrate card (some boards are overclocked and need scaling) */ 1317 1318 void 1319 auich_calibrate(struct device *self) 1320 { 1321 struct auich_softc *sc; 1322 struct timeval t1, t2; 1323 u_int8_t ociv, nciv; 1324 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1325 void *temp_buffer; 1326 struct auich_dma *p; 1327 1328 sc = (struct auich_softc*)self; 1329 /* 1330 * Grab audio from input for fixed interval and compare how 1331 * much we actually get with what we expect. Interval needs 1332 * to be sufficiently short that no interrupts are 1333 * generated. 1334 */ 1335 1336 /* Setup a buffer */ 1337 bytes = 16000; 1338 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1339 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1340 ; 1341 if (p == NULL) { 1342 printf("auich_calibrate: bad address %p\n", temp_buffer); 1343 return; 1344 } 1345 sc->dmalist_pcmi[0].base = DMAADDR(p); 1346 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size) | ICH_DMAF_IOC; 1347 1348 /* 1349 * our data format is stereo, 16 bit so each sample is 4 bytes. 1350 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1351 * we're going to start recording with interrupts disabled and measure 1352 * the time taken for one block to complete. we know the block size, 1353 * we know the time in microseconds, we calculate the sample rate: 1354 * 1355 * actual_rate [bps] = bytes / (time [s] * 4) 1356 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1357 * actual_rate [Hz] = (bytes * 250000) / time [us] 1358 */ 1359 1360 /* prepare */ 1361 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1362 nciv = ociv; 1363 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1364 sc->sc_cddma + ICH_PCMI_OFF(0)); 1365 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1366 (0 - 1) & ICH_LVI_MASK); 1367 1368 /* start */ 1369 microtime(&t1); 1370 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1371 1372 /* wait */ 1373 while (nciv == ociv) { 1374 microtime(&t2); 1375 if (t2.tv_sec - t1.tv_sec > 1) 1376 break; 1377 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1378 ICH_PCMI + ICH_CIV); 1379 } 1380 microtime(&t2); 1381 1382 /* stop */ 1383 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1384 1385 /* reset */ 1386 DELAY(100); 1387 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1388 1389 /* turn time delta into us */ 1390 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1391 1392 auich_freem(sc, temp_buffer, M_DEVBUF); 1393 1394 if (nciv == ociv) { 1395 printf("%s: ac97 link rate calibration timed out after %d us\n", 1396 sc->sc_dev.dv_xname, wait_us); 1397 return; 1398 } 1399 1400 actual_48k_rate = (bytes * 250000U) / wait_us; 1401 1402 if (actual_48k_rate <= 48500) 1403 ac97rate = 48000; 1404 else 1405 ac97rate = actual_48k_rate; 1406 1407 printf("%s: measured ac97 link rate at %d Hz", 1408 sc->sc_dev.dv_xname, actual_48k_rate); 1409 if (ac97rate != actual_48k_rate) 1410 printf(", will use %d Hz", ac97rate); 1411 printf("\n"); 1412 1413 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1414 } 1415
Indexes created Thu Oct 23 18:09:57 GMT 2025