auich.c revision 1.33
1 /* $NetBSD: auich.c,v 1.33 2003/01/21 16:05:21 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * 107 * TODO: 108 * - Add support for the dedicated microphone input. 109 * - 4ch/6ch support. 110 * 111 * NOTE: 112 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 113 * It causes PCI master abort and hangups until cold reboot. 114 * http://www.intel.com/design/chipsets/specupdt/245051.htm 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.33 2003/01/21 16:05:21 kent Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/kernel.h> 123 #include <sys/malloc.h> 124 #include <sys/device.h> 125 #include <sys/fcntl.h> 126 #include <sys/proc.h> 127 128 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 129 130 #include <dev/pci/pcidevs.h> 131 #include <dev/pci/pcivar.h> 132 #include <dev/pci/auichreg.h> 133 134 #include <sys/audioio.h> 135 #include <dev/audio_if.h> 136 #include <dev/mulaw.h> 137 #include <dev/auconv.h> 138 139 #include <machine/bus.h> 140 141 #include <dev/ic/ac97reg.h> 142 #include <dev/ic/ac97var.h> 143 144 struct auich_dma { 145 bus_dmamap_t map; 146 caddr_t addr; 147 bus_dma_segment_t segs[1]; 148 int nsegs; 149 size_t size; 150 struct auich_dma *next; 151 }; 152 153 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 154 #define KERNADDR(p) ((void *)((p)->addr)) 155 156 struct auich_cdata { 157 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 158 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 159 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 160 }; 161 162 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 163 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 164 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 165 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 166 167 struct auich_softc { 168 struct device sc_dev; 169 void *sc_ih; 170 171 audio_device_t sc_audev; 172 173 bus_space_tag_t iot; 174 bus_space_handle_t mix_ioh; 175 bus_space_handle_t aud_ioh; 176 bus_dma_tag_t dmat; 177 178 struct ac97_codec_if *codec_if; 179 struct ac97_host_if host_if; 180 181 /* DMA scatter-gather lists. */ 182 bus_dmamap_t sc_cddmamap; 183 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 184 185 struct auich_cdata *sc_cdata; 186 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 187 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 188 #define dmalist_mici sc_cdata->ic_dmalist_mici 189 190 int ptr_pcmo, 191 ptr_pcmi, 192 ptr_mici; 193 194 /* i/o buffer pointers */ 195 u_int32_t pcmo_start, pcmo_p, pcmo_end; 196 int pcmo_blksize, pcmo_fifoe; 197 198 u_int32_t pcmi_start, pcmi_p, pcmi_end; 199 int pcmi_blksize, pcmi_fifoe; 200 201 u_int32_t mici_start, mici_p, mici_end; 202 int mici_blksize, mici_fifoe; 203 204 struct auich_dma *sc_dmas; 205 206 #ifdef DIAGNOSTIC 207 pci_chipset_tag_t sc_pc; 208 pcitag_t sc_pt; 209 #endif 210 int sc_ignore_codecready; 211 /* SiS 7012 hack */ 212 int sc_sample_size; 213 int sc_sts_reg; 214 215 void (*sc_pintr)(void *); 216 void *sc_parg; 217 218 void (*sc_rintr)(void *); 219 void *sc_rarg; 220 221 /* Power Management */ 222 void *sc_powerhook; 223 int sc_suspend; 224 u_int16_t ext_status; 225 }; 226 227 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 228 & AC97_EXT_AUDIO_VRA) 229 230 /* Debug */ 231 #ifdef AUDIO_DEBUG 232 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 233 int auich_debug = 0xfffe; 234 #define ICH_DEBUG_CODECIO 0x0001 235 #define ICH_DEBUG_DMA 0x0002 236 #define ICH_DEBUG_PARAM 0x0004 237 #else 238 #define DPRINTF(x,y) /* nothing */ 239 #endif 240 241 int auich_match(struct device *, struct cfdata *, void *); 242 void auich_attach(struct device *, struct device *, void *); 243 int auich_intr(void *); 244 245 CFATTACH_DECL(auich, sizeof(struct auich_softc), 246 auich_match, auich_attach, NULL, NULL); 247 248 int auich_open(void *, int); 249 void auich_close(void *); 250 int auich_query_encoding(void *, struct audio_encoding *); 251 int auich_set_params(void *, int, int, struct audio_params *, 252 struct audio_params *); 253 int auich_round_blocksize(void *, int); 254 int auich_halt_output(void *); 255 int auich_halt_input(void *); 256 int auich_getdev(void *, struct audio_device *); 257 int auich_set_port(void *, mixer_ctrl_t *); 258 int auich_get_port(void *, mixer_ctrl_t *); 259 int auich_query_devinfo(void *, mixer_devinfo_t *); 260 void *auich_allocm(void *, int, size_t, int, int); 261 void auich_freem(void *, void *, int); 262 size_t auich_round_buffersize(void *, int, size_t); 263 paddr_t auich_mappage(void *, void *, off_t, int); 264 int auich_get_props(void *); 265 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 266 void *, struct audio_params *); 267 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 268 void *, struct audio_params *); 269 270 int auich_alloc_cdata(struct auich_softc *); 271 272 int auich_allocmem(struct auich_softc *, size_t, size_t, 273 struct auich_dma *); 274 int auich_freemem(struct auich_softc *, struct auich_dma *); 275 276 void auich_powerhook(int, void *); 277 int auich_set_rate(struct auich_softc *, int, u_long); 278 void auich_calibrate(struct device *); 279 280 281 struct audio_hw_if auich_hw_if = { 282 auich_open, 283 auich_close, 284 NULL, /* drain */ 285 auich_query_encoding, 286 auich_set_params, 287 auich_round_blocksize, 288 NULL, /* commit_setting */ 289 NULL, /* init_output */ 290 NULL, /* init_input */ 291 NULL, /* start_output */ 292 NULL, /* start_input */ 293 auich_halt_output, 294 auich_halt_input, 295 NULL, /* speaker_ctl */ 296 auich_getdev, 297 NULL, /* getfd */ 298 auich_set_port, 299 auich_get_port, 300 auich_query_devinfo, 301 auich_allocm, 302 auich_freem, 303 auich_round_buffersize, 304 auich_mappage, 305 auich_get_props, 306 auich_trigger_output, 307 auich_trigger_input, 308 NULL, /* dev_ioctl */ 309 }; 310 311 int auich_attach_codec(void *, struct ac97_codec_if *); 312 int auich_read_codec(void *, u_int8_t, u_int16_t *); 313 int auich_write_codec(void *, u_int8_t, u_int16_t); 314 void auich_reset_codec(void *); 315 316 static const struct auich_devtype { 317 int vendor; 318 int product; 319 const char *name; 320 const char *shortname; 321 } auich_devices[] = { 322 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 323 "i82801AA (ICH) AC-97 Audio", "ICH" }, 324 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 325 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, /* i810-L */ 326 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 327 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 328 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 329 "i82440MX AC-97 Audio", "440MX" }, 330 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 331 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, /* i830Mx i845MP/MZ*/ 332 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 333 "i82801DB (ICH4) AC-97 Audio", "ICH4" }, /* i845E i845Gx */ 334 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 335 "SiS 7012 AC-97 Audio", "SiS7012" }, 336 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 337 "nForce MCP AC-97 Audio", "nForce-MCP" }, 338 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 339 "nForce2 MCP-T AC-97 Audio", "nForce-MCP-T" }, 340 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 341 "AMD768 AC-97 Audio", "AMD768" }, 342 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 343 "AMD8111 AC-97 Audio", "AMD8111" }, 344 { 0, 345 NULL, NULL }, 346 }; 347 348 static const struct auich_devtype * 349 auich_lookup(struct pci_attach_args *pa) 350 { 351 const struct auich_devtype *d; 352 353 for (d = auich_devices; d->name != NULL; d++) { 354 if (PCI_VENDOR(pa->pa_id) == d->vendor 355 && PCI_PRODUCT(pa->pa_id) == d->product) 356 return (d); 357 } 358 359 return (NULL); 360 } 361 362 int 363 auich_match(struct device *parent, struct cfdata *match, void *aux) 364 { 365 struct pci_attach_args *pa = aux; 366 367 if (auich_lookup(pa) != NULL) 368 return (1); 369 370 return (0); 371 } 372 373 void 374 auich_attach(struct device *parent, struct device *self, void *aux) 375 { 376 struct auich_softc *sc = (struct auich_softc *)self; 377 struct pci_attach_args *pa = aux; 378 pci_intr_handle_t ih; 379 bus_size_t mix_size, aud_size; 380 pcireg_t csr; 381 const char *intrstr; 382 const struct auich_devtype *d; 383 u_int32_t status; 384 385 d = auich_lookup(pa); 386 if (d == NULL) 387 panic("auich_attach: impossible"); 388 389 #ifdef DIAGNOSTIC 390 sc->sc_pc = pa->pa_pc; 391 sc->sc_pt = pa->pa_tag; 392 #endif 393 printf(": %s\n", d->name); 394 395 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 396 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 397 printf("%s: can't map codec i/o space\n", 398 sc->sc_dev.dv_xname); 399 return; 400 } 401 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 402 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 403 printf("%s: can't map device i/o space\n", 404 sc->sc_dev.dv_xname); 405 return; 406 } 407 sc->dmat = pa->pa_dmat; 408 409 /* enable bus mastering */ 410 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 411 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 412 csr | PCI_COMMAND_MASTER_ENABLE); 413 414 /* Map and establish the interrupt. */ 415 if (pci_intr_map(pa, &ih)) { 416 printf("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 417 return; 418 } 419 intrstr = pci_intr_string(pa->pa_pc, ih); 420 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 421 auich_intr, sc); 422 if (sc->sc_ih == NULL) { 423 printf("%s: can't establish interrupt", sc->sc_dev.dv_xname); 424 if (intrstr != NULL) 425 printf(" at %s", intrstr); 426 printf("\n"); 427 return; 428 } 429 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 430 431 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 432 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 433 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 434 435 /* SiS 7012 needs special handling */ 436 if (d->vendor == PCI_VENDOR_SIS 437 && d->product == PCI_PRODUCT_SIS_7012_AC) { 438 sc->sc_sts_reg = ICH_PICB; 439 sc->sc_sample_size = 1; 440 } else { 441 sc->sc_sts_reg = ICH_STS; 442 sc->sc_sample_size = 2; 443 } 444 /* nForce MCP quirk */ 445 if (d->vendor == PCI_VENDOR_NVIDIA 446 && d->product == PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC) { 447 sc->sc_ignore_codecready = TRUE; 448 } 449 450 451 /* Set up DMA lists. */ 452 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 453 auich_alloc_cdata(sc); 454 455 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 456 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 457 458 /* Reset codec and AC'97 */ 459 auich_reset_codec(sc); 460 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 461 if (!(status & ICH_PCR)) { /* reset failure */ 462 if (d->vendor == PCI_VENDOR_INTEL 463 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) { 464 /* MSI 845G Max never return ICH_PCR */ 465 sc->sc_ignore_codecready = TRUE; 466 } else { 467 return; 468 } 469 } 470 /* Print capabilities though there are no supports for now */ 471 if ((status & ICH_SAMPLE_CAP) == ICH_POM20) 472 printf("%s: 20 bit precision support\n", sc->sc_dev.dv_xname); 473 if ((status & ICH_CHAN_CAP) == ICH_PCM4) 474 printf("%s: 4ch PCM output support\n", sc->sc_dev.dv_xname); 475 if ((status & ICH_CHAN_CAP) == ICH_PCM6) 476 printf("%s: 6ch PCM output support\n", sc->sc_dev.dv_xname); 477 478 sc->host_if.arg = sc; 479 sc->host_if.attach = auich_attach_codec; 480 sc->host_if.read = auich_read_codec; 481 sc->host_if.write = auich_write_codec; 482 sc->host_if.reset = auich_reset_codec; 483 484 if (ac97_attach(&sc->host_if) != 0) 485 return; 486 487 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 488 489 /* Watch for power change */ 490 sc->sc_suspend = PWR_RESUME; 491 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 492 493 if (!IS_FIXED_RATE(sc->codec_if)) { 494 config_interrupts(self, auich_calibrate); 495 } 496 } 497 498 #define ICH_CODECIO_INTERVAL 10 499 int 500 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 501 { 502 struct auich_softc *sc = v; 503 int i; 504 uint32_t status; 505 506 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 507 if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) { 508 printf("auich_read_codec: codec is not ready (0x%x)\n", status); 509 *val = 0xffff; 510 return -1; 511 } 512 /* wait for an access semaphore */ 513 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 514 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 515 DELAY(ICH_CODECIO_INTERVAL)); 516 517 if (i > 0) { 518 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 519 DPRINTF(ICH_DEBUG_CODECIO, 520 ("auich_read_codec(%x, %x)\n", reg, *val)); 521 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 522 if (status & ICH_RCS) { 523 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 524 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 525 *val = 0xffff; 526 } 527 return 0; 528 } else { 529 DPRINTF(ICH_DEBUG_CODECIO, 530 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 531 return -1; 532 } 533 } 534 535 int 536 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 537 { 538 struct auich_softc *sc = v; 539 int i; 540 541 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 542 if (!sc->sc_ignore_codecready 543 && !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) { 544 printf("auich_write_codec: codec is not ready."); 545 return -1; 546 } 547 /* wait for an access semaphore */ 548 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 549 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 550 DELAY(ICH_CODECIO_INTERVAL)); 551 552 if (i > 0) { 553 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 554 return 0; 555 } else { 556 DPRINTF(ICH_DEBUG_CODECIO, 557 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 558 return -1; 559 } 560 } 561 562 int 563 auich_attach_codec(void *v, struct ac97_codec_if *cif) 564 { 565 struct auich_softc *sc = v; 566 567 sc->codec_if = cif; 568 return 0; 569 } 570 571 void 572 auich_reset_codec(void *v) 573 { 574 struct auich_softc *sc = v; 575 int i; 576 uint32_t control; 577 578 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 579 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 580 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 581 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 582 583 for (i = 500000; i-- && 584 !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR); 585 DELAY(1)); /* or ICH_SCR? */ 586 if (i <= 0) 587 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 588 } 589 590 int 591 auich_open(void *v, int flags) 592 { 593 return 0; 594 } 595 596 void 597 auich_close(void *v) 598 { 599 struct auich_softc *sc = v; 600 601 auich_halt_output(sc); 602 auich_halt_input(sc); 603 604 sc->sc_pintr = NULL; 605 sc->sc_rintr = NULL; 606 } 607 608 int 609 auich_query_encoding(void *v, struct audio_encoding *aep) 610 { 611 612 switch (aep->index) { 613 case 0: 614 strcpy(aep->name, AudioEulinear); 615 aep->encoding = AUDIO_ENCODING_ULINEAR; 616 aep->precision = 8; 617 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 618 return (0); 619 case 1: 620 strcpy(aep->name, AudioEmulaw); 621 aep->encoding = AUDIO_ENCODING_ULAW; 622 aep->precision = 8; 623 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 624 return (0); 625 case 2: 626 strcpy(aep->name, AudioEalaw); 627 aep->encoding = AUDIO_ENCODING_ALAW; 628 aep->precision = 8; 629 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 630 return (0); 631 case 3: 632 strcpy(aep->name, AudioEslinear); 633 aep->encoding = AUDIO_ENCODING_SLINEAR; 634 aep->precision = 8; 635 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 636 return (0); 637 case 4: 638 strcpy(aep->name, AudioEslinear_le); 639 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 640 aep->precision = 16; 641 aep->flags = 0; 642 return (0); 643 case 5: 644 strcpy(aep->name, AudioEulinear_le); 645 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 646 aep->precision = 16; 647 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 648 return (0); 649 case 6: 650 strcpy(aep->name, AudioEslinear_be); 651 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 652 aep->precision = 16; 653 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 654 return (0); 655 case 7: 656 strcpy(aep->name, AudioEulinear_be); 657 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 658 aep->precision = 16; 659 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 660 return (0); 661 default: 662 return (EINVAL); 663 } 664 } 665 666 int 667 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 668 { 669 int reg; 670 u_long ratetmp; 671 672 ratetmp = srate; 673 reg = mode == AUMODE_PLAY 674 ? AC97_REG_PCM_FRONT_DAC_RATE : AC97_REG_PCM_LR_ADC_RATE; 675 return sc->codec_if->vtbl->set_rate(sc->codec_if, reg, &ratetmp); 676 } 677 678 int 679 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 680 struct audio_params *rec) 681 { 682 struct auich_softc *sc = v; 683 struct audio_params *p; 684 int mode; 685 686 for (mode = AUMODE_RECORD; mode != -1; 687 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 688 if ((setmode & mode) == 0) 689 continue; 690 691 p = mode == AUMODE_PLAY ? play : rec; 692 if (p == NULL) 693 continue; 694 695 if ((p->sample_rate != 8000) && 696 (p->sample_rate != 11025) && 697 (p->sample_rate != 16000) && 698 (p->sample_rate != 22050) && 699 (p->sample_rate != 32000) && 700 (p->sample_rate != 44100) && 701 (p->sample_rate != 48000)) 702 return (EINVAL); 703 704 p->factor = 1; 705 if (p->precision == 8) 706 p->factor *= 2; 707 708 p->sw_code = NULL; 709 /* setup hardware formats */ 710 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 711 p->hw_precision = 16; 712 713 /* If monaural is requested, aurateconv expands a monaural 714 * stream to stereo. */ 715 if (p->channels < 2) 716 p->hw_channels = 2; 717 718 switch (p->encoding) { 719 case AUDIO_ENCODING_SLINEAR_BE: 720 if (p->precision == 16) { 721 p->sw_code = swap_bytes; 722 } else { 723 if (mode == AUMODE_PLAY) 724 p->sw_code = linear8_to_linear16_le; 725 else 726 p->sw_code = linear16_to_linear8_le; 727 } 728 break; 729 730 case AUDIO_ENCODING_SLINEAR_LE: 731 if (p->precision != 16) { 732 if (mode == AUMODE_PLAY) 733 p->sw_code = linear8_to_linear16_le; 734 else 735 p->sw_code = linear16_to_linear8_le; 736 } 737 break; 738 739 case AUDIO_ENCODING_ULINEAR_BE: 740 if (p->precision == 16) { 741 if (mode == AUMODE_PLAY) 742 p->sw_code = 743 swap_bytes_change_sign16_le; 744 else 745 p->sw_code = 746 change_sign16_swap_bytes_le; 747 } else { 748 if (mode == AUMODE_PLAY) 749 p->sw_code = 750 ulinear8_to_slinear16_le; 751 else 752 p->sw_code = 753 slinear16_to_ulinear8_le; 754 } 755 break; 756 757 case AUDIO_ENCODING_ULINEAR_LE: 758 if (p->precision == 16) { 759 p->sw_code = change_sign16_le; 760 } else { 761 if (mode == AUMODE_PLAY) 762 p->sw_code = 763 ulinear8_to_slinear16_le; 764 else 765 p->sw_code = 766 slinear16_to_ulinear8_le; 767 } 768 break; 769 770 case AUDIO_ENCODING_ULAW: 771 if (mode == AUMODE_PLAY) { 772 p->sw_code = mulaw_to_slinear16_le; 773 } else { 774 p->sw_code = slinear16_to_mulaw_le; 775 } 776 break; 777 778 case AUDIO_ENCODING_ALAW: 779 if (mode == AUMODE_PLAY) { 780 p->sw_code = alaw_to_slinear16_le; 781 } else { 782 p->sw_code = slinear16_to_alaw_le; 783 } 784 break; 785 786 default: 787 return (EINVAL); 788 } 789 790 if (IS_FIXED_RATE(sc->codec_if)) { 791 p->hw_sample_rate = AC97_SINGLE_RATE; 792 /* If hw_sample_rate is changed, aurateconv works. */ 793 } else { 794 if (auich_set_rate(sc, mode, p->sample_rate)) 795 return EINVAL; 796 } 797 } 798 799 return (0); 800 } 801 802 int 803 auich_round_blocksize(void *v, int blk) 804 { 805 806 return (blk & ~0x3f); /* keep good alignment */ 807 } 808 809 int 810 auich_halt_output(void *v) 811 { 812 struct auich_softc *sc = v; 813 814 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 815 816 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 817 818 return (0); 819 } 820 821 int 822 auich_halt_input(void *v) 823 { 824 struct auich_softc *sc = v; 825 826 DPRINTF(ICH_DEBUG_DMA, 827 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 828 829 /* XXX halt both unless known otherwise */ 830 831 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 832 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 833 834 return (0); 835 } 836 837 int 838 auich_getdev(void *v, struct audio_device *adp) 839 { 840 struct auich_softc *sc = v; 841 842 *adp = sc->sc_audev; 843 return (0); 844 } 845 846 int 847 auich_set_port(void *v, mixer_ctrl_t *cp) 848 { 849 struct auich_softc *sc = v; 850 851 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 852 } 853 854 int 855 auich_get_port(void *v, mixer_ctrl_t *cp) 856 { 857 struct auich_softc *sc = v; 858 859 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 860 } 861 862 int 863 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 864 { 865 struct auich_softc *sc = v; 866 867 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 868 } 869 870 void * 871 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 872 { 873 struct auich_softc *sc = v; 874 struct auich_dma *p; 875 int error; 876 877 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 878 return (NULL); 879 880 p = malloc(sizeof(*p), pool, flags|M_ZERO); 881 if (p == NULL) 882 return (NULL); 883 884 error = auich_allocmem(sc, size, 0, p); 885 if (error) { 886 free(p, pool); 887 return (NULL); 888 } 889 890 p->next = sc->sc_dmas; 891 sc->sc_dmas = p; 892 893 return (KERNADDR(p)); 894 } 895 896 void 897 auich_freem(void *v, void *ptr, int pool) 898 { 899 struct auich_softc *sc = v; 900 struct auich_dma *p, **pp; 901 902 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 903 if (KERNADDR(p) == ptr) { 904 auich_freemem(sc, p); 905 *pp = p->next; 906 free(p, pool); 907 return; 908 } 909 } 910 } 911 912 size_t 913 auich_round_buffersize(void *v, int direction, size_t size) 914 { 915 916 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 917 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 918 919 return size; 920 } 921 922 paddr_t 923 auich_mappage(void *v, void *mem, off_t off, int prot) 924 { 925 struct auich_softc *sc = v; 926 struct auich_dma *p; 927 928 if (off < 0) 929 return (-1); 930 931 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 932 ; 933 if (!p) 934 return (-1); 935 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 936 off, prot, BUS_DMA_WAITOK)); 937 } 938 939 int 940 auich_get_props(void *v) 941 { 942 struct auich_softc *sc = v; 943 int props; 944 945 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 946 /* 947 * Even if the codec is fixed-rate, set_param() succeeds for any sample 948 * rate because of aurateconv. Applications can't know what rate the 949 * device can process in the case of mmap(). 950 */ 951 if (!IS_FIXED_RATE(sc->codec_if)) 952 props |= AUDIO_PROP_MMAP; 953 return props; 954 } 955 956 int 957 auich_intr(void *v) 958 { 959 struct auich_softc *sc = v; 960 int ret = 0, sts, gsts, i, qptr; 961 962 #ifdef DIAGNOSTIC 963 int csts; 964 #endif 965 966 #ifdef DIAGNOSTIC 967 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 968 if (csts & PCI_STATUS_MASTER_ABORT) { 969 printf("auich_intr: PCI master abort\n"); 970 } 971 #endif 972 973 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 974 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 975 976 if (gsts & ICH_POINT) { 977 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 978 DPRINTF(ICH_DEBUG_DMA, 979 ("auich_intr: osts=0x%x\n", sts)); 980 981 if (sts & ICH_FIFOE) { 982 printf("%s: fifo underrun # %u\n", 983 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 984 } 985 986 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 987 if (sts & (ICH_LVBCI | ICH_CELV)) { 988 struct auich_dmalist *q; 989 990 qptr = sc->ptr_pcmo; 991 992 while (qptr != i) { 993 q = &sc->dmalist_pcmo[qptr]; 994 995 q->base = sc->pcmo_p; 996 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 997 DPRINTF(ICH_DEBUG_DMA, 998 ("auich_intr: %p, %p = %x @ 0x%x\n", 999 &sc->dmalist_pcmo[i], q, 1000 sc->pcmo_blksize / 2, sc->pcmo_p)); 1001 1002 sc->pcmo_p += sc->pcmo_blksize; 1003 if (sc->pcmo_p >= sc->pcmo_end) 1004 sc->pcmo_p = sc->pcmo_start; 1005 1006 if (++qptr == ICH_DMALIST_MAX) 1007 qptr = 0; 1008 } 1009 1010 sc->ptr_pcmo = qptr; 1011 bus_space_write_1(sc->iot, sc->aud_ioh, 1012 ICH_PCMO + ICH_LVI, 1013 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1014 } 1015 1016 if (sts & ICH_BCIS && sc->sc_pintr) 1017 sc->sc_pintr(sc->sc_parg); 1018 1019 /* int ack */ 1020 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1021 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1022 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1023 ret++; 1024 } 1025 1026 if (gsts & ICH_PIINT) { 1027 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1028 DPRINTF(ICH_DEBUG_DMA, 1029 ("auich_intr: ists=0x%x\n", sts)); 1030 1031 if (sts & ICH_FIFOE) { 1032 printf("%s: fifo overrun # %u\n", 1033 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1034 } 1035 1036 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1037 if (sts & (ICH_LVBCI | ICH_CELV)) { 1038 struct auich_dmalist *q; 1039 1040 qptr = sc->ptr_pcmi; 1041 1042 while (qptr != i) { 1043 q = &sc->dmalist_pcmi[qptr]; 1044 1045 q->base = sc->pcmi_p; 1046 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1047 DPRINTF(ICH_DEBUG_DMA, 1048 ("auich_intr: %p, %p = %x @ 0x%x\n", 1049 &sc->dmalist_pcmi[i], q, 1050 sc->pcmi_blksize / 2, sc->pcmi_p)); 1051 1052 sc->pcmi_p += sc->pcmi_blksize; 1053 if (sc->pcmi_p >= sc->pcmi_end) 1054 sc->pcmi_p = sc->pcmi_start; 1055 1056 if (++qptr == ICH_DMALIST_MAX) 1057 qptr = 0; 1058 } 1059 1060 sc->ptr_pcmi = qptr; 1061 bus_space_write_1(sc->iot, sc->aud_ioh, 1062 ICH_PCMI + ICH_LVI, 1063 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1064 } 1065 1066 if (sts & ICH_BCIS && sc->sc_rintr) 1067 sc->sc_rintr(sc->sc_rarg); 1068 1069 /* int ack */ 1070 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1071 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1072 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1073 ret++; 1074 } 1075 1076 if (gsts & ICH_MIINT) { 1077 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1078 DPRINTF(ICH_DEBUG_DMA, 1079 ("auich_intr: ists=0x%x\n", sts)); 1080 if (sts & ICH_FIFOE) 1081 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1082 1083 /* TODO mic input dma */ 1084 1085 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1086 } 1087 1088 return ret; 1089 } 1090 1091 int 1092 auich_trigger_output(void *v, void *start, void *end, int blksize, 1093 void (*intr)(void *), void *arg, struct audio_params *param) 1094 { 1095 struct auich_softc *sc = v; 1096 struct auich_dmalist *q; 1097 struct auich_dma *p; 1098 size_t size; 1099 #ifdef DIAGNOSTIC 1100 int csts; 1101 #endif 1102 1103 DPRINTF(ICH_DEBUG_DMA, 1104 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1105 start, end, blksize, intr, arg, param)); 1106 1107 sc->sc_pintr = intr; 1108 sc->sc_parg = arg; 1109 #ifdef DIAGNOSTIC 1110 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1111 if (csts & PCI_STATUS_MASTER_ABORT) { 1112 printf("auich_trigger_output: PCI master abort\n"); 1113 } 1114 #endif 1115 1116 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1117 ; 1118 if (!p) { 1119 printf("auich_trigger_output: bad addr %p\n", start); 1120 return (EINVAL); 1121 } 1122 1123 size = (size_t)((caddr_t)end - (caddr_t)start); 1124 1125 /* 1126 * The logic behind this is: 1127 * setup one buffer to play, then LVI dump out the rest 1128 * to the scatter-gather chain. 1129 */ 1130 sc->pcmo_start = DMAADDR(p); 1131 sc->pcmo_p = sc->pcmo_start + blksize; 1132 sc->pcmo_end = sc->pcmo_start + size; 1133 sc->pcmo_blksize = blksize; 1134 1135 sc->ptr_pcmo = 0; 1136 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1137 q->base = sc->pcmo_start; 1138 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1139 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1140 sc->ptr_pcmo = 0; 1141 1142 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1143 sc->sc_cddma + ICH_PCMO_OFF(0)); 1144 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1145 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1146 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1147 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1148 1149 return (0); 1150 } 1151 1152 int 1153 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1154 void *v; 1155 void *start, *end; 1156 int blksize; 1157 void (*intr)(void *); 1158 void *arg; 1159 struct audio_params *param; 1160 { 1161 struct auich_softc *sc = v; 1162 struct auich_dmalist *q; 1163 struct auich_dma *p; 1164 size_t size; 1165 #ifdef DIAGNOSTIC 1166 int csts; 1167 #endif 1168 1169 DPRINTF(ICH_DEBUG_DMA, 1170 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1171 start, end, blksize, intr, arg, param)); 1172 1173 sc->sc_rintr = intr; 1174 sc->sc_rarg = arg; 1175 1176 #ifdef DIAGNOSTIC 1177 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1178 if (csts & PCI_STATUS_MASTER_ABORT) { 1179 printf("auich_trigger_input: PCI master abort\n"); 1180 } 1181 #endif 1182 1183 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1184 ; 1185 if (!p) { 1186 printf("auich_trigger_input: bad addr %p\n", start); 1187 return (EINVAL); 1188 } 1189 1190 size = (size_t)((caddr_t)end - (caddr_t)start); 1191 1192 /* 1193 * The logic behind this is: 1194 * setup one buffer to play, then LVI dump out the rest 1195 * to the scatter-gather chain. 1196 */ 1197 sc->pcmi_start = DMAADDR(p); 1198 sc->pcmi_p = sc->pcmi_start + blksize; 1199 sc->pcmi_end = sc->pcmi_start + size; 1200 sc->pcmi_blksize = blksize; 1201 1202 sc->ptr_pcmi = 0; 1203 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1204 q->base = sc->pcmi_start; 1205 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1206 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1207 sc->ptr_pcmi = 0; 1208 1209 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1210 sc->sc_cddma + ICH_PCMI_OFF(0)); 1211 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1212 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1213 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1214 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1215 1216 return (0); 1217 } 1218 1219 int 1220 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1221 struct auich_dma *p) 1222 { 1223 int error; 1224 1225 p->size = size; 1226 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1227 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1228 &p->nsegs, BUS_DMA_NOWAIT); 1229 if (error) 1230 return (error); 1231 1232 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1233 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1234 if (error) 1235 goto free; 1236 1237 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1238 0, BUS_DMA_NOWAIT, &p->map); 1239 if (error) 1240 goto unmap; 1241 1242 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1243 BUS_DMA_NOWAIT); 1244 if (error) 1245 goto destroy; 1246 return (0); 1247 1248 destroy: 1249 bus_dmamap_destroy(sc->dmat, p->map); 1250 unmap: 1251 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1252 free: 1253 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1254 return (error); 1255 } 1256 1257 int 1258 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1259 { 1260 1261 bus_dmamap_unload(sc->dmat, p->map); 1262 bus_dmamap_destroy(sc->dmat, p->map); 1263 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1264 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1265 return (0); 1266 } 1267 1268 int 1269 auich_alloc_cdata(struct auich_softc *sc) 1270 { 1271 bus_dma_segment_t seg; 1272 int error, rseg; 1273 1274 /* 1275 * Allocate the control data structure, and create and load the 1276 * DMA map for it. 1277 */ 1278 if ((error = bus_dmamem_alloc(sc->dmat, 1279 sizeof(struct auich_cdata), 1280 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1281 printf("%s: unable to allocate control data, error = %d\n", 1282 sc->sc_dev.dv_xname, error); 1283 goto fail_0; 1284 } 1285 1286 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1287 sizeof(struct auich_cdata), 1288 (caddr_t *) &sc->sc_cdata, 1289 BUS_DMA_COHERENT)) != 0) { 1290 printf("%s: unable to map control data, error = %d\n", 1291 sc->sc_dev.dv_xname, error); 1292 goto fail_1; 1293 } 1294 1295 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1296 sizeof(struct auich_cdata), 0, 0, 1297 &sc->sc_cddmamap)) != 0) { 1298 printf("%s: unable to create control data DMA map, " 1299 "error = %d\n", sc->sc_dev.dv_xname, error); 1300 goto fail_2; 1301 } 1302 1303 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1304 sc->sc_cdata, sizeof(struct auich_cdata), 1305 NULL, 0)) != 0) { 1306 printf("%s: unable tp load control data DMA map, " 1307 "error = %d\n", sc->sc_dev.dv_xname, error); 1308 goto fail_3; 1309 } 1310 1311 return (0); 1312 1313 fail_3: 1314 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1315 fail_2: 1316 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1317 sizeof(struct auich_cdata)); 1318 fail_1: 1319 bus_dmamem_free(sc->dmat, &seg, rseg); 1320 fail_0: 1321 return (error); 1322 } 1323 1324 void 1325 auich_powerhook(int why, void *addr) 1326 { 1327 struct auich_softc *sc = (struct auich_softc *)addr; 1328 1329 switch (why) { 1330 case PWR_SUSPEND: 1331 case PWR_STANDBY: 1332 /* Power down */ 1333 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1334 sc->sc_suspend = why; 1335 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1336 break; 1337 1338 case PWR_RESUME: 1339 /* Wake up */ 1340 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1341 if (sc->sc_suspend == PWR_RESUME) { 1342 printf("%s: resume without suspend.\n", 1343 sc->sc_dev.dv_xname); 1344 sc->sc_suspend = why; 1345 return; 1346 } 1347 sc->sc_suspend = why; 1348 auich_reset_codec(sc); 1349 DELAY(1000); 1350 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1351 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1352 break; 1353 1354 case PWR_SOFTSUSPEND: 1355 case PWR_SOFTSTANDBY: 1356 case PWR_SOFTRESUME: 1357 break; 1358 } 1359 } 1360 1361 1362 /* -------------------------------------------------------------------- */ 1363 /* Calibrate card (some boards are overclocked and need scaling) */ 1364 1365 void 1366 auich_calibrate(struct device *self) 1367 { 1368 struct auich_softc *sc; 1369 struct timeval t1, t2; 1370 u_int8_t ociv, nciv; 1371 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1372 void *temp_buffer; 1373 struct auich_dma *p; 1374 1375 sc = (struct auich_softc*)self; 1376 /* 1377 * Grab audio from input for fixed interval and compare how 1378 * much we actually get with what we expect. Interval needs 1379 * to be sufficiently short that no interrupts are 1380 * generated. 1381 */ 1382 1383 /* Setup a buffer */ 1384 bytes = 16000; 1385 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1386 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1387 ; 1388 if (p == NULL) { 1389 printf("auich_calibrate: bad address %p\n", temp_buffer); 1390 return; 1391 } 1392 sc->dmalist_pcmi[0].base = DMAADDR(p); 1393 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size) | ICH_DMAF_IOC; 1394 1395 /* 1396 * our data format is stereo, 16 bit so each sample is 4 bytes. 1397 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1398 * we're going to start recording with interrupts disabled and measure 1399 * the time taken for one block to complete. we know the block size, 1400 * we know the time in microseconds, we calculate the sample rate: 1401 * 1402 * actual_rate [bps] = bytes / (time [s] * 4) 1403 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1404 * actual_rate [Hz] = (bytes * 250000) / time [us] 1405 */ 1406 1407 /* prepare */ 1408 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1409 nciv = ociv; 1410 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1411 sc->sc_cddma + ICH_PCMI_OFF(0)); 1412 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1413 (0 - 1) & ICH_LVI_MASK); 1414 1415 /* start */ 1416 microtime(&t1); 1417 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1418 1419 /* wait */ 1420 while (nciv == ociv) { 1421 microtime(&t2); 1422 if (t2.tv_sec - t1.tv_sec > 1) 1423 break; 1424 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1425 ICH_PCMI + ICH_CIV); 1426 } 1427 microtime(&t2); 1428 1429 /* stop */ 1430 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1431 1432 /* reset */ 1433 DELAY(100); 1434 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1435 1436 /* turn time delta into us */ 1437 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1438 1439 auich_freem(sc, temp_buffer, M_DEVBUF); 1440 1441 if (nciv == ociv) { 1442 printf("%s: ac97 link rate calibration timed out after %d us\n", 1443 sc->sc_dev.dv_xname, wait_us); 1444 return; 1445 } 1446 1447 actual_48k_rate = (bytes * 250000U) / wait_us; 1448 1449 if (actual_48k_rate <= 48500) 1450 ac97rate = 48000; 1451 else 1452 ac97rate = actual_48k_rate; 1453 1454 printf("%s: measured ac97 link rate at %d Hz", 1455 sc->sc_dev.dv_xname, actual_48k_rate); 1456 if (ac97rate != actual_48k_rate) 1457 printf(", will use %d Hz", ac97rate); 1458 printf("\n"); 1459 1460 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1461 } 1462
Indexes created Thu Oct 23 18:09:57 GMT 2025