auich.c revision 1.39
1 /* $NetBSD: auich.c,v 1.39 2003/06/13 07:27:17 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * 107 * TODO: 108 * - Add support for the dedicated microphone input. 109 * - 4ch/6ch support. 110 * 111 * NOTE: 112 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 113 * It causes PCI master abort and hangups until cold reboot. 114 * http://www.intel.com/design/chipsets/specupdt/245051.htm 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.39 2003/06/13 07:27:17 kent Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/kernel.h> 123 #include <sys/malloc.h> 124 #include <sys/device.h> 125 #include <sys/fcntl.h> 126 #include <sys/proc.h> 127 128 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 129 130 #include <dev/pci/pcidevs.h> 131 #include <dev/pci/pcivar.h> 132 #include <dev/pci/auichreg.h> 133 134 #include <sys/audioio.h> 135 #include <dev/audio_if.h> 136 #include <dev/mulaw.h> 137 #include <dev/auconv.h> 138 139 #include <machine/bus.h> 140 141 #include <dev/ic/ac97reg.h> 142 #include <dev/ic/ac97var.h> 143 144 struct auich_dma { 145 bus_dmamap_t map; 146 caddr_t addr; 147 bus_dma_segment_t segs[1]; 148 int nsegs; 149 size_t size; 150 struct auich_dma *next; 151 }; 152 153 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 154 #define KERNADDR(p) ((void *)((p)->addr)) 155 156 struct auich_cdata { 157 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 158 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 159 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 160 }; 161 162 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 163 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 164 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 165 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 166 167 struct auich_softc { 168 struct device sc_dev; 169 void *sc_ih; 170 171 audio_device_t sc_audev; 172 173 bus_space_tag_t iot; 174 bus_space_handle_t mix_ioh; 175 bus_space_handle_t aud_ioh; 176 bus_dma_tag_t dmat; 177 178 struct ac97_codec_if *codec_if; 179 struct ac97_host_if host_if; 180 181 /* DMA scatter-gather lists. */ 182 bus_dmamap_t sc_cddmamap; 183 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 184 185 struct auich_cdata *sc_cdata; 186 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 187 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 188 #define dmalist_mici sc_cdata->ic_dmalist_mici 189 190 int ptr_pcmo, 191 ptr_pcmi, 192 ptr_mici; 193 194 /* i/o buffer pointers */ 195 u_int32_t pcmo_start, pcmo_p, pcmo_end; 196 int pcmo_blksize, pcmo_fifoe; 197 198 u_int32_t pcmi_start, pcmi_p, pcmi_end; 199 int pcmi_blksize, pcmi_fifoe; 200 201 u_int32_t mici_start, mici_p, mici_end; 202 int mici_blksize, mici_fifoe; 203 204 struct auich_dma *sc_dmas; 205 206 #ifdef DIAGNOSTIC 207 pci_chipset_tag_t sc_pc; 208 pcitag_t sc_pt; 209 #endif 210 int sc_ignore_codecready; 211 /* SiS 7012 hack */ 212 int sc_sample_size; 213 int sc_sts_reg; 214 /* 440MX workaround */ 215 int sc_dmamap_flags; 216 217 void (*sc_pintr)(void *); 218 void *sc_parg; 219 220 void (*sc_rintr)(void *); 221 void *sc_rarg; 222 223 /* Power Management */ 224 void *sc_powerhook; 225 int sc_suspend; 226 u_int16_t ext_status; 227 }; 228 229 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 230 & AC97_EXT_AUDIO_VRA) 231 232 /* Debug */ 233 #ifdef AUDIO_DEBUG 234 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 235 int auich_debug = 0xfffe; 236 #define ICH_DEBUG_CODECIO 0x0001 237 #define ICH_DEBUG_DMA 0x0002 238 #define ICH_DEBUG_PARAM 0x0004 239 #else 240 #define DPRINTF(x,y) /* nothing */ 241 #endif 242 243 int auich_match(struct device *, struct cfdata *, void *); 244 void auich_attach(struct device *, struct device *, void *); 245 int auich_intr(void *); 246 247 CFATTACH_DECL(auich, sizeof(struct auich_softc), 248 auich_match, auich_attach, NULL, NULL); 249 250 int auich_open(void *, int); 251 void auich_close(void *); 252 int auich_query_encoding(void *, struct audio_encoding *); 253 int auich_set_params(void *, int, int, struct audio_params *, 254 struct audio_params *); 255 int auich_round_blocksize(void *, int); 256 int auich_halt_output(void *); 257 int auich_halt_input(void *); 258 int auich_getdev(void *, struct audio_device *); 259 int auich_set_port(void *, mixer_ctrl_t *); 260 int auich_get_port(void *, mixer_ctrl_t *); 261 int auich_query_devinfo(void *, mixer_devinfo_t *); 262 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 263 void auich_freem(void *, void *, struct malloc_type *); 264 size_t auich_round_buffersize(void *, int, size_t); 265 paddr_t auich_mappage(void *, void *, off_t, int); 266 int auich_get_props(void *); 267 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 268 void *, struct audio_params *); 269 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 270 void *, struct audio_params *); 271 272 int auich_alloc_cdata(struct auich_softc *); 273 274 int auich_allocmem(struct auich_softc *, size_t, size_t, 275 struct auich_dma *); 276 int auich_freemem(struct auich_softc *, struct auich_dma *); 277 278 void auich_powerhook(int, void *); 279 int auich_set_rate(struct auich_softc *, int, u_long); 280 void auich_calibrate(struct device *); 281 282 283 struct audio_hw_if auich_hw_if = { 284 auich_open, 285 auich_close, 286 NULL, /* drain */ 287 auich_query_encoding, 288 auich_set_params, 289 auich_round_blocksize, 290 NULL, /* commit_setting */ 291 NULL, /* init_output */ 292 NULL, /* init_input */ 293 NULL, /* start_output */ 294 NULL, /* start_input */ 295 auich_halt_output, 296 auich_halt_input, 297 NULL, /* speaker_ctl */ 298 auich_getdev, 299 NULL, /* getfd */ 300 auich_set_port, 301 auich_get_port, 302 auich_query_devinfo, 303 auich_allocm, 304 auich_freem, 305 auich_round_buffersize, 306 auich_mappage, 307 auich_get_props, 308 auich_trigger_output, 309 auich_trigger_input, 310 NULL, /* dev_ioctl */ 311 }; 312 313 int auich_attach_codec(void *, struct ac97_codec_if *); 314 int auich_read_codec(void *, u_int8_t, u_int16_t *); 315 int auich_write_codec(void *, u_int8_t, u_int16_t); 316 void auich_reset_codec(void *); 317 318 static const struct auich_devtype { 319 int vendor; 320 int product; 321 const char *name; 322 const char *shortname; 323 int quirks; 324 #define QUIRK_IGNORE_CODEC_READY 0x01 325 #define QUIRK_IGNORE_CODEC_READY_MAYBE 0x02 326 } auich_devices[] = { 327 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 328 "i82801AA (ICH) AC-97 Audio", "ICH" }, 329 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 330 "i82801AB (ICH0) AC-97 Audio", "ICH0", 331 QUIRK_IGNORE_CODEC_READY_MAYBE }, /* i810-L */ 332 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 333 "i82801BA (ICH2) AC-97 Audio", "ICH2", 334 QUIRK_IGNORE_CODEC_READY_MAYBE }, 335 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 336 "i82440MX AC-97 Audio", "440MX" }, 337 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 338 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, /* i830Mx i845MP/MZ*/ 339 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 340 "i82801DB (ICH4) AC-97 Audio", "ICH4", 341 QUIRK_IGNORE_CODEC_READY_MAYBE }, 342 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 343 "SiS 7012 AC-97 Audio", "SiS7012" }, 344 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 345 "nForce MCP AC-97 Audio", "nForce-MCP", 346 QUIRK_IGNORE_CODEC_READY }, 347 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 348 "nForce2 MCP-T AC-97 Audio", "nForce-MCP-T" }, 349 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 350 "AMD768 AC-97 Audio", "AMD768" }, 351 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 352 "AMD8111 AC-97 Audio", "AMD8111" }, 353 { 0, 354 NULL, NULL }, 355 }; 356 357 static const struct auich_devtype * 358 auich_lookup(struct pci_attach_args *pa) 359 { 360 const struct auich_devtype *d; 361 362 for (d = auich_devices; d->name != NULL; d++) { 363 if (PCI_VENDOR(pa->pa_id) == d->vendor 364 && PCI_PRODUCT(pa->pa_id) == d->product) 365 return (d); 366 } 367 368 return (NULL); 369 } 370 371 int 372 auich_match(struct device *parent, struct cfdata *match, void *aux) 373 { 374 struct pci_attach_args *pa = aux; 375 376 if (auich_lookup(pa) != NULL) 377 return (1); 378 379 return (0); 380 } 381 382 void 383 auich_attach(struct device *parent, struct device *self, void *aux) 384 { 385 struct auich_softc *sc = (struct auich_softc *)self; 386 struct pci_attach_args *pa = aux; 387 pci_intr_handle_t ih; 388 bus_size_t mix_size, aud_size; 389 pcireg_t csr; 390 const char *intrstr; 391 const struct auich_devtype *d; 392 u_int32_t status; 393 394 aprint_naive(": Audio controller\n"); 395 396 d = auich_lookup(pa); 397 if (d == NULL) 398 panic("auich_attach: impossible"); 399 400 #ifdef DIAGNOSTIC 401 sc->sc_pc = pa->pa_pc; 402 sc->sc_pt = pa->pa_tag; 403 #endif 404 405 aprint_normal(": %s\n", d->name); 406 407 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 408 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 409 aprint_error("%s: can't map codec i/o space\n", 410 sc->sc_dev.dv_xname); 411 return; 412 } 413 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 414 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 415 aprint_error("%s: can't map device i/o space\n", 416 sc->sc_dev.dv_xname); 417 return; 418 } 419 sc->dmat = pa->pa_dmat; 420 421 /* enable bus mastering */ 422 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 423 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 424 csr | PCI_COMMAND_MASTER_ENABLE); 425 426 /* Map and establish the interrupt. */ 427 if (pci_intr_map(pa, &ih)) { 428 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 429 return; 430 } 431 intrstr = pci_intr_string(pa->pa_pc, ih); 432 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 433 auich_intr, sc); 434 if (sc->sc_ih == NULL) { 435 aprint_error("%s: can't establish interrupt", 436 sc->sc_dev.dv_xname); 437 if (intrstr != NULL) 438 aprint_normal(" at %s", intrstr); 439 aprint_normal("\n"); 440 return; 441 } 442 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 443 444 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 445 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 446 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 447 448 /* SiS 7012 needs special handling */ 449 if (d->vendor == PCI_VENDOR_SIS 450 && d->product == PCI_PRODUCT_SIS_7012_AC) { 451 sc->sc_sts_reg = ICH_PICB; 452 sc->sc_sample_size = 1; 453 } else { 454 sc->sc_sts_reg = ICH_STS; 455 sc->sc_sample_size = 2; 456 } 457 458 if (d->quirks & QUIRK_IGNORE_CODEC_READY) { 459 sc->sc_ignore_codecready = TRUE; 460 } 461 462 /* Workaround for a 440MX B-stepping erratum */ 463 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 464 if (d->vendor == PCI_VENDOR_INTEL 465 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 466 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 467 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 468 } 469 470 /* Set up DMA lists. */ 471 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 472 auich_alloc_cdata(sc); 473 474 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 475 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 476 477 /* Reset codec and AC'97 */ 478 auich_reset_codec(sc); 479 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 480 if (!(status & ICH_PCR)) { /* reset failure */ 481 /* It never return ICH_PCR in some cases */ 482 if (d->quirks & QUIRK_IGNORE_CODEC_READY_MAYBE) { 483 sc->sc_ignore_codecready = TRUE; 484 } else { 485 return; 486 } 487 } 488 /* Print capabilities though there are no supports for now */ 489 if ((status & ICH_SAMPLE_CAP) == ICH_POM20) 490 aprint_normal("%s: 20 bit precision support\n", 491 sc->sc_dev.dv_xname); 492 if ((status & ICH_CHAN_CAP) == ICH_PCM4) 493 aprint_normal("%s: 4ch PCM output support\n", 494 sc->sc_dev.dv_xname); 495 if ((status & ICH_CHAN_CAP) == ICH_PCM6) 496 aprint_normal("%s: 6ch PCM output support\n", 497 sc->sc_dev.dv_xname); 498 499 sc->host_if.arg = sc; 500 sc->host_if.attach = auich_attach_codec; 501 sc->host_if.read = auich_read_codec; 502 sc->host_if.write = auich_write_codec; 503 sc->host_if.reset = auich_reset_codec; 504 505 if (ac97_attach(&sc->host_if) != 0) 506 return; 507 508 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 509 510 /* Watch for power change */ 511 sc->sc_suspend = PWR_RESUME; 512 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 513 514 if (!IS_FIXED_RATE(sc->codec_if)) { 515 config_interrupts(self, auich_calibrate); 516 } 517 } 518 519 #define ICH_CODECIO_INTERVAL 10 520 int 521 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 522 { 523 struct auich_softc *sc = v; 524 int i; 525 uint32_t status; 526 527 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 528 if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) { 529 printf("auich_read_codec: codec is not ready (0x%x)\n", status); 530 *val = 0xffff; 531 return -1; 532 } 533 /* wait for an access semaphore */ 534 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 535 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 536 DELAY(ICH_CODECIO_INTERVAL)); 537 538 if (i > 0) { 539 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 540 DPRINTF(ICH_DEBUG_CODECIO, 541 ("auich_read_codec(%x, %x)\n", reg, *val)); 542 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 543 if (status & ICH_RCS) { 544 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 545 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 546 *val = 0xffff; 547 } 548 return 0; 549 } else { 550 DPRINTF(ICH_DEBUG_CODECIO, 551 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 552 return -1; 553 } 554 } 555 556 int 557 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 558 { 559 struct auich_softc *sc = v; 560 int i; 561 562 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 563 if (!sc->sc_ignore_codecready 564 && !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) { 565 printf("auich_write_codec: codec is not ready."); 566 return -1; 567 } 568 /* wait for an access semaphore */ 569 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 570 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 571 DELAY(ICH_CODECIO_INTERVAL)); 572 573 if (i > 0) { 574 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 575 return 0; 576 } else { 577 DPRINTF(ICH_DEBUG_CODECIO, 578 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 579 return -1; 580 } 581 } 582 583 int 584 auich_attach_codec(void *v, struct ac97_codec_if *cif) 585 { 586 struct auich_softc *sc = v; 587 588 sc->codec_if = cif; 589 return 0; 590 } 591 592 void 593 auich_reset_codec(void *v) 594 { 595 struct auich_softc *sc = v; 596 int i; 597 uint32_t control; 598 599 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 600 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 601 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 602 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 603 604 for (i = 500000; i-- && 605 !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR); 606 DELAY(1)); /* or ICH_SCR? */ 607 if (i <= 0) 608 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 609 } 610 611 int 612 auich_open(void *v, int flags) 613 { 614 return 0; 615 } 616 617 void 618 auich_close(void *v) 619 { 620 struct auich_softc *sc = v; 621 622 auich_halt_output(sc); 623 auich_halt_input(sc); 624 625 sc->sc_pintr = NULL; 626 sc->sc_rintr = NULL; 627 } 628 629 int 630 auich_query_encoding(void *v, struct audio_encoding *aep) 631 { 632 633 switch (aep->index) { 634 case 0: 635 strcpy(aep->name, AudioEulinear); 636 aep->encoding = AUDIO_ENCODING_ULINEAR; 637 aep->precision = 8; 638 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 639 return (0); 640 case 1: 641 strcpy(aep->name, AudioEmulaw); 642 aep->encoding = AUDIO_ENCODING_ULAW; 643 aep->precision = 8; 644 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 645 return (0); 646 case 2: 647 strcpy(aep->name, AudioEalaw); 648 aep->encoding = AUDIO_ENCODING_ALAW; 649 aep->precision = 8; 650 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 651 return (0); 652 case 3: 653 strcpy(aep->name, AudioEslinear); 654 aep->encoding = AUDIO_ENCODING_SLINEAR; 655 aep->precision = 8; 656 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 657 return (0); 658 case 4: 659 strcpy(aep->name, AudioEslinear_le); 660 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 661 aep->precision = 16; 662 aep->flags = 0; 663 return (0); 664 case 5: 665 strcpy(aep->name, AudioEulinear_le); 666 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 667 aep->precision = 16; 668 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 669 return (0); 670 case 6: 671 strcpy(aep->name, AudioEslinear_be); 672 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 673 aep->precision = 16; 674 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 675 return (0); 676 case 7: 677 strcpy(aep->name, AudioEulinear_be); 678 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 679 aep->precision = 16; 680 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 681 return (0); 682 default: 683 return (EINVAL); 684 } 685 } 686 687 int 688 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 689 { 690 int reg; 691 u_long ratetmp; 692 693 ratetmp = srate; 694 reg = mode == AUMODE_PLAY 695 ? AC97_REG_PCM_FRONT_DAC_RATE : AC97_REG_PCM_LR_ADC_RATE; 696 return sc->codec_if->vtbl->set_rate(sc->codec_if, reg, &ratetmp); 697 } 698 699 int 700 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 701 struct audio_params *rec) 702 { 703 struct auich_softc *sc = v; 704 struct audio_params *p; 705 int mode; 706 707 for (mode = AUMODE_RECORD; mode != -1; 708 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 709 if ((setmode & mode) == 0) 710 continue; 711 712 p = mode == AUMODE_PLAY ? play : rec; 713 if (p == NULL) 714 continue; 715 716 if ((p->sample_rate != 8000) && 717 (p->sample_rate != 11025) && 718 (p->sample_rate != 16000) && 719 (p->sample_rate != 22050) && 720 (p->sample_rate != 32000) && 721 (p->sample_rate != 44100) && 722 (p->sample_rate != 48000)) 723 return (EINVAL); 724 725 p->factor = 1; 726 if (p->precision == 8) 727 p->factor *= 2; 728 729 p->sw_code = NULL; 730 /* setup hardware formats */ 731 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 732 p->hw_precision = 16; 733 734 /* If monaural is requested, aurateconv expands a monaural 735 * stream to stereo. */ 736 if (p->channels < 2) 737 p->hw_channels = 2; 738 739 switch (p->encoding) { 740 case AUDIO_ENCODING_SLINEAR_BE: 741 if (p->precision == 16) { 742 p->sw_code = swap_bytes; 743 } else { 744 if (mode == AUMODE_PLAY) 745 p->sw_code = linear8_to_linear16_le; 746 else 747 p->sw_code = linear16_to_linear8_le; 748 } 749 break; 750 751 case AUDIO_ENCODING_SLINEAR_LE: 752 if (p->precision != 16) { 753 if (mode == AUMODE_PLAY) 754 p->sw_code = linear8_to_linear16_le; 755 else 756 p->sw_code = linear16_to_linear8_le; 757 } 758 break; 759 760 case AUDIO_ENCODING_ULINEAR_BE: 761 if (p->precision == 16) { 762 if (mode == AUMODE_PLAY) 763 p->sw_code = 764 swap_bytes_change_sign16_le; 765 else 766 p->sw_code = 767 change_sign16_swap_bytes_le; 768 } else { 769 if (mode == AUMODE_PLAY) 770 p->sw_code = 771 ulinear8_to_slinear16_le; 772 else 773 p->sw_code = 774 slinear16_to_ulinear8_le; 775 } 776 break; 777 778 case AUDIO_ENCODING_ULINEAR_LE: 779 if (p->precision == 16) { 780 p->sw_code = change_sign16_le; 781 } else { 782 if (mode == AUMODE_PLAY) 783 p->sw_code = 784 ulinear8_to_slinear16_le; 785 else 786 p->sw_code = 787 slinear16_to_ulinear8_le; 788 } 789 break; 790 791 case AUDIO_ENCODING_ULAW: 792 if (mode == AUMODE_PLAY) { 793 p->sw_code = mulaw_to_slinear16_le; 794 } else { 795 p->sw_code = slinear16_to_mulaw_le; 796 } 797 break; 798 799 case AUDIO_ENCODING_ALAW: 800 if (mode == AUMODE_PLAY) { 801 p->sw_code = alaw_to_slinear16_le; 802 } else { 803 p->sw_code = slinear16_to_alaw_le; 804 } 805 break; 806 807 default: 808 return (EINVAL); 809 } 810 811 if (IS_FIXED_RATE(sc->codec_if)) { 812 p->hw_sample_rate = AC97_SINGLE_RATE; 813 /* If hw_sample_rate is changed, aurateconv works. */ 814 } else { 815 if (auich_set_rate(sc, mode, p->sample_rate)) 816 return EINVAL; 817 } 818 } 819 820 return (0); 821 } 822 823 int 824 auich_round_blocksize(void *v, int blk) 825 { 826 827 return (blk & ~0x3f); /* keep good alignment */ 828 } 829 830 int 831 auich_halt_output(void *v) 832 { 833 struct auich_softc *sc = v; 834 835 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 836 837 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 838 839 return (0); 840 } 841 842 int 843 auich_halt_input(void *v) 844 { 845 struct auich_softc *sc = v; 846 847 DPRINTF(ICH_DEBUG_DMA, 848 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 849 850 /* XXX halt both unless known otherwise */ 851 852 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 853 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 854 855 return (0); 856 } 857 858 int 859 auich_getdev(void *v, struct audio_device *adp) 860 { 861 struct auich_softc *sc = v; 862 863 *adp = sc->sc_audev; 864 return (0); 865 } 866 867 int 868 auich_set_port(void *v, mixer_ctrl_t *cp) 869 { 870 struct auich_softc *sc = v; 871 872 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 873 } 874 875 int 876 auich_get_port(void *v, mixer_ctrl_t *cp) 877 { 878 struct auich_softc *sc = v; 879 880 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 881 } 882 883 int 884 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 885 { 886 struct auich_softc *sc = v; 887 888 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 889 } 890 891 void * 892 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 893 int flags) 894 { 895 struct auich_softc *sc = v; 896 struct auich_dma *p; 897 int error; 898 899 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 900 return (NULL); 901 902 p = malloc(sizeof(*p), pool, flags|M_ZERO); 903 if (p == NULL) 904 return (NULL); 905 906 error = auich_allocmem(sc, size, 0, p); 907 if (error) { 908 free(p, pool); 909 return (NULL); 910 } 911 912 p->next = sc->sc_dmas; 913 sc->sc_dmas = p; 914 915 return (KERNADDR(p)); 916 } 917 918 void 919 auich_freem(void *v, void *ptr, struct malloc_type *pool) 920 { 921 struct auich_softc *sc = v; 922 struct auich_dma *p, **pp; 923 924 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 925 if (KERNADDR(p) == ptr) { 926 auich_freemem(sc, p); 927 *pp = p->next; 928 free(p, pool); 929 return; 930 } 931 } 932 } 933 934 size_t 935 auich_round_buffersize(void *v, int direction, size_t size) 936 { 937 938 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 939 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 940 941 return size; 942 } 943 944 paddr_t 945 auich_mappage(void *v, void *mem, off_t off, int prot) 946 { 947 struct auich_softc *sc = v; 948 struct auich_dma *p; 949 950 if (off < 0) 951 return (-1); 952 953 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 954 ; 955 if (!p) 956 return (-1); 957 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 958 off, prot, BUS_DMA_WAITOK)); 959 } 960 961 int 962 auich_get_props(void *v) 963 { 964 struct auich_softc *sc = v; 965 int props; 966 967 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 968 /* 969 * Even if the codec is fixed-rate, set_param() succeeds for any sample 970 * rate because of aurateconv. Applications can't know what rate the 971 * device can process in the case of mmap(). 972 */ 973 if (!IS_FIXED_RATE(sc->codec_if)) 974 props |= AUDIO_PROP_MMAP; 975 return props; 976 } 977 978 int 979 auich_intr(void *v) 980 { 981 struct auich_softc *sc = v; 982 int ret = 0, sts, gsts, i, qptr; 983 984 #ifdef DIAGNOSTIC 985 int csts; 986 #endif 987 988 #ifdef DIAGNOSTIC 989 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 990 if (csts & PCI_STATUS_MASTER_ABORT) { 991 printf("auich_intr: PCI master abort\n"); 992 } 993 #endif 994 995 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 996 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 997 998 if (gsts & ICH_POINT) { 999 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 1000 DPRINTF(ICH_DEBUG_DMA, 1001 ("auich_intr: osts=0x%x\n", sts)); 1002 1003 if (sts & ICH_FIFOE) { 1004 printf("%s: fifo underrun # %u\n", 1005 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1006 } 1007 1008 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1009 if (sts & (ICH_LVBCI | ICH_CELV)) { 1010 struct auich_dmalist *q; 1011 1012 qptr = sc->ptr_pcmo; 1013 1014 while (qptr != i) { 1015 q = &sc->dmalist_pcmo[qptr]; 1016 1017 q->base = sc->pcmo_p; 1018 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1019 DPRINTF(ICH_DEBUG_DMA, 1020 ("auich_intr: %p, %p = %x @ 0x%x\n", 1021 &sc->dmalist_pcmo[i], q, 1022 sc->pcmo_blksize / 2, sc->pcmo_p)); 1023 1024 sc->pcmo_p += sc->pcmo_blksize; 1025 if (sc->pcmo_p >= sc->pcmo_end) 1026 sc->pcmo_p = sc->pcmo_start; 1027 1028 if (++qptr == ICH_DMALIST_MAX) 1029 qptr = 0; 1030 } 1031 1032 sc->ptr_pcmo = qptr; 1033 bus_space_write_1(sc->iot, sc->aud_ioh, 1034 ICH_PCMO + ICH_LVI, 1035 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1036 } 1037 1038 if (sts & ICH_BCIS && sc->sc_pintr) 1039 sc->sc_pintr(sc->sc_parg); 1040 1041 /* int ack */ 1042 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1043 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1044 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1045 ret++; 1046 } 1047 1048 if (gsts & ICH_PIINT) { 1049 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1050 DPRINTF(ICH_DEBUG_DMA, 1051 ("auich_intr: ists=0x%x\n", sts)); 1052 1053 if (sts & ICH_FIFOE) { 1054 printf("%s: fifo overrun # %u\n", 1055 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1056 } 1057 1058 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1059 if (sts & (ICH_LVBCI | ICH_CELV)) { 1060 struct auich_dmalist *q; 1061 1062 qptr = sc->ptr_pcmi; 1063 1064 while (qptr != i) { 1065 q = &sc->dmalist_pcmi[qptr]; 1066 1067 q->base = sc->pcmi_p; 1068 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1069 DPRINTF(ICH_DEBUG_DMA, 1070 ("auich_intr: %p, %p = %x @ 0x%x\n", 1071 &sc->dmalist_pcmi[i], q, 1072 sc->pcmi_blksize / 2, sc->pcmi_p)); 1073 1074 sc->pcmi_p += sc->pcmi_blksize; 1075 if (sc->pcmi_p >= sc->pcmi_end) 1076 sc->pcmi_p = sc->pcmi_start; 1077 1078 if (++qptr == ICH_DMALIST_MAX) 1079 qptr = 0; 1080 } 1081 1082 sc->ptr_pcmi = qptr; 1083 bus_space_write_1(sc->iot, sc->aud_ioh, 1084 ICH_PCMI + ICH_LVI, 1085 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1086 } 1087 1088 if (sts & ICH_BCIS && sc->sc_rintr) 1089 sc->sc_rintr(sc->sc_rarg); 1090 1091 /* int ack */ 1092 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1093 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1094 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1095 ret++; 1096 } 1097 1098 if (gsts & ICH_MIINT) { 1099 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1100 DPRINTF(ICH_DEBUG_DMA, 1101 ("auich_intr: ists=0x%x\n", sts)); 1102 if (sts & ICH_FIFOE) 1103 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1104 1105 /* TODO mic input DMA */ 1106 1107 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1108 } 1109 1110 return ret; 1111 } 1112 1113 int 1114 auich_trigger_output(void *v, void *start, void *end, int blksize, 1115 void (*intr)(void *), void *arg, struct audio_params *param) 1116 { 1117 struct auich_softc *sc = v; 1118 struct auich_dmalist *q; 1119 struct auich_dma *p; 1120 size_t size; 1121 #ifdef DIAGNOSTIC 1122 int csts; 1123 #endif 1124 1125 DPRINTF(ICH_DEBUG_DMA, 1126 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1127 start, end, blksize, intr, arg, param)); 1128 1129 sc->sc_pintr = intr; 1130 sc->sc_parg = arg; 1131 #ifdef DIAGNOSTIC 1132 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1133 if (csts & PCI_STATUS_MASTER_ABORT) { 1134 printf("auich_trigger_output: PCI master abort\n"); 1135 } 1136 #endif 1137 1138 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1139 ; 1140 if (!p) { 1141 printf("auich_trigger_output: bad addr %p\n", start); 1142 return (EINVAL); 1143 } 1144 1145 size = (size_t)((caddr_t)end - (caddr_t)start); 1146 1147 /* 1148 * The logic behind this is: 1149 * setup one buffer to play, then LVI dump out the rest 1150 * to the scatter-gather chain. 1151 */ 1152 sc->pcmo_start = DMAADDR(p); 1153 sc->pcmo_p = sc->pcmo_start + blksize; 1154 sc->pcmo_end = sc->pcmo_start + size; 1155 sc->pcmo_blksize = blksize; 1156 1157 sc->ptr_pcmo = 0; 1158 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1159 q->base = sc->pcmo_start; 1160 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1161 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1162 sc->ptr_pcmo = 0; 1163 1164 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1165 sc->sc_cddma + ICH_PCMO_OFF(0)); 1166 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1167 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1168 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1169 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1170 1171 return (0); 1172 } 1173 1174 int 1175 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1176 void *v; 1177 void *start, *end; 1178 int blksize; 1179 void (*intr)(void *); 1180 void *arg; 1181 struct audio_params *param; 1182 { 1183 struct auich_softc *sc = v; 1184 struct auich_dmalist *q; 1185 struct auich_dma *p; 1186 size_t size; 1187 #ifdef DIAGNOSTIC 1188 int csts; 1189 #endif 1190 1191 DPRINTF(ICH_DEBUG_DMA, 1192 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1193 start, end, blksize, intr, arg, param)); 1194 1195 sc->sc_rintr = intr; 1196 sc->sc_rarg = arg; 1197 1198 #ifdef DIAGNOSTIC 1199 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1200 if (csts & PCI_STATUS_MASTER_ABORT) { 1201 printf("auich_trigger_input: PCI master abort\n"); 1202 } 1203 #endif 1204 1205 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1206 ; 1207 if (!p) { 1208 printf("auich_trigger_input: bad addr %p\n", start); 1209 return (EINVAL); 1210 } 1211 1212 size = (size_t)((caddr_t)end - (caddr_t)start); 1213 1214 /* 1215 * The logic behind this is: 1216 * setup one buffer to play, then LVI dump out the rest 1217 * to the scatter-gather chain. 1218 */ 1219 sc->pcmi_start = DMAADDR(p); 1220 sc->pcmi_p = sc->pcmi_start + blksize; 1221 sc->pcmi_end = sc->pcmi_start + size; 1222 sc->pcmi_blksize = blksize; 1223 1224 sc->ptr_pcmi = 0; 1225 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1226 q->base = sc->pcmi_start; 1227 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1228 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1229 sc->ptr_pcmi = 0; 1230 1231 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1232 sc->sc_cddma + ICH_PCMI_OFF(0)); 1233 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1234 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1235 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1236 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1237 1238 return (0); 1239 } 1240 1241 int 1242 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1243 struct auich_dma *p) 1244 { 1245 int error; 1246 1247 p->size = size; 1248 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1249 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1250 &p->nsegs, BUS_DMA_NOWAIT); 1251 if (error) 1252 return (error); 1253 1254 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1255 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1256 if (error) 1257 goto free; 1258 1259 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1260 0, BUS_DMA_NOWAIT, &p->map); 1261 if (error) 1262 goto unmap; 1263 1264 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1265 BUS_DMA_NOWAIT); 1266 if (error) 1267 goto destroy; 1268 return (0); 1269 1270 destroy: 1271 bus_dmamap_destroy(sc->dmat, p->map); 1272 unmap: 1273 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1274 free: 1275 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1276 return (error); 1277 } 1278 1279 int 1280 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1281 { 1282 1283 bus_dmamap_unload(sc->dmat, p->map); 1284 bus_dmamap_destroy(sc->dmat, p->map); 1285 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1286 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1287 return (0); 1288 } 1289 1290 int 1291 auich_alloc_cdata(struct auich_softc *sc) 1292 { 1293 bus_dma_segment_t seg; 1294 int error, rseg; 1295 1296 /* 1297 * Allocate the control data structure, and create and load the 1298 * DMA map for it. 1299 */ 1300 if ((error = bus_dmamem_alloc(sc->dmat, 1301 sizeof(struct auich_cdata), 1302 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1303 printf("%s: unable to allocate control data, error = %d\n", 1304 sc->sc_dev.dv_xname, error); 1305 goto fail_0; 1306 } 1307 1308 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1309 sizeof(struct auich_cdata), 1310 (caddr_t *) &sc->sc_cdata, 1311 sc->sc_dmamap_flags)) != 0) { 1312 printf("%s: unable to map control data, error = %d\n", 1313 sc->sc_dev.dv_xname, error); 1314 goto fail_1; 1315 } 1316 1317 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1318 sizeof(struct auich_cdata), 0, 0, 1319 &sc->sc_cddmamap)) != 0) { 1320 printf("%s: unable to create control data DMA map, " 1321 "error = %d\n", sc->sc_dev.dv_xname, error); 1322 goto fail_2; 1323 } 1324 1325 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1326 sc->sc_cdata, sizeof(struct auich_cdata), 1327 NULL, 0)) != 0) { 1328 printf("%s: unable tp load control data DMA map, " 1329 "error = %d\n", sc->sc_dev.dv_xname, error); 1330 goto fail_3; 1331 } 1332 1333 return (0); 1334 1335 fail_3: 1336 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1337 fail_2: 1338 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1339 sizeof(struct auich_cdata)); 1340 fail_1: 1341 bus_dmamem_free(sc->dmat, &seg, rseg); 1342 fail_0: 1343 return (error); 1344 } 1345 1346 void 1347 auich_powerhook(int why, void *addr) 1348 { 1349 struct auich_softc *sc = (struct auich_softc *)addr; 1350 1351 switch (why) { 1352 case PWR_SUSPEND: 1353 case PWR_STANDBY: 1354 /* Power down */ 1355 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1356 sc->sc_suspend = why; 1357 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1358 break; 1359 1360 case PWR_RESUME: 1361 /* Wake up */ 1362 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1363 if (sc->sc_suspend == PWR_RESUME) { 1364 printf("%s: resume without suspend.\n", 1365 sc->sc_dev.dv_xname); 1366 sc->sc_suspend = why; 1367 return; 1368 } 1369 sc->sc_suspend = why; 1370 auich_reset_codec(sc); 1371 DELAY(1000); 1372 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1373 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1374 break; 1375 1376 case PWR_SOFTSUSPEND: 1377 case PWR_SOFTSTANDBY: 1378 case PWR_SOFTRESUME: 1379 break; 1380 } 1381 } 1382 1383 1384 /* -------------------------------------------------------------------- */ 1385 /* Calibrate card (some boards are overclocked and need scaling) */ 1386 1387 void 1388 auich_calibrate(struct device *self) 1389 { 1390 struct auich_softc *sc; 1391 struct timeval t1, t2; 1392 u_int8_t ociv, nciv; 1393 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1394 void *temp_buffer; 1395 struct auich_dma *p; 1396 1397 sc = (struct auich_softc*)self; 1398 /* 1399 * Grab audio from input for fixed interval and compare how 1400 * much we actually get with what we expect. Interval needs 1401 * to be sufficiently short that no interrupts are 1402 * generated. 1403 */ 1404 1405 /* Setup a buffer */ 1406 bytes = 16000; 1407 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1408 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1409 ; 1410 if (p == NULL) { 1411 printf("auich_calibrate: bad address %p\n", temp_buffer); 1412 return; 1413 } 1414 sc->dmalist_pcmi[0].base = DMAADDR(p); 1415 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size) | ICH_DMAF_IOC; 1416 1417 /* 1418 * our data format is stereo, 16 bit so each sample is 4 bytes. 1419 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1420 * we're going to start recording with interrupts disabled and measure 1421 * the time taken for one block to complete. we know the block size, 1422 * we know the time in microseconds, we calculate the sample rate: 1423 * 1424 * actual_rate [bps] = bytes / (time [s] * 4) 1425 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1426 * actual_rate [Hz] = (bytes * 250000) / time [us] 1427 */ 1428 1429 /* prepare */ 1430 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1431 nciv = ociv; 1432 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1433 sc->sc_cddma + ICH_PCMI_OFF(0)); 1434 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1435 (0 - 1) & ICH_LVI_MASK); 1436 1437 /* start */ 1438 microtime(&t1); 1439 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1440 1441 /* wait */ 1442 while (nciv == ociv) { 1443 microtime(&t2); 1444 if (t2.tv_sec - t1.tv_sec > 1) 1445 break; 1446 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1447 ICH_PCMI + ICH_CIV); 1448 } 1449 microtime(&t2); 1450 1451 /* stop */ 1452 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1453 1454 /* reset */ 1455 DELAY(100); 1456 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1457 1458 /* turn time delta into us */ 1459 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1460 1461 auich_freem(sc, temp_buffer, M_DEVBUF); 1462 1463 if (nciv == ociv) { 1464 printf("%s: ac97 link rate calibration timed out after %d us\n", 1465 sc->sc_dev.dv_xname, wait_us); 1466 return; 1467 } 1468 1469 actual_48k_rate = (bytes * 250000U) / wait_us; 1470 1471 if (actual_48k_rate <= 48500) 1472 ac97rate = 48000; 1473 else 1474 ac97rate = actual_48k_rate; 1475 1476 printf("%s: measured ac97 link rate at %d Hz", 1477 sc->sc_dev.dv_xname, actual_48k_rate); 1478 if (ac97rate != actual_48k_rate) 1479 printf(", will use %d Hz", ac97rate); 1480 printf("\n"); 1481 1482 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1483 } 1484
Indexes created Fri Oct 31 11:10:07 GMT 2025