auich.c revision 1.39.2.16
1 /* $NetBSD: auich.c,v 1.39.2.16 2005/12/11 10:28:57 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.39.2.16 2005/12/11 10:28:57 christos Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 187 struct ac97_codec_if *codec_if; 188 struct ac97_host_if host_if; 189 int sc_codecnum; 190 int sc_codectype; 191 192 /* DMA scatter-gather lists. */ 193 bus_dmamap_t sc_cddmamap; 194 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 195 196 struct auich_cdata *sc_cdata; 197 198 struct auich_ring { 199 int qptr; 200 struct auich_dmalist *dmalist; 201 202 uint32_t start, p, end; 203 int blksize; 204 205 void (*intr)(void *); 206 void *arg; 207 } pcmo, pcmi, mici; 208 209 struct auich_dma *sc_dmas; 210 211 /* SiS 7012 hack */ 212 int sc_sample_shift; 213 int sc_sts_reg; 214 /* 440MX workaround */ 215 int sc_dmamap_flags; 216 217 /* Power Management */ 218 void *sc_powerhook; 219 int sc_suspend; 220 struct pci_conf_state sc_pciconf; 221 222 /* sysctl */ 223 struct sysctllog *sc_log; 224 uint32_t sc_ac97_clock; 225 int sc_ac97_clock_mib; 226 227 int sc_modem_offset; 228 229 #define AUICH_AUDIO_NFORMATS 3 230 #define AUICH_MODEM_NFORMATS 1 231 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 232 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 233 struct audio_encoding_set *sc_encodings; 234 }; 235 236 /* Debug */ 237 #ifdef AUICH_DEBUG 238 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 239 int auich_debug = 0xfffe; 240 #define ICH_DEBUG_CODECIO 0x0001 241 #define ICH_DEBUG_DMA 0x0002 242 #define ICH_DEBUG_INTR 0x0004 243 #else 244 #define DPRINTF(x,y) /* nothing */ 245 #endif 246 247 static int auich_match(struct device *, struct cfdata *, void *); 248 static void auich_attach(struct device *, struct device *, void *); 249 static int auich_detach(struct device *, int); 250 static int auich_activate(struct device *, enum devact); 251 static int auich_intr(void *); 252 253 CFATTACH_DECL(auich, sizeof(struct auich_softc), 254 auich_match, auich_attach, auich_detach, auich_activate); 255 256 static int auich_query_encoding(void *, struct audio_encoding *); 257 static int auich_set_params(void *, int, int, audio_params_t *, 258 audio_params_t *, stream_filter_list_t *, 259 stream_filter_list_t *); 260 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 261 static void auich_halt_pipe(struct auich_softc *, int); 262 static int auich_halt_output(void *); 263 static int auich_halt_input(void *); 264 static int auich_getdev(void *, struct audio_device *); 265 static int auich_set_port(void *, mixer_ctrl_t *); 266 static int auich_get_port(void *, mixer_ctrl_t *); 267 static int auich_query_devinfo(void *, mixer_devinfo_t *); 268 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 269 static void auich_freem(void *, void *, struct malloc_type *); 270 static size_t auich_round_buffersize(void *, int, size_t); 271 static paddr_t auich_mappage(void *, void *, off_t, int); 272 static int auich_get_props(void *); 273 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 274 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 275 static int auich_trigger_output(void *, void *, void *, int, 276 void (*)(void *), void *, const audio_params_t *); 277 static int auich_trigger_input(void *, void *, void *, int, 278 void (*)(void *), void *, const audio_params_t *); 279 280 static int auich_alloc_cdata(struct auich_softc *); 281 282 static int auich_allocmem(struct auich_softc *, size_t, size_t, 283 struct auich_dma *); 284 static int auich_freemem(struct auich_softc *, struct auich_dma *); 285 286 static void auich_powerhook(int, void *); 287 static int auich_set_rate(struct auich_softc *, int, u_long); 288 static int auich_sysctl_verify(SYSCTLFN_ARGS); 289 static void auich_finish_attach(struct device *); 290 static void auich_calibrate(struct auich_softc *); 291 static void auich_clear_cas(struct auich_softc *); 292 293 static int auich_attach_codec(void *, struct ac97_codec_if *); 294 static int auich_read_codec(void *, uint8_t, uint16_t *); 295 static int auich_write_codec(void *, uint8_t, uint16_t); 296 static int auich_reset_codec(void *); 297 298 static const struct audio_hw_if auich_hw_if = { 299 NULL, /* open */ 300 NULL, /* close */ 301 NULL, /* drain */ 302 auich_query_encoding, 303 auich_set_params, 304 auich_round_blocksize, 305 NULL, /* commit_setting */ 306 NULL, /* init_output */ 307 NULL, /* init_input */ 308 NULL, /* start_output */ 309 NULL, /* start_input */ 310 auich_halt_output, 311 auich_halt_input, 312 NULL, /* speaker_ctl */ 313 auich_getdev, 314 NULL, /* getfd */ 315 auich_set_port, 316 auich_get_port, 317 auich_query_devinfo, 318 auich_allocm, 319 auich_freem, 320 auich_round_buffersize, 321 auich_mappage, 322 auich_get_props, 323 auich_trigger_output, 324 auich_trigger_input, 325 NULL, /* dev_ioctl */ 326 }; 327 328 #define AUICH_FORMATS_1CH 0 329 #define AUICH_FORMATS_4CH 1 330 #define AUICH_FORMATS_6CH 2 331 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 332 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 333 2, AUFMT_STEREO, 0, {8000, 48000}}, 334 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 335 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 336 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 337 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 338 }; 339 340 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 341 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 342 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 343 }; 344 345 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 346 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 347 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 348 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 349 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 350 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 351 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 352 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 353 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 354 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 355 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 356 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 357 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 358 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 359 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 360 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 361 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 362 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 363 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 364 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 365 366 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 367 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 368 369 struct auich_devtype { 370 pcireg_t id; 371 const char *name; 372 const char *shortname; /* must be less than 11 characters */ 373 }; 374 375 static const struct auich_devtype auich_audio_devices[] = { 376 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 377 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 378 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 379 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 380 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 381 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 382 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 383 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 384 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 385 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 386 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 387 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 388 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 389 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 390 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 391 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 392 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 393 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 394 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 395 { 0, NULL, NULL }, 396 }; 397 398 static const struct auich_devtype auich_modem_devices[] = { 399 #ifdef AUICH_ATTACH_MODEM 400 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 401 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 402 #endif 403 { 0, NULL, NULL }, 404 }; 405 406 static const struct auich_devtype * 407 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 408 { 409 const struct auich_devtype *d; 410 411 for (d = auich_devices; d->name != NULL; d++) { 412 if (pa->pa_id == d->id) 413 return d; 414 } 415 416 return NULL; 417 } 418 419 static int 420 auich_match(struct device *parent, struct cfdata *match, void *aux) 421 { 422 struct pci_attach_args *pa; 423 424 pa = aux; 425 if (auich_lookup(pa, auich_audio_devices) != NULL) 426 return 1; 427 if (auich_lookup(pa, auich_modem_devices) != NULL) 428 return 1; 429 430 return 0; 431 } 432 433 static void 434 auich_attach(struct device *parent, struct device *self, void *aux) 435 { 436 struct auich_softc *sc; 437 struct pci_attach_args *pa; 438 pci_intr_handle_t ih; 439 pcireg_t v; 440 const char *intrstr; 441 const struct auich_devtype *d; 442 const struct sysctlnode *node, *node_ac97clock; 443 int err, node_mib, i; 444 445 sc = (struct auich_softc *)self; 446 pa = aux; 447 448 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 449 sc->sc_modem_offset = 0x10; 450 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 451 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 452 sc->sc_modem_offset = 0; 453 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 454 } else 455 panic("auich_attach: impossible"); 456 457 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 458 aprint_naive(": Audio controller\n"); 459 else 460 aprint_naive(": Modem controller\n"); 461 462 sc->sc_pc = pa->pa_pc; 463 sc->sc_pt = pa->pa_tag; 464 465 aprint_normal(": %s\n", d->name); 466 467 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 468 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 469 || d->id == PCIID_ICH4MODEM) { 470 /* 471 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 472 */ 473 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 474 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 475 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 476 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 477 v | ICH_CFG_IOSE); 478 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 479 0, &sc->iot, &sc->mix_ioh, NULL, 480 &sc->mix_size)) { 481 aprint_error("%s: can't map codec i/o space\n", 482 sc->sc_dev.dv_xname); 483 return; 484 } 485 } 486 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 487 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 488 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 489 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 490 v | ICH_CFG_IOSE); 491 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 492 0, &sc->iot, &sc->aud_ioh, NULL, 493 &sc->aud_size)) { 494 aprint_error("%s: can't map device i/o space\n", 495 sc->sc_dev.dv_xname); 496 return; 497 } 498 } 499 } else { 500 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 501 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 502 aprint_error("%s: can't map codec i/o space\n", 503 sc->sc_dev.dv_xname); 504 return; 505 } 506 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 507 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 508 aprint_error("%s: can't map device i/o space\n", 509 sc->sc_dev.dv_xname); 510 return; 511 } 512 } 513 sc->dmat = pa->pa_dmat; 514 515 /* enable bus mastering */ 516 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 517 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 518 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 519 520 /* Map and establish the interrupt. */ 521 if (pci_intr_map(pa, &ih)) { 522 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 523 return; 524 } 525 intrstr = pci_intr_string(pa->pa_pc, ih); 526 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 527 auich_intr, sc); 528 if (sc->sc_ih == NULL) { 529 aprint_error("%s: can't establish interrupt", 530 sc->sc_dev.dv_xname); 531 if (intrstr != NULL) 532 aprint_normal(" at %s", intrstr); 533 aprint_normal("\n"); 534 return; 535 } 536 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 537 538 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 539 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 540 "0x%02x", PCI_REVISION(pa->pa_class)); 541 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 542 543 /* SiS 7012 needs special handling */ 544 if (d->id == PCIID_SIS7012) { 545 sc->sc_sts_reg = ICH_PICB; 546 sc->sc_sample_shift = 0; 547 /* Un-mute output. From Linux. */ 548 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 549 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 550 ICH_SIS_CTL_UNMUTE); 551 } else { 552 sc->sc_sts_reg = ICH_STS; 553 sc->sc_sample_shift = 1; 554 } 555 556 /* Workaround for a 440MX B-stepping erratum */ 557 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 558 if (d->id == PCIID_440MX) { 559 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 560 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 561 } 562 563 /* Set up DMA lists. */ 564 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 565 auich_alloc_cdata(sc); 566 567 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 568 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 569 570 /* Modem codecs are always the secondary codec on ICH */ 571 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 572 573 sc->host_if.arg = sc; 574 sc->host_if.attach = auich_attach_codec; 575 sc->host_if.read = auich_read_codec; 576 sc->host_if.write = auich_write_codec; 577 sc->host_if.reset = auich_reset_codec; 578 579 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 580 return; 581 582 /* setup audio_format */ 583 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 584 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 585 if (!AC97_IS_4CH(sc->codec_if)) 586 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 587 if (!AC97_IS_6CH(sc->codec_if)) 588 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 589 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 590 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 591 sc->sc_audio_formats[i].frequency_type = 1; 592 sc->sc_audio_formats[i].frequency[0] = 48000; 593 } 594 } 595 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 596 &sc->sc_encodings)) 597 return; 598 } else { 599 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 600 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 601 &sc->sc_encodings)) 602 return; 603 } 604 605 606 /* Watch for power change */ 607 sc->sc_suspend = PWR_RESUME; 608 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 609 610 config_interrupts(self, auich_finish_attach); 611 612 /* sysctl setup */ 613 if (AC97_IS_FIXED_RATE(sc->codec_if) && 614 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 615 return; 616 617 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 618 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 619 CTL_HW, CTL_EOL); 620 if (err != 0) 621 goto sysctl_err; 622 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 623 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 624 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 625 if (err != 0) 626 goto sysctl_err; 627 node_mib = node->sysctl_num; 628 629 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 630 /* passing the sc address instead of &sc->sc_ac97_clock */ 631 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 632 CTLFLAG_READWRITE, 633 CTLTYPE_INT, "ac97rate", 634 SYSCTL_DESCR("AC'97 codec link rate"), 635 auich_sysctl_verify, 0, sc, 0, 636 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 637 if (err != 0) 638 goto sysctl_err; 639 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 640 } 641 642 return; 643 644 sysctl_err: 645 printf("%s: failed to add sysctl nodes. (%d)\n", 646 sc->sc_dev.dv_xname, err); 647 return; /* failure of sysctl is not fatal. */ 648 } 649 650 static int 651 auich_activate(struct device *self, enum devact act) 652 { 653 struct auich_softc *sc; 654 int ret; 655 656 sc = (struct auich_softc *)self; 657 ret = 0; 658 switch (act) { 659 case DVACT_ACTIVATE: 660 return EOPNOTSUPP; 661 case DVACT_DEACTIVATE: 662 if (sc->sc_audiodev != NULL) 663 ret = config_deactivate(sc->sc_audiodev); 664 return ret; 665 } 666 return EOPNOTSUPP; 667 } 668 669 static int 670 auich_detach(struct device *self, int flags) 671 { 672 struct auich_softc *sc; 673 674 sc = (struct auich_softc *)self; 675 676 /* audio */ 677 if (sc->sc_audiodev != NULL) 678 config_detach(sc->sc_audiodev, flags); 679 680 /* sysctl */ 681 sysctl_teardown(&sc->sc_log); 682 683 /* audio_encoding_set */ 684 auconv_delete_encodings(sc->sc_encodings); 685 686 /* ac97 */ 687 if (sc->codec_if != NULL) 688 sc->codec_if->vtbl->detach(sc->codec_if); 689 690 /* PCI */ 691 if (sc->sc_ih != NULL) 692 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 693 if (sc->mix_size != 0) 694 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 695 if (sc->aud_size != 0) 696 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 697 return 0; 698 } 699 700 static int 701 auich_sysctl_verify(SYSCTLFN_ARGS) 702 { 703 int error, tmp; 704 struct sysctlnode node; 705 struct auich_softc *sc; 706 707 node = *rnode; 708 sc = rnode->sysctl_data; 709 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 710 tmp = sc->sc_ac97_clock; 711 node.sysctl_data = &tmp; 712 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 713 if (error || newp == NULL) 714 return error; 715 716 if (tmp < 48000 || tmp > 96000) 717 return EINVAL; 718 sc->sc_ac97_clock = tmp; 719 } 720 721 return 0; 722 } 723 724 static void 725 auich_finish_attach(struct device *self) 726 { 727 struct auich_softc *sc; 728 729 sc = (void *)self; 730 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 731 auich_calibrate(sc); 732 733 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 734 } 735 736 #define ICH_CODECIO_INTERVAL 10 737 static int 738 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 739 { 740 struct auich_softc *sc; 741 int i; 742 uint32_t status; 743 744 sc = v; 745 /* wait for an access semaphore */ 746 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 747 bus_space_read_1(sc->iot, sc->aud_ioh, 748 ICH_CAS + sc->sc_modem_offset) & 1; 749 DELAY(ICH_CODECIO_INTERVAL)); 750 751 if (i > 0) { 752 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 753 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 754 DPRINTF(ICH_DEBUG_CODECIO, 755 ("auich_read_codec(%x, %x)\n", reg, *val)); 756 status = bus_space_read_4(sc->iot, sc->aud_ioh, 757 ICH_GSTS + sc->sc_modem_offset); 758 if (status & ICH_RCS) { 759 bus_space_write_4(sc->iot, sc->aud_ioh, 760 ICH_GSTS + sc->sc_modem_offset, 761 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 762 *val = 0xffff; 763 DPRINTF(ICH_DEBUG_CODECIO, 764 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 765 if (reg == AC97_REG_GPIO_STATUS) 766 auich_clear_cas(sc); 767 return -1; 768 } 769 if (reg == AC97_REG_GPIO_STATUS) 770 auich_clear_cas(sc); 771 return 0; 772 } else { 773 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 774 if (reg == AC97_REG_GPIO_STATUS) 775 auich_clear_cas(sc); 776 return -1; 777 } 778 } 779 780 static int 781 auich_write_codec(void *v, uint8_t reg, uint16_t val) 782 { 783 struct auich_softc *sc; 784 int i; 785 786 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 787 sc = v; 788 /* wait for an access semaphore */ 789 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 790 bus_space_read_1(sc->iot, sc->aud_ioh, 791 ICH_CAS + sc->sc_modem_offset) & 1; 792 DELAY(ICH_CODECIO_INTERVAL)); 793 794 if (i > 0) { 795 bus_space_write_2(sc->iot, sc->mix_ioh, 796 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 797 return 0; 798 } else { 799 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 800 return -1; 801 } 802 } 803 804 static int 805 auich_attach_codec(void *v, struct ac97_codec_if *cif) 806 { 807 struct auich_softc *sc; 808 809 sc = v; 810 sc->codec_if = cif; 811 812 return 0; 813 } 814 815 static int 816 auich_reset_codec(void *v) 817 { 818 struct auich_softc *sc; 819 int i; 820 uint32_t control, status; 821 822 sc = v; 823 control = bus_space_read_4(sc->iot, sc->aud_ioh, 824 ICH_GCTRL + sc->sc_modem_offset); 825 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 826 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 827 } else { 828 control &= ~ICH_ACLSO; 829 control |= ICH_GIE; 830 } 831 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 832 bus_space_write_4(sc->iot, sc->aud_ioh, 833 ICH_GCTRL + sc->sc_modem_offset, control); 834 835 for (i = 500000; i >= 0; i--) { 836 status = bus_space_read_4(sc->iot, sc->aud_ioh, 837 ICH_GSTS + sc->sc_modem_offset); 838 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 839 break; 840 DELAY(1); 841 } 842 if (i <= 0) { 843 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 844 return ETIMEDOUT; 845 } 846 #ifdef DEBUG 847 if (status & ICH_SCR) 848 printf("%s: The 2nd codec is ready.\n", 849 sc->sc_dev.dv_xname); 850 if (status & ICH_S2CR) 851 printf("%s: The 3rd codec is ready.\n", 852 sc->sc_dev.dv_xname); 853 #endif 854 return 0; 855 } 856 857 static int 858 auich_query_encoding(void *v, struct audio_encoding *aep) 859 { 860 struct auich_softc *sc; 861 862 sc = (struct auich_softc *)v; 863 return auconv_query_encoding(sc->sc_encodings, aep); 864 } 865 866 static int 867 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 868 { 869 int ret; 870 u_int ratetmp; 871 872 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 873 ratetmp = srate; 874 if (mode == AUMODE_RECORD) 875 return sc->codec_if->vtbl->set_rate(sc->codec_if, 876 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 877 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 878 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 879 if (ret) 880 return ret; 881 ratetmp = srate; 882 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 883 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 884 if (ret) 885 return ret; 886 ratetmp = srate; 887 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 888 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 889 return ret; 890 } 891 892 static int 893 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 894 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 895 { 896 struct auich_softc *sc; 897 audio_params_t *p; 898 stream_filter_list_t *fil; 899 int mode, index; 900 uint32_t control; 901 902 sc = v; 903 for (mode = AUMODE_RECORD; mode != -1; 904 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 905 if ((setmode & mode) == 0) 906 continue; 907 908 p = mode == AUMODE_PLAY ? play : rec; 909 fil = mode == AUMODE_PLAY ? pfil : rfil; 910 if (p == NULL) 911 continue; 912 913 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 914 if (p->sample_rate < 8000 || 915 p->sample_rate > 48000) 916 return EINVAL; 917 918 index = auconv_set_converter(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 919 mode, p, TRUE, fil); 920 } else { 921 if (p->sample_rate != 8000 && p->sample_rate != 16000) 922 return EINVAL; 923 index = auconv_set_converter(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 924 mode, p, TRUE, fil); 925 } 926 if (index < 0) 927 return EINVAL; 928 if (fil->req_size > 0) 929 p = &fil->filters[0].param; 930 /* p represents HW encoding */ 931 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 932 if (sc->sc_audio_formats[index].frequency_type != 1 933 && auich_set_rate(sc, mode, p->sample_rate)) 934 return EINVAL; 935 } else { 936 if (sc->sc_modem_formats[index].frequency_type != 1 937 && auich_set_rate(sc, mode, p->sample_rate)) 938 return EINVAL; 939 auich_write_codec(sc, AC97_REG_LINE1_RATE, 940 p->sample_rate); 941 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 942 } 943 if (mode == AUMODE_PLAY && 944 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 945 control = bus_space_read_4(sc->iot, sc->aud_ioh, 946 ICH_GCTRL + sc->sc_modem_offset); 947 control &= ~ICH_PCM246_MASK; 948 if (p->channels == 4) { 949 control |= ICH_PCM4; 950 } else if (p->channels == 6) { 951 control |= ICH_PCM6; 952 } 953 bus_space_write_4(sc->iot, sc->aud_ioh, 954 ICH_GCTRL + sc->sc_modem_offset, control); 955 } 956 } 957 958 return 0; 959 } 960 961 static int 962 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 963 { 964 965 return blk & ~0x3f; /* keep good alignment */ 966 } 967 968 static void 969 auich_halt_pipe(struct auich_softc *sc, int pipe) 970 { 971 int i; 972 uint32_t status; 973 974 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 975 for (i = 0; i < 100; i++) { 976 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 977 if (status & ICH_DCH) 978 break; 979 DELAY(1); 980 } 981 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 982 983 #if AUICH_DEBUG 984 if (i > 0) 985 printf("auich_halt_pipe: halt took %d cycles\n", i); 986 #endif 987 } 988 989 static int 990 auich_halt_output(void *v) 991 { 992 struct auich_softc *sc; 993 994 sc = v; 995 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 996 997 auich_halt_pipe(sc, ICH_PCMO); 998 sc->pcmo.intr = NULL; 999 1000 return 0; 1001 } 1002 1003 static int 1004 auich_halt_input(void *v) 1005 { 1006 struct auich_softc *sc; 1007 1008 sc = v; 1009 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1010 1011 auich_halt_pipe(sc, ICH_PCMI); 1012 sc->pcmi.intr = NULL; 1013 1014 return 0; 1015 } 1016 1017 static int 1018 auich_getdev(void *v, struct audio_device *adp) 1019 { 1020 struct auich_softc *sc; 1021 1022 sc = v; 1023 *adp = sc->sc_audev; 1024 return 0; 1025 } 1026 1027 static int 1028 auich_set_port(void *v, mixer_ctrl_t *cp) 1029 { 1030 struct auich_softc *sc; 1031 1032 sc = v; 1033 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1034 } 1035 1036 static int 1037 auich_get_port(void *v, mixer_ctrl_t *cp) 1038 { 1039 struct auich_softc *sc; 1040 1041 sc = v; 1042 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1043 } 1044 1045 static int 1046 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1047 { 1048 struct auich_softc *sc; 1049 1050 sc = v; 1051 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1052 } 1053 1054 static void * 1055 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 1056 int flags) 1057 { 1058 struct auich_softc *sc; 1059 struct auich_dma *p; 1060 int error; 1061 1062 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1063 return NULL; 1064 1065 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1066 if (p == NULL) 1067 return NULL; 1068 1069 sc = v; 1070 error = auich_allocmem(sc, size, 0, p); 1071 if (error) { 1072 free(p, pool); 1073 return NULL; 1074 } 1075 1076 p->next = sc->sc_dmas; 1077 sc->sc_dmas = p; 1078 1079 return KERNADDR(p); 1080 } 1081 1082 static void 1083 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1084 { 1085 struct auich_softc *sc; 1086 struct auich_dma *p, **pp; 1087 1088 sc = v; 1089 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1090 if (KERNADDR(p) == ptr) { 1091 auich_freemem(sc, p); 1092 *pp = p->next; 1093 free(p, pool); 1094 return; 1095 } 1096 } 1097 } 1098 1099 static size_t 1100 auich_round_buffersize(void *v, int direction, size_t size) 1101 { 1102 1103 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1104 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1105 1106 return size; 1107 } 1108 1109 static paddr_t 1110 auich_mappage(void *v, void *mem, off_t off, int prot) 1111 { 1112 struct auich_softc *sc; 1113 struct auich_dma *p; 1114 1115 if (off < 0) 1116 return -1; 1117 sc = v; 1118 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1119 continue; 1120 if (!p) 1121 return -1; 1122 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1123 off, prot, BUS_DMA_WAITOK); 1124 } 1125 1126 static int 1127 auich_get_props(void *v) 1128 { 1129 struct auich_softc *sc; 1130 int props; 1131 1132 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1133 sc = v; 1134 /* 1135 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1136 * rate because of aurateconv. Applications can't know what rate the 1137 * device can process in the case of mmap(). 1138 */ 1139 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1140 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1141 props |= AUDIO_PROP_MMAP; 1142 return props; 1143 } 1144 1145 static int 1146 auich_intr(void *v) 1147 { 1148 struct auich_softc *sc; 1149 int ret, gsts; 1150 #ifdef DIAGNOSTIC 1151 int csts; 1152 #endif 1153 1154 sc = v; 1155 ret = 0; 1156 #ifdef DIAGNOSTIC 1157 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1158 if (csts & PCI_STATUS_MASTER_ABORT) { 1159 printf("auich_intr: PCI master abort\n"); 1160 } 1161 #endif 1162 1163 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1164 ICH_GSTS + sc->sc_modem_offset); 1165 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1166 1167 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1168 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1169 int sts; 1170 1171 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1172 ICH_PCMO + sc->sc_sts_reg); 1173 DPRINTF(ICH_DEBUG_INTR, 1174 ("auich_intr: osts=0x%x\n", sts)); 1175 1176 if (sts & ICH_FIFOE) 1177 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1178 1179 if (sts & ICH_BCIS) 1180 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1181 1182 /* int ack */ 1183 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1184 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1185 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1186 bus_space_write_4(sc->iot, sc->aud_ioh, 1187 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1188 else 1189 bus_space_write_4(sc->iot, sc->aud_ioh, 1190 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1191 ret++; 1192 } 1193 1194 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1195 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1196 int sts; 1197 1198 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1199 ICH_PCMI + sc->sc_sts_reg); 1200 DPRINTF(ICH_DEBUG_INTR, 1201 ("auich_intr: ists=0x%x\n", sts)); 1202 1203 if (sts & ICH_FIFOE) 1204 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1205 1206 if (sts & ICH_BCIS) 1207 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1208 1209 /* int ack */ 1210 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1211 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1212 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1213 bus_space_write_4(sc->iot, sc->aud_ioh, 1214 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1215 else 1216 bus_space_write_4(sc->iot, sc->aud_ioh, 1217 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1218 ret++; 1219 } 1220 1221 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1222 int sts; 1223 1224 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1225 ICH_MICI + sc->sc_sts_reg); 1226 DPRINTF(ICH_DEBUG_INTR, 1227 ("auich_intr: ists=0x%x\n", sts)); 1228 1229 if (sts & ICH_FIFOE) 1230 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1231 1232 if (sts & ICH_BCIS) 1233 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1234 1235 /* int ack */ 1236 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1237 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1238 bus_space_write_4(sc->iot, sc->aud_ioh, 1239 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1240 ret++; 1241 } 1242 1243 #ifdef AUICH_MODEM_DEBUG 1244 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1245 printf("%s: gsts=0x%x\n", sc->sc_dev.dv_xname, gsts); 1246 /* int ack */ 1247 bus_space_write_4(sc->iot, sc->aud_ioh, 1248 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1249 ret++; 1250 } 1251 #endif 1252 1253 return ret; 1254 } 1255 1256 static void 1257 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1258 { 1259 int blksize, qptr; 1260 struct auich_dmalist *q; 1261 1262 blksize = ring->blksize; 1263 1264 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1265 q = &ring->dmalist[qptr]; 1266 q->base = ring->p; 1267 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1268 1269 ring->p += blksize; 1270 if (ring->p >= ring->end) 1271 ring->p = ring->start; 1272 } 1273 ring->qptr = 0; 1274 1275 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1276 (qptr - 1) & ICH_LVI_MASK); 1277 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1278 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1279 } 1280 1281 static void 1282 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1283 { 1284 int blksize, qptr, nqptr; 1285 struct auich_dmalist *q; 1286 1287 blksize = ring->blksize; 1288 qptr = ring->qptr; 1289 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1290 1291 while (qptr != nqptr) { 1292 q = &ring->dmalist[qptr]; 1293 q->base = ring->p; 1294 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1295 1296 DPRINTF(ICH_DEBUG_INTR, 1297 ("auich_intr: %p, %p = %x @ 0x%x\n", 1298 &ring->dmalist[qptr], q, q->len, q->base)); 1299 1300 ring->p += blksize; 1301 if (ring->p >= ring->end) 1302 ring->p = ring->start; 1303 1304 qptr = (qptr + 1) & ICH_LVI_MASK; 1305 if (ring->intr) 1306 ring->intr(ring->arg); 1307 } 1308 ring->qptr = qptr; 1309 1310 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1311 (qptr - 1) & ICH_LVI_MASK); 1312 } 1313 1314 static int 1315 auich_trigger_output(void *v, void *start, void *end, int blksize, 1316 void (*intr)(void *), void *arg, const audio_params_t *param) 1317 { 1318 struct auich_softc *sc; 1319 struct auich_dma *p; 1320 size_t size; 1321 1322 DPRINTF(ICH_DEBUG_DMA, 1323 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1324 start, end, blksize, intr, arg, param)); 1325 sc = v; 1326 1327 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1328 continue; 1329 if (!p) { 1330 printf("auich_trigger_output: bad addr %p\n", start); 1331 return EINVAL; 1332 } 1333 1334 size = (size_t)((caddr_t)end - (caddr_t)start); 1335 1336 sc->pcmo.intr = intr; 1337 sc->pcmo.arg = arg; 1338 sc->pcmo.start = DMAADDR(p); 1339 sc->pcmo.p = sc->pcmo.start; 1340 sc->pcmo.end = sc->pcmo.start + size; 1341 sc->pcmo.blksize = blksize; 1342 1343 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1344 sc->sc_cddma + ICH_PCMO_OFF(0)); 1345 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1346 1347 return 0; 1348 } 1349 1350 static int 1351 auich_trigger_input(void *v, void *start, void *end, int blksize, 1352 void (*intr)(void *), void *arg, const audio_params_t *param) 1353 { 1354 struct auich_softc *sc; 1355 struct auich_dma *p; 1356 size_t size; 1357 1358 DPRINTF(ICH_DEBUG_DMA, 1359 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1360 start, end, blksize, intr, arg, param)); 1361 sc = v; 1362 1363 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1364 continue; 1365 if (!p) { 1366 printf("auich_trigger_input: bad addr %p\n", start); 1367 return EINVAL; 1368 } 1369 1370 size = (size_t)((caddr_t)end - (caddr_t)start); 1371 1372 sc->pcmi.intr = intr; 1373 sc->pcmi.arg = arg; 1374 sc->pcmi.start = DMAADDR(p); 1375 sc->pcmi.p = sc->pcmi.start; 1376 sc->pcmi.end = sc->pcmi.start + size; 1377 sc->pcmi.blksize = blksize; 1378 1379 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1380 sc->sc_cddma + ICH_PCMI_OFF(0)); 1381 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1382 1383 return 0; 1384 } 1385 1386 static int 1387 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1388 struct auich_dma *p) 1389 { 1390 int error; 1391 1392 p->size = size; 1393 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1394 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1395 &p->nsegs, BUS_DMA_NOWAIT); 1396 if (error) 1397 return error; 1398 1399 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1400 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1401 if (error) 1402 goto free; 1403 1404 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1405 0, BUS_DMA_NOWAIT, &p->map); 1406 if (error) 1407 goto unmap; 1408 1409 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1410 BUS_DMA_NOWAIT); 1411 if (error) 1412 goto destroy; 1413 return 0; 1414 1415 destroy: 1416 bus_dmamap_destroy(sc->dmat, p->map); 1417 unmap: 1418 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1419 free: 1420 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1421 return error; 1422 } 1423 1424 static int 1425 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1426 { 1427 1428 bus_dmamap_unload(sc->dmat, p->map); 1429 bus_dmamap_destroy(sc->dmat, p->map); 1430 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1431 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1432 return 0; 1433 } 1434 1435 static int 1436 auich_alloc_cdata(struct auich_softc *sc) 1437 { 1438 bus_dma_segment_t seg; 1439 int error, rseg; 1440 1441 /* 1442 * Allocate the control data structure, and create and load the 1443 * DMA map for it. 1444 */ 1445 if ((error = bus_dmamem_alloc(sc->dmat, 1446 sizeof(struct auich_cdata), 1447 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1448 printf("%s: unable to allocate control data, error = %d\n", 1449 sc->sc_dev.dv_xname, error); 1450 goto fail_0; 1451 } 1452 1453 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1454 sizeof(struct auich_cdata), 1455 (caddr_t *) &sc->sc_cdata, 1456 sc->sc_dmamap_flags)) != 0) { 1457 printf("%s: unable to map control data, error = %d\n", 1458 sc->sc_dev.dv_xname, error); 1459 goto fail_1; 1460 } 1461 1462 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1463 sizeof(struct auich_cdata), 0, 0, 1464 &sc->sc_cddmamap)) != 0) { 1465 printf("%s: unable to create control data DMA map, " 1466 "error = %d\n", sc->sc_dev.dv_xname, error); 1467 goto fail_2; 1468 } 1469 1470 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1471 sc->sc_cdata, sizeof(struct auich_cdata), 1472 NULL, 0)) != 0) { 1473 printf("%s: unable tp load control data DMA map, " 1474 "error = %d\n", sc->sc_dev.dv_xname, error); 1475 goto fail_3; 1476 } 1477 1478 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1479 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1480 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1481 1482 return 0; 1483 1484 fail_3: 1485 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1486 fail_2: 1487 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1488 sizeof(struct auich_cdata)); 1489 fail_1: 1490 bus_dmamem_free(sc->dmat, &seg, rseg); 1491 fail_0: 1492 return error; 1493 } 1494 1495 static void 1496 auich_powerhook(int why, void *addr) 1497 { 1498 struct auich_softc *sc; 1499 1500 sc = (struct auich_softc *)addr; 1501 switch (why) { 1502 case PWR_SUSPEND: 1503 case PWR_STANDBY: 1504 /* Power down */ 1505 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1506 sc->sc_suspend = why; 1507 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1508 break; 1509 1510 case PWR_RESUME: 1511 /* Wake up */ 1512 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1513 if (sc->sc_suspend == PWR_RESUME) { 1514 printf("%s: resume without suspend.\n", 1515 sc->sc_dev.dv_xname); 1516 sc->sc_suspend = why; 1517 return; 1518 } 1519 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1520 sc->sc_suspend = why; 1521 auich_reset_codec(sc); 1522 DELAY(1000); 1523 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1524 break; 1525 1526 case PWR_SOFTSUSPEND: 1527 case PWR_SOFTSTANDBY: 1528 case PWR_SOFTRESUME: 1529 break; 1530 } 1531 } 1532 1533 /* 1534 * Calibrate card (some boards are overclocked and need scaling) 1535 */ 1536 static void 1537 auich_calibrate(struct auich_softc *sc) 1538 { 1539 struct timeval t1, t2; 1540 uint8_t ociv, nciv; 1541 uint64_t wait_us; 1542 uint32_t actual_48k_rate, bytes, ac97rate; 1543 void *temp_buffer; 1544 struct auich_dma *p; 1545 u_int rate; 1546 1547 /* 1548 * Grab audio from input for fixed interval and compare how 1549 * much we actually get with what we expect. Interval needs 1550 * to be sufficiently short that no interrupts are 1551 * generated. 1552 */ 1553 1554 /* Force the codec to a known state first. */ 1555 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1556 rate = sc->sc_ac97_clock = 48000; 1557 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1558 &rate); 1559 1560 /* Setup a buffer */ 1561 bytes = 64000; 1562 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1563 1564 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1565 continue; 1566 if (p == NULL) { 1567 printf("auich_calibrate: bad address %p\n", temp_buffer); 1568 return; 1569 } 1570 sc->pcmi.dmalist[0].base = DMAADDR(p); 1571 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1572 1573 /* 1574 * our data format is stereo, 16 bit so each sample is 4 bytes. 1575 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1576 * we're going to start recording with interrupts disabled and measure 1577 * the time taken for one block to complete. we know the block size, 1578 * we know the time in microseconds, we calculate the sample rate: 1579 * 1580 * actual_rate [bps] = bytes / (time [s] * 4) 1581 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1582 * actual_rate [Hz] = (bytes * 250000) / time [us] 1583 */ 1584 1585 /* prepare */ 1586 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1587 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1588 sc->sc_cddma + ICH_PCMI_OFF(0)); 1589 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1590 (0 - 1) & ICH_LVI_MASK); 1591 1592 /* start */ 1593 microtime(&t1); 1594 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1595 1596 /* wait */ 1597 nciv = ociv; 1598 do { 1599 microtime(&t2); 1600 if (t2.tv_sec - t1.tv_sec > 1) 1601 break; 1602 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1603 ICH_PCMI + ICH_CIV); 1604 } while (nciv == ociv); 1605 microtime(&t2); 1606 1607 /* stop */ 1608 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1609 1610 /* reset */ 1611 DELAY(100); 1612 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1613 1614 /* turn time delta into us */ 1615 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1616 1617 auich_freem(sc, temp_buffer, M_DEVBUF); 1618 1619 if (nciv == ociv) { 1620 printf("%s: ac97 link rate calibration timed out after %" 1621 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1622 return; 1623 } 1624 1625 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1626 1627 if (actual_48k_rate < 50000) 1628 ac97rate = 48000; 1629 else 1630 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1631 1632 printf("%s: measured ac97 link rate at %d Hz", 1633 sc->sc_dev.dv_xname, actual_48k_rate); 1634 if (ac97rate != actual_48k_rate) 1635 printf(", will use %d Hz", ac97rate); 1636 printf("\n"); 1637 1638 sc->sc_ac97_clock = ac97rate; 1639 } 1640 1641 static void 1642 auich_clear_cas(struct auich_softc *sc) 1643 { 1644 /* Clear the codec access semaphore */ 1645 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1646 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1647 1648 return; 1649 } 1650
Indexes created Wed Oct 22 13:09:56 GMT 2025