auich.c revision 1.40
1 /* $NetBSD: auich.c,v 1.40 2003/08/19 21:04:22 erh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * 107 * TODO: 108 * - Add support for the dedicated microphone input. 109 * - 4ch/6ch support. 110 * 111 * NOTE: 112 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 113 * It causes PCI master abort and hangups until cold reboot. 114 * http://www.intel.com/design/chipsets/specupdt/245051.htm 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.40 2003/08/19 21:04:22 erh Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/kernel.h> 123 #include <sys/malloc.h> 124 #include <sys/device.h> 125 #include <sys/fcntl.h> 126 #include <sys/proc.h> 127 128 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 129 130 #include <dev/pci/pcidevs.h> 131 #include <dev/pci/pcivar.h> 132 #include <dev/pci/auichreg.h> 133 134 #include <sys/audioio.h> 135 #include <dev/audio_if.h> 136 #include <dev/mulaw.h> 137 #include <dev/auconv.h> 138 139 #include <machine/bus.h> 140 141 #include <dev/ic/ac97reg.h> 142 #include <dev/ic/ac97var.h> 143 144 struct auich_dma { 145 bus_dmamap_t map; 146 caddr_t addr; 147 bus_dma_segment_t segs[1]; 148 int nsegs; 149 size_t size; 150 struct auich_dma *next; 151 }; 152 153 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 154 #define KERNADDR(p) ((void *)((p)->addr)) 155 156 struct auich_cdata { 157 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 158 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 159 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 160 }; 161 162 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 163 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 164 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 165 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 166 167 struct auich_softc { 168 struct device sc_dev; 169 void *sc_ih; 170 171 audio_device_t sc_audev; 172 173 bus_space_tag_t iot; 174 bus_space_handle_t mix_ioh; 175 bus_space_handle_t aud_ioh; 176 bus_dma_tag_t dmat; 177 178 struct ac97_codec_if *codec_if; 179 struct ac97_host_if host_if; 180 181 /* DMA scatter-gather lists. */ 182 bus_dmamap_t sc_cddmamap; 183 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 184 185 struct auich_cdata *sc_cdata; 186 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 187 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 188 #define dmalist_mici sc_cdata->ic_dmalist_mici 189 190 int ptr_pcmo, 191 ptr_pcmi, 192 ptr_mici; 193 194 /* i/o buffer pointers */ 195 u_int32_t pcmo_start, pcmo_p, pcmo_end; 196 int pcmo_blksize, pcmo_fifoe; 197 198 u_int32_t pcmi_start, pcmi_p, pcmi_end; 199 int pcmi_blksize, pcmi_fifoe; 200 201 u_int32_t mici_start, mici_p, mici_end; 202 int mici_blksize, mici_fifoe; 203 204 struct auich_dma *sc_dmas; 205 206 #ifdef DIAGNOSTIC 207 pci_chipset_tag_t sc_pc; 208 pcitag_t sc_pt; 209 #endif 210 int sc_ignore_codecready; 211 /* SiS 7012 hack */ 212 int sc_sample_size; 213 int sc_sts_reg; 214 /* 440MX workaround */ 215 int sc_dmamap_flags; 216 217 void (*sc_pintr)(void *); 218 void *sc_parg; 219 220 void (*sc_rintr)(void *); 221 void *sc_rarg; 222 223 /* Power Management */ 224 void *sc_powerhook; 225 int sc_suspend; 226 u_int16_t ext_status; 227 }; 228 229 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 230 & AC97_EXT_AUDIO_VRA) 231 232 /* Debug */ 233 #ifdef AUDIO_DEBUG 234 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 235 int auich_debug = 0xfffe; 236 #define ICH_DEBUG_CODECIO 0x0001 237 #define ICH_DEBUG_DMA 0x0002 238 #define ICH_DEBUG_PARAM 0x0004 239 #else 240 #define DPRINTF(x,y) /* nothing */ 241 #endif 242 243 int auich_match(struct device *, struct cfdata *, void *); 244 void auich_attach(struct device *, struct device *, void *); 245 int auich_intr(void *); 246 247 CFATTACH_DECL(auich, sizeof(struct auich_softc), 248 auich_match, auich_attach, NULL, NULL); 249 250 int auich_open(void *, int); 251 void auich_close(void *); 252 int auich_query_encoding(void *, struct audio_encoding *); 253 int auich_set_params(void *, int, int, struct audio_params *, 254 struct audio_params *); 255 int auich_round_blocksize(void *, int); 256 int auich_halt_output(void *); 257 int auich_halt_input(void *); 258 int auich_getdev(void *, struct audio_device *); 259 int auich_set_port(void *, mixer_ctrl_t *); 260 int auich_get_port(void *, mixer_ctrl_t *); 261 int auich_query_devinfo(void *, mixer_devinfo_t *); 262 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 263 void auich_freem(void *, void *, struct malloc_type *); 264 size_t auich_round_buffersize(void *, int, size_t); 265 paddr_t auich_mappage(void *, void *, off_t, int); 266 int auich_get_props(void *); 267 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 268 void *, struct audio_params *); 269 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 270 void *, struct audio_params *); 271 272 int auich_alloc_cdata(struct auich_softc *); 273 274 int auich_allocmem(struct auich_softc *, size_t, size_t, 275 struct auich_dma *); 276 int auich_freemem(struct auich_softc *, struct auich_dma *); 277 278 void auich_powerhook(int, void *); 279 int auich_set_rate(struct auich_softc *, int, u_long); 280 void auich_calibrate(struct device *); 281 282 283 struct audio_hw_if auich_hw_if = { 284 auich_open, 285 auich_close, 286 NULL, /* drain */ 287 auich_query_encoding, 288 auich_set_params, 289 auich_round_blocksize, 290 NULL, /* commit_setting */ 291 NULL, /* init_output */ 292 NULL, /* init_input */ 293 NULL, /* start_output */ 294 NULL, /* start_input */ 295 auich_halt_output, 296 auich_halt_input, 297 NULL, /* speaker_ctl */ 298 auich_getdev, 299 NULL, /* getfd */ 300 auich_set_port, 301 auich_get_port, 302 auich_query_devinfo, 303 auich_allocm, 304 auich_freem, 305 auich_round_buffersize, 306 auich_mappage, 307 auich_get_props, 308 auich_trigger_output, 309 auich_trigger_input, 310 NULL, /* dev_ioctl */ 311 }; 312 313 int auich_attach_codec(void *, struct ac97_codec_if *); 314 int auich_read_codec(void *, u_int8_t, u_int16_t *); 315 int auich_write_codec(void *, u_int8_t, u_int16_t); 316 void auich_reset_codec(void *); 317 318 static const struct auich_devtype { 319 int vendor; 320 int product; 321 const char *name; 322 const char *shortname; 323 int quirks; 324 #define QUIRK_IGNORE_CODEC_READY 0x01 325 #define QUIRK_IGNORE_CODEC_READY_MAYBE 0x02 326 } auich_devices[] = { 327 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 328 "i82801AA (ICH) AC-97 Audio", "ICH" }, 329 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 330 "i82801AB (ICH0) AC-97 Audio", "ICH0", 331 QUIRK_IGNORE_CODEC_READY_MAYBE }, /* i810-L */ 332 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 333 "i82801BA (ICH2) AC-97 Audio", "ICH2", 334 QUIRK_IGNORE_CODEC_READY_MAYBE }, 335 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 336 "i82440MX AC-97 Audio", "440MX" }, 337 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 338 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, /* i830Mx i845MP/MZ*/ 339 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 340 "i82801DB (ICH4) AC-97 Audio", "ICH4", 341 QUIRK_IGNORE_CODEC_READY_MAYBE }, 342 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 343 "i82801EB (ICH5) AC-97 Audio", "ICH5", 344 QUIRK_IGNORE_CODEC_READY }, 345 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 346 "SiS 7012 AC-97 Audio", "SiS7012" }, 347 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 348 "nForce MCP AC-97 Audio", "nForce-MCP", 349 QUIRK_IGNORE_CODEC_READY }, 350 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 351 "nForce2 MCP-T AC-97 Audio", "nForce-MCP-T" }, 352 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 353 "AMD768 AC-97 Audio", "AMD768" }, 354 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 355 "AMD8111 AC-97 Audio", "AMD8111" }, 356 { 0, 357 NULL, NULL }, 358 }; 359 360 static const struct auich_devtype * 361 auich_lookup(struct pci_attach_args *pa) 362 { 363 const struct auich_devtype *d; 364 365 for (d = auich_devices; d->name != NULL; d++) { 366 if (PCI_VENDOR(pa->pa_id) == d->vendor 367 && PCI_PRODUCT(pa->pa_id) == d->product) 368 return (d); 369 } 370 371 return (NULL); 372 } 373 374 int 375 auich_match(struct device *parent, struct cfdata *match, void *aux) 376 { 377 struct pci_attach_args *pa = aux; 378 379 if (auich_lookup(pa) != NULL) 380 return (1); 381 382 return (0); 383 } 384 385 void 386 auich_attach(struct device *parent, struct device *self, void *aux) 387 { 388 struct auich_softc *sc = (struct auich_softc *)self; 389 struct pci_attach_args *pa = aux; 390 pci_intr_handle_t ih; 391 bus_size_t mix_size, aud_size; 392 pcireg_t csr; 393 const char *intrstr; 394 const struct auich_devtype *d; 395 u_int32_t status; 396 397 aprint_naive(": Audio controller\n"); 398 399 d = auich_lookup(pa); 400 if (d == NULL) 401 panic("auich_attach: impossible"); 402 403 #ifdef DIAGNOSTIC 404 sc->sc_pc = pa->pa_pc; 405 sc->sc_pt = pa->pa_tag; 406 #endif 407 408 aprint_normal(": %s\n", d->name); 409 410 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 411 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 412 aprint_error("%s: can't map codec i/o space\n", 413 sc->sc_dev.dv_xname); 414 return; 415 } 416 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 417 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 418 aprint_error("%s: can't map device i/o space\n", 419 sc->sc_dev.dv_xname); 420 return; 421 } 422 sc->dmat = pa->pa_dmat; 423 424 /* enable bus mastering */ 425 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 426 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 427 csr | PCI_COMMAND_MASTER_ENABLE); 428 429 /* Map and establish the interrupt. */ 430 if (pci_intr_map(pa, &ih)) { 431 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 432 return; 433 } 434 intrstr = pci_intr_string(pa->pa_pc, ih); 435 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 436 auich_intr, sc); 437 if (sc->sc_ih == NULL) { 438 aprint_error("%s: can't establish interrupt", 439 sc->sc_dev.dv_xname); 440 if (intrstr != NULL) 441 aprint_normal(" at %s", intrstr); 442 aprint_normal("\n"); 443 return; 444 } 445 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 446 447 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 448 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 449 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 450 451 /* SiS 7012 needs special handling */ 452 if (d->vendor == PCI_VENDOR_SIS 453 && d->product == PCI_PRODUCT_SIS_7012_AC) { 454 sc->sc_sts_reg = ICH_PICB; 455 sc->sc_sample_size = 1; 456 } else { 457 sc->sc_sts_reg = ICH_STS; 458 sc->sc_sample_size = 2; 459 } 460 461 if (d->quirks & QUIRK_IGNORE_CODEC_READY) { 462 sc->sc_ignore_codecready = TRUE; 463 } 464 465 /* Workaround for a 440MX B-stepping erratum */ 466 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 467 if (d->vendor == PCI_VENDOR_INTEL 468 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 469 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 470 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 471 } 472 473 /* Set up DMA lists. */ 474 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 475 auich_alloc_cdata(sc); 476 477 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 478 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 479 480 /* Reset codec and AC'97 */ 481 auich_reset_codec(sc); 482 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 483 if (!(status & ICH_PCR)) { /* reset failure */ 484 /* It never return ICH_PCR in some cases */ 485 if (d->quirks & QUIRK_IGNORE_CODEC_READY_MAYBE) { 486 sc->sc_ignore_codecready = TRUE; 487 } else { 488 return; 489 } 490 } 491 /* Print capabilities though there are no supports for now */ 492 if ((status & ICH_SAMPLE_CAP) == ICH_POM20) 493 aprint_normal("%s: 20 bit precision support\n", 494 sc->sc_dev.dv_xname); 495 if ((status & ICH_CHAN_CAP) == ICH_PCM4) 496 aprint_normal("%s: 4ch PCM output support\n", 497 sc->sc_dev.dv_xname); 498 if ((status & ICH_CHAN_CAP) == ICH_PCM6) 499 aprint_normal("%s: 6ch PCM output support\n", 500 sc->sc_dev.dv_xname); 501 502 sc->host_if.arg = sc; 503 sc->host_if.attach = auich_attach_codec; 504 sc->host_if.read = auich_read_codec; 505 sc->host_if.write = auich_write_codec; 506 sc->host_if.reset = auich_reset_codec; 507 508 if (ac97_attach(&sc->host_if) != 0) 509 return; 510 511 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 512 513 /* Watch for power change */ 514 sc->sc_suspend = PWR_RESUME; 515 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 516 517 if (!IS_FIXED_RATE(sc->codec_if)) { 518 config_interrupts(self, auich_calibrate); 519 } 520 } 521 522 #define ICH_CODECIO_INTERVAL 10 523 int 524 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 525 { 526 struct auich_softc *sc = v; 527 int i; 528 uint32_t status; 529 530 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 531 if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) { 532 printf("auich_read_codec: codec is not ready (0x%x)\n", status); 533 *val = 0xffff; 534 return -1; 535 } 536 /* wait for an access semaphore */ 537 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 538 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 539 DELAY(ICH_CODECIO_INTERVAL)); 540 541 if (i > 0) { 542 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 543 DPRINTF(ICH_DEBUG_CODECIO, 544 ("auich_read_codec(%x, %x)\n", reg, *val)); 545 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 546 if (status & ICH_RCS) { 547 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 548 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 549 *val = 0xffff; 550 } 551 return 0; 552 } else { 553 DPRINTF(ICH_DEBUG_CODECIO, 554 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 555 return -1; 556 } 557 } 558 559 int 560 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 561 { 562 struct auich_softc *sc = v; 563 int i; 564 565 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 566 if (!sc->sc_ignore_codecready 567 && !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) { 568 printf("auich_write_codec: codec is not ready."); 569 return -1; 570 } 571 /* wait for an access semaphore */ 572 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 573 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 574 DELAY(ICH_CODECIO_INTERVAL)); 575 576 if (i > 0) { 577 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 578 return 0; 579 } else { 580 DPRINTF(ICH_DEBUG_CODECIO, 581 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 582 return -1; 583 } 584 } 585 586 int 587 auich_attach_codec(void *v, struct ac97_codec_if *cif) 588 { 589 struct auich_softc *sc = v; 590 591 sc->codec_if = cif; 592 return 0; 593 } 594 595 void 596 auich_reset_codec(void *v) 597 { 598 struct auich_softc *sc = v; 599 int i; 600 uint32_t control; 601 602 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 603 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 604 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 605 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 606 607 for (i = 500000; i-- && 608 !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR); 609 DELAY(1)); /* or ICH_SCR? */ 610 if (i <= 0) 611 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 612 } 613 614 int 615 auich_open(void *v, int flags) 616 { 617 return 0; 618 } 619 620 void 621 auich_close(void *v) 622 { 623 struct auich_softc *sc = v; 624 625 auich_halt_output(sc); 626 auich_halt_input(sc); 627 628 sc->sc_pintr = NULL; 629 sc->sc_rintr = NULL; 630 } 631 632 int 633 auich_query_encoding(void *v, struct audio_encoding *aep) 634 { 635 636 switch (aep->index) { 637 case 0: 638 strcpy(aep->name, AudioEulinear); 639 aep->encoding = AUDIO_ENCODING_ULINEAR; 640 aep->precision = 8; 641 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 642 return (0); 643 case 1: 644 strcpy(aep->name, AudioEmulaw); 645 aep->encoding = AUDIO_ENCODING_ULAW; 646 aep->precision = 8; 647 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 648 return (0); 649 case 2: 650 strcpy(aep->name, AudioEalaw); 651 aep->encoding = AUDIO_ENCODING_ALAW; 652 aep->precision = 8; 653 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 654 return (0); 655 case 3: 656 strcpy(aep->name, AudioEslinear); 657 aep->encoding = AUDIO_ENCODING_SLINEAR; 658 aep->precision = 8; 659 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 660 return (0); 661 case 4: 662 strcpy(aep->name, AudioEslinear_le); 663 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 664 aep->precision = 16; 665 aep->flags = 0; 666 return (0); 667 case 5: 668 strcpy(aep->name, AudioEulinear_le); 669 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 670 aep->precision = 16; 671 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 672 return (0); 673 case 6: 674 strcpy(aep->name, AudioEslinear_be); 675 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 676 aep->precision = 16; 677 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 678 return (0); 679 case 7: 680 strcpy(aep->name, AudioEulinear_be); 681 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 682 aep->precision = 16; 683 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 684 return (0); 685 default: 686 return (EINVAL); 687 } 688 } 689 690 int 691 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 692 { 693 int reg; 694 u_long ratetmp; 695 696 ratetmp = srate; 697 reg = mode == AUMODE_PLAY 698 ? AC97_REG_PCM_FRONT_DAC_RATE : AC97_REG_PCM_LR_ADC_RATE; 699 return sc->codec_if->vtbl->set_rate(sc->codec_if, reg, &ratetmp); 700 } 701 702 int 703 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 704 struct audio_params *rec) 705 { 706 struct auich_softc *sc = v; 707 struct audio_params *p; 708 int mode; 709 710 for (mode = AUMODE_RECORD; mode != -1; 711 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 712 if ((setmode & mode) == 0) 713 continue; 714 715 p = mode == AUMODE_PLAY ? play : rec; 716 if (p == NULL) 717 continue; 718 719 if ((p->sample_rate != 8000) && 720 (p->sample_rate != 11025) && 721 (p->sample_rate != 16000) && 722 (p->sample_rate != 22050) && 723 (p->sample_rate != 32000) && 724 (p->sample_rate != 44100) && 725 (p->sample_rate != 48000)) 726 return (EINVAL); 727 728 p->factor = 1; 729 if (p->precision == 8) 730 p->factor *= 2; 731 732 p->sw_code = NULL; 733 /* setup hardware formats */ 734 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 735 p->hw_precision = 16; 736 737 /* If monaural is requested, aurateconv expands a monaural 738 * stream to stereo. */ 739 if (p->channels < 2) 740 p->hw_channels = 2; 741 742 switch (p->encoding) { 743 case AUDIO_ENCODING_SLINEAR_BE: 744 if (p->precision == 16) { 745 p->sw_code = swap_bytes; 746 } else { 747 if (mode == AUMODE_PLAY) 748 p->sw_code = linear8_to_linear16_le; 749 else 750 p->sw_code = linear16_to_linear8_le; 751 } 752 break; 753 754 case AUDIO_ENCODING_SLINEAR_LE: 755 if (p->precision != 16) { 756 if (mode == AUMODE_PLAY) 757 p->sw_code = linear8_to_linear16_le; 758 else 759 p->sw_code = linear16_to_linear8_le; 760 } 761 break; 762 763 case AUDIO_ENCODING_ULINEAR_BE: 764 if (p->precision == 16) { 765 if (mode == AUMODE_PLAY) 766 p->sw_code = 767 swap_bytes_change_sign16_le; 768 else 769 p->sw_code = 770 change_sign16_swap_bytes_le; 771 } else { 772 if (mode == AUMODE_PLAY) 773 p->sw_code = 774 ulinear8_to_slinear16_le; 775 else 776 p->sw_code = 777 slinear16_to_ulinear8_le; 778 } 779 break; 780 781 case AUDIO_ENCODING_ULINEAR_LE: 782 if (p->precision == 16) { 783 p->sw_code = change_sign16_le; 784 } else { 785 if (mode == AUMODE_PLAY) 786 p->sw_code = 787 ulinear8_to_slinear16_le; 788 else 789 p->sw_code = 790 slinear16_to_ulinear8_le; 791 } 792 break; 793 794 case AUDIO_ENCODING_ULAW: 795 if (mode == AUMODE_PLAY) { 796 p->sw_code = mulaw_to_slinear16_le; 797 } else { 798 p->sw_code = slinear16_to_mulaw_le; 799 } 800 break; 801 802 case AUDIO_ENCODING_ALAW: 803 if (mode == AUMODE_PLAY) { 804 p->sw_code = alaw_to_slinear16_le; 805 } else { 806 p->sw_code = slinear16_to_alaw_le; 807 } 808 break; 809 810 default: 811 return (EINVAL); 812 } 813 814 if (IS_FIXED_RATE(sc->codec_if)) { 815 p->hw_sample_rate = AC97_SINGLE_RATE; 816 /* If hw_sample_rate is changed, aurateconv works. */ 817 } else { 818 if (auich_set_rate(sc, mode, p->sample_rate)) 819 return EINVAL; 820 } 821 } 822 823 return (0); 824 } 825 826 int 827 auich_round_blocksize(void *v, int blk) 828 { 829 830 return (blk & ~0x3f); /* keep good alignment */ 831 } 832 833 int 834 auich_halt_output(void *v) 835 { 836 struct auich_softc *sc = v; 837 838 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 839 840 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 841 842 return (0); 843 } 844 845 int 846 auich_halt_input(void *v) 847 { 848 struct auich_softc *sc = v; 849 850 DPRINTF(ICH_DEBUG_DMA, 851 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 852 853 /* XXX halt both unless known otherwise */ 854 855 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 856 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 857 858 return (0); 859 } 860 861 int 862 auich_getdev(void *v, struct audio_device *adp) 863 { 864 struct auich_softc *sc = v; 865 866 *adp = sc->sc_audev; 867 return (0); 868 } 869 870 int 871 auich_set_port(void *v, mixer_ctrl_t *cp) 872 { 873 struct auich_softc *sc = v; 874 875 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 876 } 877 878 int 879 auich_get_port(void *v, mixer_ctrl_t *cp) 880 { 881 struct auich_softc *sc = v; 882 883 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 884 } 885 886 int 887 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 888 { 889 struct auich_softc *sc = v; 890 891 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 892 } 893 894 void * 895 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 896 int flags) 897 { 898 struct auich_softc *sc = v; 899 struct auich_dma *p; 900 int error; 901 902 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 903 return (NULL); 904 905 p = malloc(sizeof(*p), pool, flags|M_ZERO); 906 if (p == NULL) 907 return (NULL); 908 909 error = auich_allocmem(sc, size, 0, p); 910 if (error) { 911 free(p, pool); 912 return (NULL); 913 } 914 915 p->next = sc->sc_dmas; 916 sc->sc_dmas = p; 917 918 return (KERNADDR(p)); 919 } 920 921 void 922 auich_freem(void *v, void *ptr, struct malloc_type *pool) 923 { 924 struct auich_softc *sc = v; 925 struct auich_dma *p, **pp; 926 927 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 928 if (KERNADDR(p) == ptr) { 929 auich_freemem(sc, p); 930 *pp = p->next; 931 free(p, pool); 932 return; 933 } 934 } 935 } 936 937 size_t 938 auich_round_buffersize(void *v, int direction, size_t size) 939 { 940 941 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 942 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 943 944 return size; 945 } 946 947 paddr_t 948 auich_mappage(void *v, void *mem, off_t off, int prot) 949 { 950 struct auich_softc *sc = v; 951 struct auich_dma *p; 952 953 if (off < 0) 954 return (-1); 955 956 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 957 ; 958 if (!p) 959 return (-1); 960 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 961 off, prot, BUS_DMA_WAITOK)); 962 } 963 964 int 965 auich_get_props(void *v) 966 { 967 struct auich_softc *sc = v; 968 int props; 969 970 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 971 /* 972 * Even if the codec is fixed-rate, set_param() succeeds for any sample 973 * rate because of aurateconv. Applications can't know what rate the 974 * device can process in the case of mmap(). 975 */ 976 if (!IS_FIXED_RATE(sc->codec_if)) 977 props |= AUDIO_PROP_MMAP; 978 return props; 979 } 980 981 int 982 auich_intr(void *v) 983 { 984 struct auich_softc *sc = v; 985 int ret = 0, sts, gsts, i, qptr; 986 987 #ifdef DIAGNOSTIC 988 int csts; 989 #endif 990 991 #ifdef DIAGNOSTIC 992 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 993 if (csts & PCI_STATUS_MASTER_ABORT) { 994 printf("auich_intr: PCI master abort\n"); 995 } 996 #endif 997 998 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 999 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 1000 1001 if (gsts & ICH_POINT) { 1002 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 1003 DPRINTF(ICH_DEBUG_DMA, 1004 ("auich_intr: osts=0x%x\n", sts)); 1005 1006 if (sts & ICH_FIFOE) { 1007 printf("%s: fifo underrun # %u\n", 1008 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1009 } 1010 1011 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1012 if (sts & (ICH_LVBCI | ICH_CELV)) { 1013 struct auich_dmalist *q; 1014 1015 qptr = sc->ptr_pcmo; 1016 1017 while (qptr != i) { 1018 q = &sc->dmalist_pcmo[qptr]; 1019 1020 q->base = sc->pcmo_p; 1021 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1022 DPRINTF(ICH_DEBUG_DMA, 1023 ("auich_intr: %p, %p = %x @ 0x%x\n", 1024 &sc->dmalist_pcmo[i], q, 1025 sc->pcmo_blksize / 2, sc->pcmo_p)); 1026 1027 sc->pcmo_p += sc->pcmo_blksize; 1028 if (sc->pcmo_p >= sc->pcmo_end) 1029 sc->pcmo_p = sc->pcmo_start; 1030 1031 if (++qptr == ICH_DMALIST_MAX) 1032 qptr = 0; 1033 } 1034 1035 sc->ptr_pcmo = qptr; 1036 bus_space_write_1(sc->iot, sc->aud_ioh, 1037 ICH_PCMO + ICH_LVI, 1038 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1039 } 1040 1041 if (sts & ICH_BCIS && sc->sc_pintr) 1042 sc->sc_pintr(sc->sc_parg); 1043 1044 /* int ack */ 1045 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1046 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1047 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1048 ret++; 1049 } 1050 1051 if (gsts & ICH_PIINT) { 1052 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1053 DPRINTF(ICH_DEBUG_DMA, 1054 ("auich_intr: ists=0x%x\n", sts)); 1055 1056 if (sts & ICH_FIFOE) { 1057 printf("%s: fifo overrun # %u\n", 1058 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1059 } 1060 1061 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1062 if (sts & (ICH_LVBCI | ICH_CELV)) { 1063 struct auich_dmalist *q; 1064 1065 qptr = sc->ptr_pcmi; 1066 1067 while (qptr != i) { 1068 q = &sc->dmalist_pcmi[qptr]; 1069 1070 q->base = sc->pcmi_p; 1071 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1072 DPRINTF(ICH_DEBUG_DMA, 1073 ("auich_intr: %p, %p = %x @ 0x%x\n", 1074 &sc->dmalist_pcmi[i], q, 1075 sc->pcmi_blksize / 2, sc->pcmi_p)); 1076 1077 sc->pcmi_p += sc->pcmi_blksize; 1078 if (sc->pcmi_p >= sc->pcmi_end) 1079 sc->pcmi_p = sc->pcmi_start; 1080 1081 if (++qptr == ICH_DMALIST_MAX) 1082 qptr = 0; 1083 } 1084 1085 sc->ptr_pcmi = qptr; 1086 bus_space_write_1(sc->iot, sc->aud_ioh, 1087 ICH_PCMI + ICH_LVI, 1088 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1089 } 1090 1091 if (sts & ICH_BCIS && sc->sc_rintr) 1092 sc->sc_rintr(sc->sc_rarg); 1093 1094 /* int ack */ 1095 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1096 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1097 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1098 ret++; 1099 } 1100 1101 if (gsts & ICH_MIINT) { 1102 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1103 DPRINTF(ICH_DEBUG_DMA, 1104 ("auich_intr: ists=0x%x\n", sts)); 1105 if (sts & ICH_FIFOE) 1106 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1107 1108 /* TODO mic input DMA */ 1109 1110 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1111 } 1112 1113 return ret; 1114 } 1115 1116 int 1117 auich_trigger_output(void *v, void *start, void *end, int blksize, 1118 void (*intr)(void *), void *arg, struct audio_params *param) 1119 { 1120 struct auich_softc *sc = v; 1121 struct auich_dmalist *q; 1122 struct auich_dma *p; 1123 size_t size; 1124 #ifdef DIAGNOSTIC 1125 int csts; 1126 #endif 1127 1128 DPRINTF(ICH_DEBUG_DMA, 1129 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1130 start, end, blksize, intr, arg, param)); 1131 1132 sc->sc_pintr = intr; 1133 sc->sc_parg = arg; 1134 #ifdef DIAGNOSTIC 1135 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1136 if (csts & PCI_STATUS_MASTER_ABORT) { 1137 printf("auich_trigger_output: PCI master abort\n"); 1138 } 1139 #endif 1140 1141 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1142 ; 1143 if (!p) { 1144 printf("auich_trigger_output: bad addr %p\n", start); 1145 return (EINVAL); 1146 } 1147 1148 size = (size_t)((caddr_t)end - (caddr_t)start); 1149 1150 /* 1151 * The logic behind this is: 1152 * setup one buffer to play, then LVI dump out the rest 1153 * to the scatter-gather chain. 1154 */ 1155 sc->pcmo_start = DMAADDR(p); 1156 sc->pcmo_p = sc->pcmo_start + blksize; 1157 sc->pcmo_end = sc->pcmo_start + size; 1158 sc->pcmo_blksize = blksize; 1159 1160 sc->ptr_pcmo = 0; 1161 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1162 q->base = sc->pcmo_start; 1163 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1164 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1165 sc->ptr_pcmo = 0; 1166 1167 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1168 sc->sc_cddma + ICH_PCMO_OFF(0)); 1169 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1170 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1171 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1172 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1173 1174 return (0); 1175 } 1176 1177 int 1178 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1179 void *v; 1180 void *start, *end; 1181 int blksize; 1182 void (*intr)(void *); 1183 void *arg; 1184 struct audio_params *param; 1185 { 1186 struct auich_softc *sc = v; 1187 struct auich_dmalist *q; 1188 struct auich_dma *p; 1189 size_t size; 1190 #ifdef DIAGNOSTIC 1191 int csts; 1192 #endif 1193 1194 DPRINTF(ICH_DEBUG_DMA, 1195 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1196 start, end, blksize, intr, arg, param)); 1197 1198 sc->sc_rintr = intr; 1199 sc->sc_rarg = arg; 1200 1201 #ifdef DIAGNOSTIC 1202 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1203 if (csts & PCI_STATUS_MASTER_ABORT) { 1204 printf("auich_trigger_input: PCI master abort\n"); 1205 } 1206 #endif 1207 1208 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1209 ; 1210 if (!p) { 1211 printf("auich_trigger_input: bad addr %p\n", start); 1212 return (EINVAL); 1213 } 1214 1215 size = (size_t)((caddr_t)end - (caddr_t)start); 1216 1217 /* 1218 * The logic behind this is: 1219 * setup one buffer to play, then LVI dump out the rest 1220 * to the scatter-gather chain. 1221 */ 1222 sc->pcmi_start = DMAADDR(p); 1223 sc->pcmi_p = sc->pcmi_start + blksize; 1224 sc->pcmi_end = sc->pcmi_start + size; 1225 sc->pcmi_blksize = blksize; 1226 1227 sc->ptr_pcmi = 0; 1228 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1229 q->base = sc->pcmi_start; 1230 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1231 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1232 sc->ptr_pcmi = 0; 1233 1234 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1235 sc->sc_cddma + ICH_PCMI_OFF(0)); 1236 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1237 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1238 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1239 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1240 1241 return (0); 1242 } 1243 1244 int 1245 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1246 struct auich_dma *p) 1247 { 1248 int error; 1249 1250 p->size = size; 1251 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1252 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1253 &p->nsegs, BUS_DMA_NOWAIT); 1254 if (error) 1255 return (error); 1256 1257 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1258 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1259 if (error) 1260 goto free; 1261 1262 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1263 0, BUS_DMA_NOWAIT, &p->map); 1264 if (error) 1265 goto unmap; 1266 1267 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1268 BUS_DMA_NOWAIT); 1269 if (error) 1270 goto destroy; 1271 return (0); 1272 1273 destroy: 1274 bus_dmamap_destroy(sc->dmat, p->map); 1275 unmap: 1276 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1277 free: 1278 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1279 return (error); 1280 } 1281 1282 int 1283 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1284 { 1285 1286 bus_dmamap_unload(sc->dmat, p->map); 1287 bus_dmamap_destroy(sc->dmat, p->map); 1288 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1289 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1290 return (0); 1291 } 1292 1293 int 1294 auich_alloc_cdata(struct auich_softc *sc) 1295 { 1296 bus_dma_segment_t seg; 1297 int error, rseg; 1298 1299 /* 1300 * Allocate the control data structure, and create and load the 1301 * DMA map for it. 1302 */ 1303 if ((error = bus_dmamem_alloc(sc->dmat, 1304 sizeof(struct auich_cdata), 1305 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1306 printf("%s: unable to allocate control data, error = %d\n", 1307 sc->sc_dev.dv_xname, error); 1308 goto fail_0; 1309 } 1310 1311 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1312 sizeof(struct auich_cdata), 1313 (caddr_t *) &sc->sc_cdata, 1314 sc->sc_dmamap_flags)) != 0) { 1315 printf("%s: unable to map control data, error = %d\n", 1316 sc->sc_dev.dv_xname, error); 1317 goto fail_1; 1318 } 1319 1320 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1321 sizeof(struct auich_cdata), 0, 0, 1322 &sc->sc_cddmamap)) != 0) { 1323 printf("%s: unable to create control data DMA map, " 1324 "error = %d\n", sc->sc_dev.dv_xname, error); 1325 goto fail_2; 1326 } 1327 1328 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1329 sc->sc_cdata, sizeof(struct auich_cdata), 1330 NULL, 0)) != 0) { 1331 printf("%s: unable tp load control data DMA map, " 1332 "error = %d\n", sc->sc_dev.dv_xname, error); 1333 goto fail_3; 1334 } 1335 1336 return (0); 1337 1338 fail_3: 1339 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1340 fail_2: 1341 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1342 sizeof(struct auich_cdata)); 1343 fail_1: 1344 bus_dmamem_free(sc->dmat, &seg, rseg); 1345 fail_0: 1346 return (error); 1347 } 1348 1349 void 1350 auich_powerhook(int why, void *addr) 1351 { 1352 struct auich_softc *sc = (struct auich_softc *)addr; 1353 1354 switch (why) { 1355 case PWR_SUSPEND: 1356 case PWR_STANDBY: 1357 /* Power down */ 1358 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1359 sc->sc_suspend = why; 1360 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1361 break; 1362 1363 case PWR_RESUME: 1364 /* Wake up */ 1365 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1366 if (sc->sc_suspend == PWR_RESUME) { 1367 printf("%s: resume without suspend.\n", 1368 sc->sc_dev.dv_xname); 1369 sc->sc_suspend = why; 1370 return; 1371 } 1372 sc->sc_suspend = why; 1373 auich_reset_codec(sc); 1374 DELAY(1000); 1375 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1376 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1377 break; 1378 1379 case PWR_SOFTSUSPEND: 1380 case PWR_SOFTSTANDBY: 1381 case PWR_SOFTRESUME: 1382 break; 1383 } 1384 } 1385 1386 1387 /* -------------------------------------------------------------------- */ 1388 /* Calibrate card (some boards are overclocked and need scaling) */ 1389 1390 void 1391 auich_calibrate(struct device *self) 1392 { 1393 struct auich_softc *sc; 1394 struct timeval t1, t2; 1395 u_int8_t ociv, nciv; 1396 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1397 void *temp_buffer; 1398 struct auich_dma *p; 1399 1400 sc = (struct auich_softc*)self; 1401 /* 1402 * Grab audio from input for fixed interval and compare how 1403 * much we actually get with what we expect. Interval needs 1404 * to be sufficiently short that no interrupts are 1405 * generated. 1406 */ 1407 1408 /* Setup a buffer */ 1409 bytes = 16000; 1410 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1411 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1412 ; 1413 if (p == NULL) { 1414 printf("auich_calibrate: bad address %p\n", temp_buffer); 1415 return; 1416 } 1417 sc->dmalist_pcmi[0].base = DMAADDR(p); 1418 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size) | ICH_DMAF_IOC; 1419 1420 /* 1421 * our data format is stereo, 16 bit so each sample is 4 bytes. 1422 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1423 * we're going to start recording with interrupts disabled and measure 1424 * the time taken for one block to complete. we know the block size, 1425 * we know the time in microseconds, we calculate the sample rate: 1426 * 1427 * actual_rate [bps] = bytes / (time [s] * 4) 1428 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1429 * actual_rate [Hz] = (bytes * 250000) / time [us] 1430 */ 1431 1432 /* prepare */ 1433 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1434 nciv = ociv; 1435 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1436 sc->sc_cddma + ICH_PCMI_OFF(0)); 1437 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1438 (0 - 1) & ICH_LVI_MASK); 1439 1440 /* start */ 1441 microtime(&t1); 1442 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1443 1444 /* wait */ 1445 while (nciv == ociv) { 1446 microtime(&t2); 1447 if (t2.tv_sec - t1.tv_sec > 1) 1448 break; 1449 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1450 ICH_PCMI + ICH_CIV); 1451 } 1452 microtime(&t2); 1453 1454 /* stop */ 1455 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1456 1457 /* reset */ 1458 DELAY(100); 1459 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1460 1461 /* turn time delta into us */ 1462 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1463 1464 auich_freem(sc, temp_buffer, M_DEVBUF); 1465 1466 if (nciv == ociv) { 1467 printf("%s: ac97 link rate calibration timed out after %d us\n", 1468 sc->sc_dev.dv_xname, wait_us); 1469 return; 1470 } 1471 1472 actual_48k_rate = (bytes * 250000U) / wait_us; 1473 1474 if (actual_48k_rate <= 48500) 1475 ac97rate = 48000; 1476 else 1477 ac97rate = actual_48k_rate; 1478 1479 printf("%s: measured ac97 link rate at %d Hz", 1480 sc->sc_dev.dv_xname, actual_48k_rate); 1481 if (ac97rate != actual_48k_rate) 1482 printf(", will use %d Hz", ac97rate); 1483 printf("\n"); 1484 1485 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1486 } 1487
Indexes created Thu Oct 23 22:10:10 GMT 2025