auich.c revision 1.43
1 /* $NetBSD: auich.c,v 1.43 2003/10/21 01:12:42 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * 108 * TODO: 109 * - Add support for the dedicated microphone input. 110 * 111 * NOTE: 112 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 113 * It causes PCI master abort and hangups until cold reboot. 114 * http://www.intel.com/design/chipsets/specupdt/245051.htm 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.43 2003/10/21 01:12:42 fvdl Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/kernel.h> 123 #include <sys/malloc.h> 124 #include <sys/device.h> 125 #include <sys/fcntl.h> 126 #include <sys/proc.h> 127 128 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 129 130 #include <dev/pci/pcidevs.h> 131 #include <dev/pci/pcivar.h> 132 #include <dev/pci/auichreg.h> 133 134 #include <sys/audioio.h> 135 #include <dev/audio_if.h> 136 #include <dev/mulaw.h> 137 #include <dev/auconv.h> 138 139 #include <machine/bus.h> 140 141 #include <dev/ic/ac97reg.h> 142 #include <dev/ic/ac97var.h> 143 144 struct auich_dma { 145 bus_dmamap_t map; 146 caddr_t addr; 147 bus_dma_segment_t segs[1]; 148 int nsegs; 149 size_t size; 150 struct auich_dma *next; 151 }; 152 153 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 154 #define KERNADDR(p) ((void *)((p)->addr)) 155 156 struct auich_cdata { 157 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 158 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 159 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 160 }; 161 162 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 163 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 164 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 165 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 166 167 struct auich_softc { 168 struct device sc_dev; 169 void *sc_ih; 170 171 audio_device_t sc_audev; 172 173 bus_space_tag_t iot; 174 bus_space_handle_t mix_ioh; 175 bus_space_handle_t aud_ioh; 176 bus_dma_tag_t dmat; 177 178 struct ac97_codec_if *codec_if; 179 struct ac97_host_if host_if; 180 181 /* DMA scatter-gather lists. */ 182 bus_dmamap_t sc_cddmamap; 183 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 184 185 struct auich_cdata *sc_cdata; 186 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 187 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 188 #define dmalist_mici sc_cdata->ic_dmalist_mici 189 190 int ptr_pcmo, 191 ptr_pcmi, 192 ptr_mici; 193 194 /* i/o buffer pointers */ 195 u_int32_t pcmo_start, pcmo_p, pcmo_end; 196 int pcmo_blksize, pcmo_fifoe; 197 198 u_int32_t pcmi_start, pcmi_p, pcmi_end; 199 int pcmi_blksize, pcmi_fifoe; 200 201 u_int32_t mici_start, mici_p, mici_end; 202 int mici_blksize, mici_fifoe; 203 204 struct auich_dma *sc_dmas; 205 206 #ifdef DIAGNOSTIC 207 pci_chipset_tag_t sc_pc; 208 pcitag_t sc_pt; 209 #endif 210 int sc_ignore_codecready; 211 /* SiS 7012 hack */ 212 int sc_sample_size; 213 int sc_sts_reg; 214 /* 440MX workaround */ 215 int sc_dmamap_flags; 216 217 void (*sc_pintr)(void *); 218 void *sc_parg; 219 220 void (*sc_rintr)(void *); 221 void *sc_rarg; 222 223 /* Power Management */ 224 void *sc_powerhook; 225 int sc_suspend; 226 u_int16_t ext_status; 227 }; 228 229 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 230 & AC97_EXT_AUDIO_VRA) 231 #define SUPPORTS_4CH(codec) ((codec)->vtbl->get_extcaps(codec) \ 232 & AC97_EXT_AUDIO_SDAC) 233 #define AC97_6CH_DACS (AC97_EXT_AUDIO_SDAC | AC97_EXT_AUDIO_CDAC \ 234 | AC97_EXT_AUDIO_LDAC) 235 #define SUPPORTS_6CH(codec) (((codec)->vtbl->get_extcaps(codec) \ 236 & AC97_6CH_DACS) == AC97_6CH_DACS) 237 238 /* Debug */ 239 #ifdef AUDIO_DEBUG 240 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 241 int auich_debug = 0xfffe; 242 #define ICH_DEBUG_CODECIO 0x0001 243 #define ICH_DEBUG_DMA 0x0002 244 #define ICH_DEBUG_PARAM 0x0004 245 #else 246 #define DPRINTF(x,y) /* nothing */ 247 #endif 248 249 int auich_match(struct device *, struct cfdata *, void *); 250 void auich_attach(struct device *, struct device *, void *); 251 int auich_intr(void *); 252 253 CFATTACH_DECL(auich, sizeof(struct auich_softc), 254 auich_match, auich_attach, NULL, NULL); 255 256 int auich_open(void *, int); 257 void auich_close(void *); 258 int auich_query_encoding(void *, struct audio_encoding *); 259 int auich_set_params(void *, int, int, struct audio_params *, 260 struct audio_params *); 261 int auich_round_blocksize(void *, int); 262 int auich_halt_output(void *); 263 int auich_halt_input(void *); 264 int auich_getdev(void *, struct audio_device *); 265 int auich_set_port(void *, mixer_ctrl_t *); 266 int auich_get_port(void *, mixer_ctrl_t *); 267 int auich_query_devinfo(void *, mixer_devinfo_t *); 268 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 269 void auich_freem(void *, void *, struct malloc_type *); 270 size_t auich_round_buffersize(void *, int, size_t); 271 paddr_t auich_mappage(void *, void *, off_t, int); 272 int auich_get_props(void *); 273 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 274 void *, struct audio_params *); 275 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 276 void *, struct audio_params *); 277 278 int auich_alloc_cdata(struct auich_softc *); 279 280 int auich_allocmem(struct auich_softc *, size_t, size_t, 281 struct auich_dma *); 282 int auich_freemem(struct auich_softc *, struct auich_dma *); 283 284 void auich_powerhook(int, void *); 285 int auich_set_rate(struct auich_softc *, int, u_long); 286 void auich_finish_attach(struct device *); 287 void auich_calibrate(struct auich_softc *); 288 289 290 struct audio_hw_if auich_hw_if = { 291 auich_open, 292 auich_close, 293 NULL, /* drain */ 294 auich_query_encoding, 295 auich_set_params, 296 auich_round_blocksize, 297 NULL, /* commit_setting */ 298 NULL, /* init_output */ 299 NULL, /* init_input */ 300 NULL, /* start_output */ 301 NULL, /* start_input */ 302 auich_halt_output, 303 auich_halt_input, 304 NULL, /* speaker_ctl */ 305 auich_getdev, 306 NULL, /* getfd */ 307 auich_set_port, 308 auich_get_port, 309 auich_query_devinfo, 310 auich_allocm, 311 auich_freem, 312 auich_round_buffersize, 313 auich_mappage, 314 auich_get_props, 315 auich_trigger_output, 316 auich_trigger_input, 317 NULL, /* dev_ioctl */ 318 }; 319 320 int auich_attach_codec(void *, struct ac97_codec_if *); 321 int auich_read_codec(void *, u_int8_t, u_int16_t *); 322 int auich_write_codec(void *, u_int8_t, u_int16_t); 323 void auich_reset_codec(void *); 324 325 static const struct auich_devtype { 326 int vendor; 327 int product; 328 const char *name; 329 const char *shortname; 330 int quirks; 331 #define QUIRK_IGNORE_CODEC_READY 0x01 332 #define QUIRK_IGNORE_CODEC_READY_MAYBE 0x02 333 } auich_devices[] = { 334 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 335 "i82801AA (ICH) AC-97 Audio", "ICH" }, 336 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 337 "i82801AB (ICH0) AC-97 Audio", "ICH0", 338 QUIRK_IGNORE_CODEC_READY_MAYBE }, 339 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 340 "i82801BA (ICH2) AC-97 Audio", "ICH2", 341 QUIRK_IGNORE_CODEC_READY_MAYBE }, 342 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 343 "i82440MX AC-97 Audio", "440MX" }, 344 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 345 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 346 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 347 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4", 348 QUIRK_IGNORE_CODEC_READY_MAYBE }, 349 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 350 "i82801EB (ICH5) AC-97 Audio", "ICH5", 351 QUIRK_IGNORE_CODEC_READY }, 352 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 353 "SiS 7012 AC-97 Audio", "SiS7012" }, 354 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 355 "nForce MCP AC-97 Audio", "nForce-MCP", 356 QUIRK_IGNORE_CODEC_READY }, 357 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 358 "nForce2 MCP-T AC-97 Audio", "nForce-MCP-T" }, 359 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 360 "AMD768 AC-97 Audio", "AMD768" }, 361 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 362 "AMD8111 AC-97 Audio", "AMD8111" }, 363 { 0, 0, 364 NULL, NULL }, 365 }; 366 367 static const struct auich_devtype * 368 auich_lookup(struct pci_attach_args *pa) 369 { 370 const struct auich_devtype *d; 371 372 for (d = auich_devices; d->name != NULL; d++) { 373 if (PCI_VENDOR(pa->pa_id) == d->vendor 374 && PCI_PRODUCT(pa->pa_id) == d->product) 375 return (d); 376 } 377 378 return (NULL); 379 } 380 381 int 382 auich_match(struct device *parent, struct cfdata *match, void *aux) 383 { 384 struct pci_attach_args *pa = aux; 385 386 if (auich_lookup(pa) != NULL) 387 return (1); 388 389 return (0); 390 } 391 392 void 393 auich_attach(struct device *parent, struct device *self, void *aux) 394 { 395 struct auich_softc *sc = (struct auich_softc *)self; 396 struct pci_attach_args *pa = aux; 397 pci_intr_handle_t ih; 398 bus_size_t mix_size, aud_size; 399 pcireg_t csr; 400 const char *intrstr; 401 const struct auich_devtype *d; 402 u_int32_t status; 403 404 aprint_naive(": Audio controller\n"); 405 406 d = auich_lookup(pa); 407 if (d == NULL) 408 panic("auich_attach: impossible"); 409 410 #ifdef DIAGNOSTIC 411 sc->sc_pc = pa->pa_pc; 412 sc->sc_pt = pa->pa_tag; 413 #endif 414 415 aprint_normal(": %s\n", d->name); 416 417 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 418 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 419 aprint_error("%s: can't map codec i/o space\n", 420 sc->sc_dev.dv_xname); 421 return; 422 } 423 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 424 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 425 aprint_error("%s: can't map device i/o space\n", 426 sc->sc_dev.dv_xname); 427 return; 428 } 429 sc->dmat = pa->pa_dmat; 430 431 /* enable bus mastering */ 432 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 433 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 434 csr | PCI_COMMAND_MASTER_ENABLE); 435 436 /* Map and establish the interrupt. */ 437 if (pci_intr_map(pa, &ih)) { 438 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 439 return; 440 } 441 intrstr = pci_intr_string(pa->pa_pc, ih); 442 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 443 auich_intr, sc); 444 if (sc->sc_ih == NULL) { 445 aprint_error("%s: can't establish interrupt", 446 sc->sc_dev.dv_xname); 447 if (intrstr != NULL) 448 aprint_normal(" at %s", intrstr); 449 aprint_normal("\n"); 450 return; 451 } 452 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 453 454 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 455 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 456 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 457 458 /* SiS 7012 needs special handling */ 459 if (d->vendor == PCI_VENDOR_SIS 460 && d->product == PCI_PRODUCT_SIS_7012_AC) { 461 sc->sc_sts_reg = ICH_PICB; 462 sc->sc_sample_size = 1; 463 } else { 464 sc->sc_sts_reg = ICH_STS; 465 sc->sc_sample_size = 2; 466 } 467 468 if (d->quirks & QUIRK_IGNORE_CODEC_READY) { 469 sc->sc_ignore_codecready = TRUE; 470 } 471 472 /* Workaround for a 440MX B-stepping erratum */ 473 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 474 if (d->vendor == PCI_VENDOR_INTEL 475 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 476 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 477 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 478 } 479 480 /* Set up DMA lists. */ 481 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 482 auich_alloc_cdata(sc); 483 484 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 485 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 486 487 /* Reset codec and AC'97 */ 488 auich_reset_codec(sc); 489 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 490 if (!(status & ICH_PCR)) { /* reset failure */ 491 /* It never return ICH_PCR in some cases */ 492 if (d->quirks & QUIRK_IGNORE_CODEC_READY_MAYBE) { 493 sc->sc_ignore_codecready = TRUE; 494 } else { 495 return; 496 } 497 } 498 499 sc->host_if.arg = sc; 500 sc->host_if.attach = auich_attach_codec; 501 sc->host_if.read = auich_read_codec; 502 sc->host_if.write = auich_write_codec; 503 sc->host_if.reset = auich_reset_codec; 504 505 if (ac97_attach(&sc->host_if) != 0) 506 return; 507 508 /* Watch for power change */ 509 sc->sc_suspend = PWR_RESUME; 510 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 511 512 config_interrupts(self, auich_finish_attach); 513 } 514 515 void 516 auich_finish_attach(struct device *self) 517 { 518 struct auich_softc *sc = (void *)self; 519 520 if (!IS_FIXED_RATE(sc->codec_if)) 521 auich_calibrate(sc); 522 523 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 524 } 525 526 #define ICH_CODECIO_INTERVAL 10 527 int 528 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 529 { 530 struct auich_softc *sc = v; 531 int i; 532 uint32_t status; 533 534 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 535 if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) { 536 printf("auich_read_codec: codec is not ready (0x%x)\n", status); 537 *val = 0xffff; 538 return -1; 539 } 540 /* wait for an access semaphore */ 541 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 542 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 543 DELAY(ICH_CODECIO_INTERVAL)); 544 545 if (i > 0) { 546 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 547 DPRINTF(ICH_DEBUG_CODECIO, 548 ("auich_read_codec(%x, %x)\n", reg, *val)); 549 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 550 if (status & ICH_RCS) { 551 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 552 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 553 *val = 0xffff; 554 } 555 return 0; 556 } else { 557 DPRINTF(ICH_DEBUG_CODECIO, 558 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 559 return -1; 560 } 561 } 562 563 int 564 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 565 { 566 struct auich_softc *sc = v; 567 int i; 568 569 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 570 if (!sc->sc_ignore_codecready 571 && !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) { 572 printf("auich_write_codec: codec is not ready."); 573 return -1; 574 } 575 /* wait for an access semaphore */ 576 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 577 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 578 DELAY(ICH_CODECIO_INTERVAL)); 579 580 if (i > 0) { 581 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 582 return 0; 583 } else { 584 DPRINTF(ICH_DEBUG_CODECIO, 585 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 586 return -1; 587 } 588 } 589 590 int 591 auich_attach_codec(void *v, struct ac97_codec_if *cif) 592 { 593 struct auich_softc *sc = v; 594 595 sc->codec_if = cif; 596 return 0; 597 } 598 599 void 600 auich_reset_codec(void *v) 601 { 602 struct auich_softc *sc = v; 603 int i; 604 uint32_t control; 605 606 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 607 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 608 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 609 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 610 611 for (i = 500000; i-- && 612 !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR); 613 DELAY(1)); /* or ICH_SCR? */ 614 if (i <= 0) 615 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 616 } 617 618 int 619 auich_open(void *v, int flags) 620 { 621 return 0; 622 } 623 624 void 625 auich_close(void *v) 626 { 627 struct auich_softc *sc = v; 628 629 auich_halt_output(sc); 630 auich_halt_input(sc); 631 632 sc->sc_pintr = NULL; 633 sc->sc_rintr = NULL; 634 } 635 636 int 637 auich_query_encoding(void *v, struct audio_encoding *aep) 638 { 639 640 switch (aep->index) { 641 case 0: 642 strcpy(aep->name, AudioEulinear); 643 aep->encoding = AUDIO_ENCODING_ULINEAR; 644 aep->precision = 8; 645 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 646 return (0); 647 case 1: 648 strcpy(aep->name, AudioEmulaw); 649 aep->encoding = AUDIO_ENCODING_ULAW; 650 aep->precision = 8; 651 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 652 return (0); 653 case 2: 654 strcpy(aep->name, AudioEalaw); 655 aep->encoding = AUDIO_ENCODING_ALAW; 656 aep->precision = 8; 657 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 658 return (0); 659 case 3: 660 strcpy(aep->name, AudioEslinear); 661 aep->encoding = AUDIO_ENCODING_SLINEAR; 662 aep->precision = 8; 663 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 664 return (0); 665 case 4: 666 strcpy(aep->name, AudioEslinear_le); 667 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 668 aep->precision = 16; 669 aep->flags = 0; 670 return (0); 671 case 5: 672 strcpy(aep->name, AudioEulinear_le); 673 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 674 aep->precision = 16; 675 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 676 return (0); 677 case 6: 678 strcpy(aep->name, AudioEslinear_be); 679 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 680 aep->precision = 16; 681 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 682 return (0); 683 case 7: 684 strcpy(aep->name, AudioEulinear_be); 685 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 686 aep->precision = 16; 687 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 688 return (0); 689 default: 690 return (EINVAL); 691 } 692 } 693 694 int 695 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 696 { 697 int ret; 698 u_long ratetmp; 699 700 ratetmp = srate; 701 if (mode == AUMODE_RECORD) 702 return sc->codec_if->vtbl->set_rate(sc->codec_if, 703 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 704 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 705 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 706 if (ret) 707 return ret; 708 ratetmp = srate; 709 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 710 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 711 if (ret) 712 return ret; 713 ratetmp = srate; 714 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 715 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 716 return ret; 717 } 718 719 int 720 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 721 struct audio_params *rec) 722 { 723 struct auich_softc *sc = v; 724 struct audio_params *p; 725 int mode; 726 u_int32_t control; 727 728 for (mode = AUMODE_RECORD; mode != -1; 729 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 730 if ((setmode & mode) == 0) 731 continue; 732 733 p = mode == AUMODE_PLAY ? play : rec; 734 if (p == NULL) 735 continue; 736 737 if ((p->sample_rate != 8000) && 738 (p->sample_rate != 11025) && 739 (p->sample_rate != 12000) && 740 (p->sample_rate != 16000) && 741 (p->sample_rate != 22050) && 742 (p->sample_rate != 24000) && 743 (p->sample_rate != 32000) && 744 (p->sample_rate != 44100) && 745 (p->sample_rate != 48000)) 746 return (EINVAL); 747 748 p->factor = 1; 749 if (p->precision == 8) 750 p->factor *= 2; 751 752 p->sw_code = NULL; 753 /* setup hardware formats */ 754 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 755 p->hw_precision = 16; 756 757 if (mode == AUMODE_RECORD) { 758 if (p->channels < 1 || p->channels > 2) 759 return EINVAL; 760 } else { 761 switch (p->channels) { 762 case 1: 763 break; 764 case 2: 765 break; 766 case 4: 767 if (!SUPPORTS_4CH(sc->codec_if)) 768 return EINVAL; 769 break; 770 case 6: 771 if (!SUPPORTS_6CH(sc->codec_if)) 772 return EINVAL; 773 break; 774 default: 775 return EINVAL; 776 } 777 } 778 /* If monaural is requested, aurateconv expands a monaural 779 * stream to stereo. */ 780 if (p->channels == 1) 781 p->hw_channels = 2; 782 783 switch (p->encoding) { 784 case AUDIO_ENCODING_SLINEAR_BE: 785 if (p->precision == 16) { 786 p->sw_code = swap_bytes; 787 } else { 788 if (mode == AUMODE_PLAY) 789 p->sw_code = linear8_to_linear16_le; 790 else 791 p->sw_code = linear16_to_linear8_le; 792 } 793 break; 794 795 case AUDIO_ENCODING_SLINEAR_LE: 796 if (p->precision != 16) { 797 if (mode == AUMODE_PLAY) 798 p->sw_code = linear8_to_linear16_le; 799 else 800 p->sw_code = linear16_to_linear8_le; 801 } 802 break; 803 804 case AUDIO_ENCODING_ULINEAR_BE: 805 if (p->precision == 16) { 806 if (mode == AUMODE_PLAY) 807 p->sw_code = 808 swap_bytes_change_sign16_le; 809 else 810 p->sw_code = 811 change_sign16_swap_bytes_le; 812 } else { 813 if (mode == AUMODE_PLAY) 814 p->sw_code = 815 ulinear8_to_slinear16_le; 816 else 817 p->sw_code = 818 slinear16_to_ulinear8_le; 819 } 820 break; 821 822 case AUDIO_ENCODING_ULINEAR_LE: 823 if (p->precision == 16) { 824 p->sw_code = change_sign16_le; 825 } else { 826 if (mode == AUMODE_PLAY) 827 p->sw_code = 828 ulinear8_to_slinear16_le; 829 else 830 p->sw_code = 831 slinear16_to_ulinear8_le; 832 } 833 break; 834 835 case AUDIO_ENCODING_ULAW: 836 if (mode == AUMODE_PLAY) { 837 p->sw_code = mulaw_to_slinear16_le; 838 } else { 839 p->sw_code = slinear16_to_mulaw_le; 840 } 841 break; 842 843 case AUDIO_ENCODING_ALAW: 844 if (mode == AUMODE_PLAY) { 845 p->sw_code = alaw_to_slinear16_le; 846 } else { 847 p->sw_code = slinear16_to_alaw_le; 848 } 849 break; 850 851 default: 852 return (EINVAL); 853 } 854 855 if (IS_FIXED_RATE(sc->codec_if)) { 856 p->hw_sample_rate = AC97_SINGLE_RATE; 857 /* If hw_sample_rate is changed, aurateconv works. */ 858 } else { 859 if (auich_set_rate(sc, mode, p->sample_rate)) 860 return EINVAL; 861 } 862 if (mode == AUMODE_PLAY) { 863 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 864 control &= ~ICH_PCM246_MASK; 865 if (p->channels == 4) { 866 control |= ICH_PCM4; 867 } else if (p->channels == 6) { 868 control |= ICH_PCM6; 869 } 870 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 871 } 872 } 873 874 return (0); 875 } 876 877 int 878 auich_round_blocksize(void *v, int blk) 879 { 880 881 return (blk & ~0x3f); /* keep good alignment */ 882 } 883 884 int 885 auich_halt_output(void *v) 886 { 887 struct auich_softc *sc = v; 888 889 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 890 891 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 892 893 return (0); 894 } 895 896 int 897 auich_halt_input(void *v) 898 { 899 struct auich_softc *sc = v; 900 901 DPRINTF(ICH_DEBUG_DMA, 902 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 903 904 /* XXX halt both unless known otherwise */ 905 906 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 907 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 908 909 return (0); 910 } 911 912 int 913 auich_getdev(void *v, struct audio_device *adp) 914 { 915 struct auich_softc *sc = v; 916 917 *adp = sc->sc_audev; 918 return (0); 919 } 920 921 int 922 auich_set_port(void *v, mixer_ctrl_t *cp) 923 { 924 struct auich_softc *sc = v; 925 926 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 927 } 928 929 int 930 auich_get_port(void *v, mixer_ctrl_t *cp) 931 { 932 struct auich_softc *sc = v; 933 934 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 935 } 936 937 int 938 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 939 { 940 struct auich_softc *sc = v; 941 942 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 943 } 944 945 void * 946 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 947 int flags) 948 { 949 struct auich_softc *sc = v; 950 struct auich_dma *p; 951 int error; 952 953 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 954 return (NULL); 955 956 p = malloc(sizeof(*p), pool, flags|M_ZERO); 957 if (p == NULL) 958 return (NULL); 959 960 error = auich_allocmem(sc, size, 0, p); 961 if (error) { 962 free(p, pool); 963 return (NULL); 964 } 965 966 p->next = sc->sc_dmas; 967 sc->sc_dmas = p; 968 969 return (KERNADDR(p)); 970 } 971 972 void 973 auich_freem(void *v, void *ptr, struct malloc_type *pool) 974 { 975 struct auich_softc *sc = v; 976 struct auich_dma *p, **pp; 977 978 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 979 if (KERNADDR(p) == ptr) { 980 auich_freemem(sc, p); 981 *pp = p->next; 982 free(p, pool); 983 return; 984 } 985 } 986 } 987 988 size_t 989 auich_round_buffersize(void *v, int direction, size_t size) 990 { 991 992 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 993 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 994 995 return size; 996 } 997 998 paddr_t 999 auich_mappage(void *v, void *mem, off_t off, int prot) 1000 { 1001 struct auich_softc *sc = v; 1002 struct auich_dma *p; 1003 1004 if (off < 0) 1005 return (-1); 1006 1007 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1008 ; 1009 if (!p) 1010 return (-1); 1011 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1012 off, prot, BUS_DMA_WAITOK)); 1013 } 1014 1015 int 1016 auich_get_props(void *v) 1017 { 1018 struct auich_softc *sc = v; 1019 int props; 1020 1021 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1022 /* 1023 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1024 * rate because of aurateconv. Applications can't know what rate the 1025 * device can process in the case of mmap(). 1026 */ 1027 if (!IS_FIXED_RATE(sc->codec_if)) 1028 props |= AUDIO_PROP_MMAP; 1029 return props; 1030 } 1031 1032 int 1033 auich_intr(void *v) 1034 { 1035 struct auich_softc *sc = v; 1036 int ret = 0, sts, gsts, i, qptr; 1037 1038 #ifdef DIAGNOSTIC 1039 int csts; 1040 #endif 1041 1042 #ifdef DIAGNOSTIC 1043 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1044 if (csts & PCI_STATUS_MASTER_ABORT) { 1045 printf("auich_intr: PCI master abort\n"); 1046 } 1047 #endif 1048 1049 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 1050 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 1051 1052 if (gsts & ICH_POINT) { 1053 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 1054 DPRINTF(ICH_DEBUG_DMA, 1055 ("auich_intr: osts=0x%x\n", sts)); 1056 1057 if (sts & ICH_FIFOE) { 1058 printf("%s: fifo underrun # %u\n", 1059 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1060 } 1061 1062 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1063 if (sts & (ICH_LVBCI | ICH_CELV)) { 1064 struct auich_dmalist *q; 1065 1066 qptr = sc->ptr_pcmo; 1067 1068 while (qptr != i) { 1069 q = &sc->dmalist_pcmo[qptr]; 1070 1071 q->base = sc->pcmo_p; 1072 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1073 DPRINTF(ICH_DEBUG_DMA, 1074 ("auich_intr: %p, %p = %x @ 0x%x\n", 1075 &sc->dmalist_pcmo[i], q, 1076 sc->pcmo_blksize / 2, sc->pcmo_p)); 1077 1078 sc->pcmo_p += sc->pcmo_blksize; 1079 if (sc->pcmo_p >= sc->pcmo_end) 1080 sc->pcmo_p = sc->pcmo_start; 1081 1082 if (++qptr == ICH_DMALIST_MAX) 1083 qptr = 0; 1084 } 1085 1086 sc->ptr_pcmo = qptr; 1087 bus_space_write_1(sc->iot, sc->aud_ioh, 1088 ICH_PCMO + ICH_LVI, 1089 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1090 } 1091 1092 if (sts & ICH_BCIS && sc->sc_pintr) 1093 sc->sc_pintr(sc->sc_parg); 1094 1095 /* int ack */ 1096 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1097 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1098 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1099 ret++; 1100 } 1101 1102 if (gsts & ICH_PIINT) { 1103 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1104 DPRINTF(ICH_DEBUG_DMA, 1105 ("auich_intr: ists=0x%x\n", sts)); 1106 1107 if (sts & ICH_FIFOE) { 1108 printf("%s: fifo overrun # %u\n", 1109 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1110 } 1111 1112 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1113 if (sts & (ICH_LVBCI | ICH_CELV)) { 1114 struct auich_dmalist *q; 1115 1116 qptr = sc->ptr_pcmi; 1117 1118 while (qptr != i) { 1119 q = &sc->dmalist_pcmi[qptr]; 1120 1121 q->base = sc->pcmi_p; 1122 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1123 DPRINTF(ICH_DEBUG_DMA, 1124 ("auich_intr: %p, %p = %x @ 0x%x\n", 1125 &sc->dmalist_pcmi[i], q, 1126 sc->pcmi_blksize / 2, sc->pcmi_p)); 1127 1128 sc->pcmi_p += sc->pcmi_blksize; 1129 if (sc->pcmi_p >= sc->pcmi_end) 1130 sc->pcmi_p = sc->pcmi_start; 1131 1132 if (++qptr == ICH_DMALIST_MAX) 1133 qptr = 0; 1134 } 1135 1136 sc->ptr_pcmi = qptr; 1137 bus_space_write_1(sc->iot, sc->aud_ioh, 1138 ICH_PCMI + ICH_LVI, 1139 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1140 } 1141 1142 if (sts & ICH_BCIS && sc->sc_rintr) 1143 sc->sc_rintr(sc->sc_rarg); 1144 1145 /* int ack */ 1146 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1147 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1148 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1149 ret++; 1150 } 1151 1152 if (gsts & ICH_MIINT) { 1153 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1154 DPRINTF(ICH_DEBUG_DMA, 1155 ("auich_intr: ists=0x%x\n", sts)); 1156 if (sts & ICH_FIFOE) 1157 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1158 1159 /* TODO mic input DMA */ 1160 1161 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1162 } 1163 1164 return ret; 1165 } 1166 1167 int 1168 auich_trigger_output(void *v, void *start, void *end, int blksize, 1169 void (*intr)(void *), void *arg, struct audio_params *param) 1170 { 1171 struct auich_softc *sc = v; 1172 struct auich_dmalist *q; 1173 struct auich_dma *p; 1174 size_t size; 1175 #ifdef DIAGNOSTIC 1176 int csts; 1177 #endif 1178 1179 DPRINTF(ICH_DEBUG_DMA, 1180 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1181 start, end, blksize, intr, arg, param)); 1182 1183 sc->sc_pintr = intr; 1184 sc->sc_parg = arg; 1185 #ifdef DIAGNOSTIC 1186 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1187 if (csts & PCI_STATUS_MASTER_ABORT) { 1188 printf("auich_trigger_output: PCI master abort\n"); 1189 } 1190 #endif 1191 1192 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1193 ; 1194 if (!p) { 1195 printf("auich_trigger_output: bad addr %p\n", start); 1196 return (EINVAL); 1197 } 1198 1199 size = (size_t)((caddr_t)end - (caddr_t)start); 1200 1201 /* 1202 * The logic behind this is: 1203 * setup one buffer to play, then LVI dump out the rest 1204 * to the scatter-gather chain. 1205 */ 1206 sc->pcmo_start = DMAADDR(p); 1207 sc->pcmo_p = sc->pcmo_start + blksize; 1208 sc->pcmo_end = sc->pcmo_start + size; 1209 sc->pcmo_blksize = blksize; 1210 1211 sc->ptr_pcmo = 0; 1212 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1213 q->base = sc->pcmo_start; 1214 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1215 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1216 sc->ptr_pcmo = 0; 1217 1218 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1219 sc->sc_cddma + ICH_PCMO_OFF(0)); 1220 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1221 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1222 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1223 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1224 1225 return (0); 1226 } 1227 1228 int 1229 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1230 void *v; 1231 void *start, *end; 1232 int blksize; 1233 void (*intr)(void *); 1234 void *arg; 1235 struct audio_params *param; 1236 { 1237 struct auich_softc *sc = v; 1238 struct auich_dmalist *q; 1239 struct auich_dma *p; 1240 size_t size; 1241 #ifdef DIAGNOSTIC 1242 int csts; 1243 #endif 1244 1245 DPRINTF(ICH_DEBUG_DMA, 1246 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1247 start, end, blksize, intr, arg, param)); 1248 1249 sc->sc_rintr = intr; 1250 sc->sc_rarg = arg; 1251 1252 #ifdef DIAGNOSTIC 1253 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1254 if (csts & PCI_STATUS_MASTER_ABORT) { 1255 printf("auich_trigger_input: PCI master abort\n"); 1256 } 1257 #endif 1258 1259 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1260 ; 1261 if (!p) { 1262 printf("auich_trigger_input: bad addr %p\n", start); 1263 return (EINVAL); 1264 } 1265 1266 size = (size_t)((caddr_t)end - (caddr_t)start); 1267 1268 /* 1269 * The logic behind this is: 1270 * setup one buffer to play, then LVI dump out the rest 1271 * to the scatter-gather chain. 1272 */ 1273 sc->pcmi_start = DMAADDR(p); 1274 sc->pcmi_p = sc->pcmi_start + blksize; 1275 sc->pcmi_end = sc->pcmi_start + size; 1276 sc->pcmi_blksize = blksize; 1277 1278 sc->ptr_pcmi = 0; 1279 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1280 q->base = sc->pcmi_start; 1281 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1282 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1283 sc->ptr_pcmi = 0; 1284 1285 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1286 sc->sc_cddma + ICH_PCMI_OFF(0)); 1287 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1288 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1289 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1290 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1291 1292 return (0); 1293 } 1294 1295 int 1296 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1297 struct auich_dma *p) 1298 { 1299 int error; 1300 1301 p->size = size; 1302 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1303 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1304 &p->nsegs, BUS_DMA_NOWAIT); 1305 if (error) 1306 return (error); 1307 1308 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1309 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1310 if (error) 1311 goto free; 1312 1313 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1314 0, BUS_DMA_NOWAIT, &p->map); 1315 if (error) 1316 goto unmap; 1317 1318 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1319 BUS_DMA_NOWAIT); 1320 if (error) 1321 goto destroy; 1322 return (0); 1323 1324 destroy: 1325 bus_dmamap_destroy(sc->dmat, p->map); 1326 unmap: 1327 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1328 free: 1329 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1330 return (error); 1331 } 1332 1333 int 1334 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1335 { 1336 1337 bus_dmamap_unload(sc->dmat, p->map); 1338 bus_dmamap_destroy(sc->dmat, p->map); 1339 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1340 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1341 return (0); 1342 } 1343 1344 int 1345 auich_alloc_cdata(struct auich_softc *sc) 1346 { 1347 bus_dma_segment_t seg; 1348 int error, rseg; 1349 1350 /* 1351 * Allocate the control data structure, and create and load the 1352 * DMA map for it. 1353 */ 1354 if ((error = bus_dmamem_alloc(sc->dmat, 1355 sizeof(struct auich_cdata), 1356 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1357 printf("%s: unable to allocate control data, error = %d\n", 1358 sc->sc_dev.dv_xname, error); 1359 goto fail_0; 1360 } 1361 1362 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1363 sizeof(struct auich_cdata), 1364 (caddr_t *) &sc->sc_cdata, 1365 sc->sc_dmamap_flags)) != 0) { 1366 printf("%s: unable to map control data, error = %d\n", 1367 sc->sc_dev.dv_xname, error); 1368 goto fail_1; 1369 } 1370 1371 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1372 sizeof(struct auich_cdata), 0, 0, 1373 &sc->sc_cddmamap)) != 0) { 1374 printf("%s: unable to create control data DMA map, " 1375 "error = %d\n", sc->sc_dev.dv_xname, error); 1376 goto fail_2; 1377 } 1378 1379 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1380 sc->sc_cdata, sizeof(struct auich_cdata), 1381 NULL, 0)) != 0) { 1382 printf("%s: unable tp load control data DMA map, " 1383 "error = %d\n", sc->sc_dev.dv_xname, error); 1384 goto fail_3; 1385 } 1386 1387 return (0); 1388 1389 fail_3: 1390 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1391 fail_2: 1392 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1393 sizeof(struct auich_cdata)); 1394 fail_1: 1395 bus_dmamem_free(sc->dmat, &seg, rseg); 1396 fail_0: 1397 return (error); 1398 } 1399 1400 void 1401 auich_powerhook(int why, void *addr) 1402 { 1403 struct auich_softc *sc = (struct auich_softc *)addr; 1404 1405 switch (why) { 1406 case PWR_SUSPEND: 1407 case PWR_STANDBY: 1408 /* Power down */ 1409 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1410 sc->sc_suspend = why; 1411 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1412 break; 1413 1414 case PWR_RESUME: 1415 /* Wake up */ 1416 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1417 if (sc->sc_suspend == PWR_RESUME) { 1418 printf("%s: resume without suspend.\n", 1419 sc->sc_dev.dv_xname); 1420 sc->sc_suspend = why; 1421 return; 1422 } 1423 sc->sc_suspend = why; 1424 auich_reset_codec(sc); 1425 DELAY(1000); 1426 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1427 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1428 break; 1429 1430 case PWR_SOFTSUSPEND: 1431 case PWR_SOFTSTANDBY: 1432 case PWR_SOFTRESUME: 1433 break; 1434 } 1435 } 1436 1437 1438 /* -------------------------------------------------------------------- */ 1439 /* Calibrate card (some boards are overclocked and need scaling) */ 1440 1441 void 1442 auich_calibrate(struct auich_softc *sc) 1443 { 1444 struct timeval t1, t2; 1445 u_int8_t ociv, nciv; 1446 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1447 void *temp_buffer; 1448 struct auich_dma *p; 1449 1450 /* 1451 * Grab audio from input for fixed interval and compare how 1452 * much we actually get with what we expect. Interval needs 1453 * to be sufficiently short that no interrupts are 1454 * generated. 1455 */ 1456 1457 /* Setup a buffer */ 1458 bytes = 16000; 1459 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1460 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1461 ; 1462 if (p == NULL) { 1463 printf("auich_calibrate: bad address %p\n", temp_buffer); 1464 return; 1465 } 1466 sc->dmalist_pcmi[0].base = DMAADDR(p); 1467 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size); 1468 1469 /* 1470 * our data format is stereo, 16 bit so each sample is 4 bytes. 1471 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1472 * we're going to start recording with interrupts disabled and measure 1473 * the time taken for one block to complete. we know the block size, 1474 * we know the time in microseconds, we calculate the sample rate: 1475 * 1476 * actual_rate [bps] = bytes / (time [s] * 4) 1477 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1478 * actual_rate [Hz] = (bytes * 250000) / time [us] 1479 */ 1480 1481 /* prepare */ 1482 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1483 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1484 sc->sc_cddma + ICH_PCMI_OFF(0)); 1485 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1486 (0 - 1) & ICH_LVI_MASK); 1487 1488 /* start */ 1489 microtime(&t1); 1490 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1491 1492 /* wait */ 1493 do { 1494 microtime(&t2); 1495 if (t2.tv_sec - t1.tv_sec > 1) 1496 break; 1497 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1498 ICH_PCMI + ICH_CIV); 1499 } while (nciv == ociv); 1500 1501 /* stop */ 1502 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1503 1504 /* reset */ 1505 DELAY(100); 1506 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1507 1508 /* turn time delta into us */ 1509 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1510 1511 auich_freem(sc, temp_buffer, M_DEVBUF); 1512 1513 if (nciv == ociv) { 1514 printf("%s: ac97 link rate calibration timed out after %d us\n", 1515 sc->sc_dev.dv_xname, wait_us); 1516 return; 1517 } 1518 1519 actual_48k_rate = (bytes * 250000U) / wait_us; 1520 1521 if (actual_48k_rate <= 48500) 1522 ac97rate = 48000; 1523 else 1524 ac97rate = actual_48k_rate; 1525 1526 printf("%s: measured ac97 link rate at %d Hz", 1527 sc->sc_dev.dv_xname, actual_48k_rate); 1528 if (ac97rate != actual_48k_rate) 1529 printf(", will use %d Hz", ac97rate); 1530 printf("\n"); 1531 1532 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1533 } 1534
Indexes created Thu Oct 23 22:10:10 GMT 2025