auich.c revision 1.45
1 /* $NetBSD: auich.c,v 1.45 2003/10/22 15:57:33 manu Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * 108 * TODO: 109 * - Add support for the dedicated microphone input. 110 * 111 * NOTE: 112 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 113 * It causes PCI master abort and hangups until cold reboot. 114 * http://www.intel.com/design/chipsets/specupdt/245051.htm 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.45 2003/10/22 15:57:33 manu Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/kernel.h> 123 #include <sys/malloc.h> 124 #include <sys/device.h> 125 #include <sys/fcntl.h> 126 #include <sys/proc.h> 127 128 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 129 130 #include <dev/pci/pcidevs.h> 131 #include <dev/pci/pcivar.h> 132 #include <dev/pci/auichreg.h> 133 134 #include <sys/audioio.h> 135 #include <dev/audio_if.h> 136 #include <dev/mulaw.h> 137 #include <dev/auconv.h> 138 139 #include <machine/bus.h> 140 141 #include <dev/ic/ac97reg.h> 142 #include <dev/ic/ac97var.h> 143 144 struct auich_dma { 145 bus_dmamap_t map; 146 caddr_t addr; 147 bus_dma_segment_t segs[1]; 148 int nsegs; 149 size_t size; 150 struct auich_dma *next; 151 }; 152 153 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 154 #define KERNADDR(p) ((void *)((p)->addr)) 155 156 struct auich_cdata { 157 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 158 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 159 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 160 }; 161 162 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 163 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 164 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 165 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 166 167 struct auich_softc { 168 struct device sc_dev; 169 void *sc_ih; 170 171 audio_device_t sc_audev; 172 173 bus_space_tag_t iot; 174 bus_space_handle_t mix_ioh; 175 bus_space_handle_t aud_ioh; 176 bus_dma_tag_t dmat; 177 178 struct ac97_codec_if *codec_if; 179 struct ac97_host_if host_if; 180 181 /* DMA scatter-gather lists. */ 182 bus_dmamap_t sc_cddmamap; 183 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 184 185 struct auich_cdata *sc_cdata; 186 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 187 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 188 #define dmalist_mici sc_cdata->ic_dmalist_mici 189 190 int ptr_pcmo, 191 ptr_pcmi, 192 ptr_mici; 193 194 /* i/o buffer pointers */ 195 u_int32_t pcmo_start, pcmo_p, pcmo_end; 196 int pcmo_blksize, pcmo_fifoe; 197 198 u_int32_t pcmi_start, pcmi_p, pcmi_end; 199 int pcmi_blksize, pcmi_fifoe; 200 201 u_int32_t mici_start, mici_p, mici_end; 202 int mici_blksize, mici_fifoe; 203 204 struct auich_dma *sc_dmas; 205 206 #ifdef DIAGNOSTIC 207 pci_chipset_tag_t sc_pc; 208 pcitag_t sc_pt; 209 #endif 210 int sc_ignore_codecready; 211 /* SiS 7012 hack */ 212 int sc_sample_size; 213 int sc_sts_reg; 214 /* 440MX workaround */ 215 int sc_dmamap_flags; 216 217 void (*sc_pintr)(void *); 218 void *sc_parg; 219 220 void (*sc_rintr)(void *); 221 void *sc_rarg; 222 223 /* Power Management */ 224 void *sc_powerhook; 225 int sc_suspend; 226 u_int16_t ext_status; 227 }; 228 229 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 230 & AC97_EXT_AUDIO_VRA) 231 #define SUPPORTS_4CH(codec) ((codec)->vtbl->get_extcaps(codec) \ 232 & AC97_EXT_AUDIO_SDAC) 233 #define AC97_6CH_DACS (AC97_EXT_AUDIO_SDAC | AC97_EXT_AUDIO_CDAC \ 234 | AC97_EXT_AUDIO_LDAC) 235 #define SUPPORTS_6CH(codec) (((codec)->vtbl->get_extcaps(codec) \ 236 & AC97_6CH_DACS) == AC97_6CH_DACS) 237 238 /* Debug */ 239 #ifdef AUDIO_DEBUG 240 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 241 int auich_debug = 0xfffe; 242 #define ICH_DEBUG_CODECIO 0x0001 243 #define ICH_DEBUG_DMA 0x0002 244 #define ICH_DEBUG_PARAM 0x0004 245 #else 246 #define DPRINTF(x,y) /* nothing */ 247 #endif 248 249 int auich_match(struct device *, struct cfdata *, void *); 250 void auich_attach(struct device *, struct device *, void *); 251 int auich_intr(void *); 252 253 CFATTACH_DECL(auich, sizeof(struct auich_softc), 254 auich_match, auich_attach, NULL, NULL); 255 256 int auich_open(void *, int); 257 void auich_close(void *); 258 int auich_query_encoding(void *, struct audio_encoding *); 259 int auich_set_params(void *, int, int, struct audio_params *, 260 struct audio_params *); 261 int auich_round_blocksize(void *, int); 262 int auich_halt_output(void *); 263 int auich_halt_input(void *); 264 int auich_getdev(void *, struct audio_device *); 265 int auich_set_port(void *, mixer_ctrl_t *); 266 int auich_get_port(void *, mixer_ctrl_t *); 267 int auich_query_devinfo(void *, mixer_devinfo_t *); 268 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 269 void auich_freem(void *, void *, struct malloc_type *); 270 size_t auich_round_buffersize(void *, int, size_t); 271 paddr_t auich_mappage(void *, void *, off_t, int); 272 int auich_get_props(void *); 273 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 274 void *, struct audio_params *); 275 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 276 void *, struct audio_params *); 277 278 int auich_alloc_cdata(struct auich_softc *); 279 280 int auich_allocmem(struct auich_softc *, size_t, size_t, 281 struct auich_dma *); 282 int auich_freemem(struct auich_softc *, struct auich_dma *); 283 284 void auich_powerhook(int, void *); 285 int auich_set_rate(struct auich_softc *, int, u_long); 286 void auich_finish_attach(struct device *); 287 void auich_calibrate(struct auich_softc *); 288 289 290 struct audio_hw_if auich_hw_if = { 291 auich_open, 292 auich_close, 293 NULL, /* drain */ 294 auich_query_encoding, 295 auich_set_params, 296 auich_round_blocksize, 297 NULL, /* commit_setting */ 298 NULL, /* init_output */ 299 NULL, /* init_input */ 300 NULL, /* start_output */ 301 NULL, /* start_input */ 302 auich_halt_output, 303 auich_halt_input, 304 NULL, /* speaker_ctl */ 305 auich_getdev, 306 NULL, /* getfd */ 307 auich_set_port, 308 auich_get_port, 309 auich_query_devinfo, 310 auich_allocm, 311 auich_freem, 312 auich_round_buffersize, 313 auich_mappage, 314 auich_get_props, 315 auich_trigger_output, 316 auich_trigger_input, 317 NULL, /* dev_ioctl */ 318 }; 319 320 int auich_attach_codec(void *, struct ac97_codec_if *); 321 int auich_read_codec(void *, u_int8_t, u_int16_t *); 322 int auich_write_codec(void *, u_int8_t, u_int16_t); 323 void auich_reset_codec(void *); 324 325 static const struct auich_devtype { 326 int vendor; 327 int product; 328 const char *name; 329 const char *shortname; 330 int quirks; 331 #define QUIRK_IGNORE_CODEC_READY 0x01 332 #define QUIRK_IGNORE_CODEC_READY_MAYBE 0x02 333 } auich_devices[] = { 334 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 335 "i82801AA (ICH) AC-97 Audio", "ICH" }, 336 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 337 "i82801AB (ICH0) AC-97 Audio", "ICH0", 338 QUIRK_IGNORE_CODEC_READY_MAYBE }, 339 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 340 "i82801BA (ICH2) AC-97 Audio", "ICH2", 341 QUIRK_IGNORE_CODEC_READY_MAYBE }, 342 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 343 "i82440MX AC-97 Audio", "440MX" }, 344 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 345 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 346 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 347 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4", 348 QUIRK_IGNORE_CODEC_READY_MAYBE }, 349 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 350 "i82801EB (ICH5) AC-97 Audio", "ICH5", 351 QUIRK_IGNORE_CODEC_READY }, 352 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 353 "SiS 7012 AC-97 Audio", "SiS7012" }, 354 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 355 "nForce MCP AC-97 Audio", "nForce-MCP", 356 QUIRK_IGNORE_CODEC_READY }, 357 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 358 "nForce2 MCP-T AC-97 Audio", "nForce-MCP-T" }, 359 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 360 "nForce3 MCP-T AC-97 Audio", "nForce-MCP-T" }, 361 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 362 "AMD768 AC-97 Audio", "AMD768" }, 363 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 364 "AMD8111 AC-97 Audio", "AMD8111" }, 365 { 0, 0, 366 NULL, NULL }, 367 }; 368 369 static const struct auich_devtype * 370 auich_lookup(struct pci_attach_args *pa) 371 { 372 const struct auich_devtype *d; 373 374 for (d = auich_devices; d->name != NULL; d++) { 375 if (PCI_VENDOR(pa->pa_id) == d->vendor 376 && PCI_PRODUCT(pa->pa_id) == d->product) 377 return (d); 378 } 379 380 return (NULL); 381 } 382 383 int 384 auich_match(struct device *parent, struct cfdata *match, void *aux) 385 { 386 struct pci_attach_args *pa = aux; 387 388 if (auich_lookup(pa) != NULL) 389 return (1); 390 391 return (0); 392 } 393 394 void 395 auich_attach(struct device *parent, struct device *self, void *aux) 396 { 397 struct auich_softc *sc = (struct auich_softc *)self; 398 struct pci_attach_args *pa = aux; 399 pci_intr_handle_t ih; 400 bus_size_t mix_size, aud_size; 401 pcireg_t csr; 402 const char *intrstr; 403 const struct auich_devtype *d; 404 u_int32_t status; 405 406 aprint_naive(": Audio controller\n"); 407 408 d = auich_lookup(pa); 409 if (d == NULL) 410 panic("auich_attach: impossible"); 411 412 #ifdef DIAGNOSTIC 413 sc->sc_pc = pa->pa_pc; 414 sc->sc_pt = pa->pa_tag; 415 #endif 416 417 aprint_normal(": %s\n", d->name); 418 419 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 420 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 421 aprint_error("%s: can't map codec i/o space\n", 422 sc->sc_dev.dv_xname); 423 return; 424 } 425 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 426 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 427 aprint_error("%s: can't map device i/o space\n", 428 sc->sc_dev.dv_xname); 429 return; 430 } 431 sc->dmat = pa->pa_dmat; 432 433 /* enable bus mastering */ 434 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 435 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 436 csr | PCI_COMMAND_MASTER_ENABLE); 437 438 /* Map and establish the interrupt. */ 439 if (pci_intr_map(pa, &ih)) { 440 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 441 return; 442 } 443 intrstr = pci_intr_string(pa->pa_pc, ih); 444 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 445 auich_intr, sc); 446 if (sc->sc_ih == NULL) { 447 aprint_error("%s: can't establish interrupt", 448 sc->sc_dev.dv_xname); 449 if (intrstr != NULL) 450 aprint_normal(" at %s", intrstr); 451 aprint_normal("\n"); 452 return; 453 } 454 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 455 456 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 457 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 458 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 459 460 /* SiS 7012 needs special handling */ 461 if (d->vendor == PCI_VENDOR_SIS 462 && d->product == PCI_PRODUCT_SIS_7012_AC) { 463 sc->sc_sts_reg = ICH_PICB; 464 sc->sc_sample_size = 1; 465 } else { 466 sc->sc_sts_reg = ICH_STS; 467 sc->sc_sample_size = 2; 468 } 469 470 if (d->quirks & QUIRK_IGNORE_CODEC_READY) { 471 sc->sc_ignore_codecready = TRUE; 472 } 473 474 /* Workaround for a 440MX B-stepping erratum */ 475 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 476 if (d->vendor == PCI_VENDOR_INTEL 477 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 478 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 479 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 480 } 481 482 /* Set up DMA lists. */ 483 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 484 auich_alloc_cdata(sc); 485 486 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 487 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 488 489 /* Reset codec and AC'97 */ 490 auich_reset_codec(sc); 491 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 492 493 /* Reset failure */ 494 if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) { 495 /* It never return ICH_PCR in some cases */ 496 if (d->quirks & QUIRK_IGNORE_CODEC_READY_MAYBE) { 497 sc->sc_ignore_codecready = TRUE; 498 } else { 499 return; 500 } 501 } 502 503 sc->host_if.arg = sc; 504 sc->host_if.attach = auich_attach_codec; 505 sc->host_if.read = auich_read_codec; 506 sc->host_if.write = auich_write_codec; 507 sc->host_if.reset = auich_reset_codec; 508 509 if (ac97_attach(&sc->host_if) != 0) 510 return; 511 512 /* Watch for power change */ 513 sc->sc_suspend = PWR_RESUME; 514 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 515 516 config_interrupts(self, auich_finish_attach); 517 } 518 519 void 520 auich_finish_attach(struct device *self) 521 { 522 struct auich_softc *sc = (void *)self; 523 524 if (!IS_FIXED_RATE(sc->codec_if)) 525 auich_calibrate(sc); 526 527 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 528 } 529 530 #define ICH_CODECIO_INTERVAL 10 531 int 532 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 533 { 534 struct auich_softc *sc = v; 535 int i; 536 uint32_t status; 537 538 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 539 if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) { 540 printf("auich_read_codec: codec is not ready (0x%x)\n", status); 541 *val = 0xffff; 542 return -1; 543 } 544 /* wait for an access semaphore */ 545 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 546 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 547 DELAY(ICH_CODECIO_INTERVAL)); 548 549 if (i > 0) { 550 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 551 DPRINTF(ICH_DEBUG_CODECIO, 552 ("auich_read_codec(%x, %x)\n", reg, *val)); 553 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 554 if (status & ICH_RCS) { 555 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 556 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 557 *val = 0xffff; 558 } 559 return 0; 560 } else { 561 DPRINTF(ICH_DEBUG_CODECIO, 562 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 563 return -1; 564 } 565 } 566 567 int 568 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 569 { 570 struct auich_softc *sc = v; 571 int i; 572 573 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 574 if (!sc->sc_ignore_codecready 575 && !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) { 576 printf("auich_write_codec: codec is not ready."); 577 return -1; 578 } 579 /* wait for an access semaphore */ 580 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 581 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 582 DELAY(ICH_CODECIO_INTERVAL)); 583 584 if (i > 0) { 585 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 586 return 0; 587 } else { 588 DPRINTF(ICH_DEBUG_CODECIO, 589 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 590 return -1; 591 } 592 } 593 594 int 595 auich_attach_codec(void *v, struct ac97_codec_if *cif) 596 { 597 struct auich_softc *sc = v; 598 599 sc->codec_if = cif; 600 return 0; 601 } 602 603 void 604 auich_reset_codec(void *v) 605 { 606 struct auich_softc *sc = v; 607 int i; 608 uint32_t control; 609 610 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 611 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 612 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 613 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 614 615 for (i = 500000; i-- && 616 !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR); 617 DELAY(1)); /* or ICH_SCR? */ 618 if (!sc->sc_ignore_codecready && (i <= 0)) 619 printf("%s: auich_reset_codec: time out\n", 620 sc->sc_dev.dv_xname); 621 } 622 623 int 624 auich_open(void *v, int flags) 625 { 626 return 0; 627 } 628 629 void 630 auich_close(void *v) 631 { 632 struct auich_softc *sc = v; 633 634 auich_halt_output(sc); 635 auich_halt_input(sc); 636 637 sc->sc_pintr = NULL; 638 sc->sc_rintr = NULL; 639 } 640 641 int 642 auich_query_encoding(void *v, struct audio_encoding *aep) 643 { 644 645 switch (aep->index) { 646 case 0: 647 strcpy(aep->name, AudioEulinear); 648 aep->encoding = AUDIO_ENCODING_ULINEAR; 649 aep->precision = 8; 650 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 651 return (0); 652 case 1: 653 strcpy(aep->name, AudioEmulaw); 654 aep->encoding = AUDIO_ENCODING_ULAW; 655 aep->precision = 8; 656 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 657 return (0); 658 case 2: 659 strcpy(aep->name, AudioEalaw); 660 aep->encoding = AUDIO_ENCODING_ALAW; 661 aep->precision = 8; 662 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 663 return (0); 664 case 3: 665 strcpy(aep->name, AudioEslinear); 666 aep->encoding = AUDIO_ENCODING_SLINEAR; 667 aep->precision = 8; 668 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 669 return (0); 670 case 4: 671 strcpy(aep->name, AudioEslinear_le); 672 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 673 aep->precision = 16; 674 aep->flags = 0; 675 return (0); 676 case 5: 677 strcpy(aep->name, AudioEulinear_le); 678 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 679 aep->precision = 16; 680 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 681 return (0); 682 case 6: 683 strcpy(aep->name, AudioEslinear_be); 684 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 685 aep->precision = 16; 686 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 687 return (0); 688 case 7: 689 strcpy(aep->name, AudioEulinear_be); 690 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 691 aep->precision = 16; 692 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 693 return (0); 694 default: 695 return (EINVAL); 696 } 697 } 698 699 int 700 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 701 { 702 int ret; 703 u_long ratetmp; 704 705 ratetmp = srate; 706 if (mode == AUMODE_RECORD) 707 return sc->codec_if->vtbl->set_rate(sc->codec_if, 708 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 709 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 710 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 711 if (ret) 712 return ret; 713 ratetmp = srate; 714 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 715 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 716 if (ret) 717 return ret; 718 ratetmp = srate; 719 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 720 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 721 return ret; 722 } 723 724 int 725 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 726 struct audio_params *rec) 727 { 728 struct auich_softc *sc = v; 729 struct audio_params *p; 730 int mode; 731 u_int32_t control; 732 733 for (mode = AUMODE_RECORD; mode != -1; 734 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 735 if ((setmode & mode) == 0) 736 continue; 737 738 p = mode == AUMODE_PLAY ? play : rec; 739 if (p == NULL) 740 continue; 741 742 if ((p->sample_rate != 8000) && 743 (p->sample_rate != 11025) && 744 (p->sample_rate != 12000) && 745 (p->sample_rate != 16000) && 746 (p->sample_rate != 22050) && 747 (p->sample_rate != 24000) && 748 (p->sample_rate != 32000) && 749 (p->sample_rate != 44100) && 750 (p->sample_rate != 48000)) 751 return (EINVAL); 752 753 p->factor = 1; 754 if (p->precision == 8) 755 p->factor *= 2; 756 757 p->sw_code = NULL; 758 /* setup hardware formats */ 759 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 760 p->hw_precision = 16; 761 762 if (mode == AUMODE_RECORD) { 763 if (p->channels < 1 || p->channels > 2) 764 return EINVAL; 765 } else { 766 switch (p->channels) { 767 case 1: 768 break; 769 case 2: 770 break; 771 case 4: 772 if (!SUPPORTS_4CH(sc->codec_if)) 773 return EINVAL; 774 break; 775 case 6: 776 if (!SUPPORTS_6CH(sc->codec_if)) 777 return EINVAL; 778 break; 779 default: 780 return EINVAL; 781 } 782 } 783 /* If monaural is requested, aurateconv expands a monaural 784 * stream to stereo. */ 785 if (p->channels == 1) 786 p->hw_channels = 2; 787 788 switch (p->encoding) { 789 case AUDIO_ENCODING_SLINEAR_BE: 790 if (p->precision == 16) { 791 p->sw_code = swap_bytes; 792 } else { 793 if (mode == AUMODE_PLAY) 794 p->sw_code = linear8_to_linear16_le; 795 else 796 p->sw_code = linear16_to_linear8_le; 797 } 798 break; 799 800 case AUDIO_ENCODING_SLINEAR_LE: 801 if (p->precision != 16) { 802 if (mode == AUMODE_PLAY) 803 p->sw_code = linear8_to_linear16_le; 804 else 805 p->sw_code = linear16_to_linear8_le; 806 } 807 break; 808 809 case AUDIO_ENCODING_ULINEAR_BE: 810 if (p->precision == 16) { 811 if (mode == AUMODE_PLAY) 812 p->sw_code = 813 swap_bytes_change_sign16_le; 814 else 815 p->sw_code = 816 change_sign16_swap_bytes_le; 817 } else { 818 if (mode == AUMODE_PLAY) 819 p->sw_code = 820 ulinear8_to_slinear16_le; 821 else 822 p->sw_code = 823 slinear16_to_ulinear8_le; 824 } 825 break; 826 827 case AUDIO_ENCODING_ULINEAR_LE: 828 if (p->precision == 16) { 829 p->sw_code = change_sign16_le; 830 } else { 831 if (mode == AUMODE_PLAY) 832 p->sw_code = 833 ulinear8_to_slinear16_le; 834 else 835 p->sw_code = 836 slinear16_to_ulinear8_le; 837 } 838 break; 839 840 case AUDIO_ENCODING_ULAW: 841 if (mode == AUMODE_PLAY) { 842 p->sw_code = mulaw_to_slinear16_le; 843 } else { 844 p->sw_code = slinear16_to_mulaw_le; 845 } 846 break; 847 848 case AUDIO_ENCODING_ALAW: 849 if (mode == AUMODE_PLAY) { 850 p->sw_code = alaw_to_slinear16_le; 851 } else { 852 p->sw_code = slinear16_to_alaw_le; 853 } 854 break; 855 856 default: 857 return (EINVAL); 858 } 859 860 if (IS_FIXED_RATE(sc->codec_if)) { 861 p->hw_sample_rate = AC97_SINGLE_RATE; 862 /* If hw_sample_rate is changed, aurateconv works. */ 863 } else { 864 if (auich_set_rate(sc, mode, p->sample_rate)) 865 return EINVAL; 866 } 867 if (mode == AUMODE_PLAY) { 868 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 869 control &= ~ICH_PCM246_MASK; 870 if (p->channels == 4) { 871 control |= ICH_PCM4; 872 } else if (p->channels == 6) { 873 control |= ICH_PCM6; 874 } 875 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 876 } 877 } 878 879 return (0); 880 } 881 882 int 883 auich_round_blocksize(void *v, int blk) 884 { 885 886 return (blk & ~0x3f); /* keep good alignment */ 887 } 888 889 int 890 auich_halt_output(void *v) 891 { 892 struct auich_softc *sc = v; 893 894 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 895 896 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 897 898 return (0); 899 } 900 901 int 902 auich_halt_input(void *v) 903 { 904 struct auich_softc *sc = v; 905 906 DPRINTF(ICH_DEBUG_DMA, 907 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 908 909 /* XXX halt both unless known otherwise */ 910 911 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 912 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 913 914 return (0); 915 } 916 917 int 918 auich_getdev(void *v, struct audio_device *adp) 919 { 920 struct auich_softc *sc = v; 921 922 *adp = sc->sc_audev; 923 return (0); 924 } 925 926 int 927 auich_set_port(void *v, mixer_ctrl_t *cp) 928 { 929 struct auich_softc *sc = v; 930 931 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 932 } 933 934 int 935 auich_get_port(void *v, mixer_ctrl_t *cp) 936 { 937 struct auich_softc *sc = v; 938 939 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 940 } 941 942 int 943 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 944 { 945 struct auich_softc *sc = v; 946 947 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 948 } 949 950 void * 951 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 952 int flags) 953 { 954 struct auich_softc *sc = v; 955 struct auich_dma *p; 956 int error; 957 958 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 959 return (NULL); 960 961 p = malloc(sizeof(*p), pool, flags|M_ZERO); 962 if (p == NULL) 963 return (NULL); 964 965 error = auich_allocmem(sc, size, 0, p); 966 if (error) { 967 free(p, pool); 968 return (NULL); 969 } 970 971 p->next = sc->sc_dmas; 972 sc->sc_dmas = p; 973 974 return (KERNADDR(p)); 975 } 976 977 void 978 auich_freem(void *v, void *ptr, struct malloc_type *pool) 979 { 980 struct auich_softc *sc = v; 981 struct auich_dma *p, **pp; 982 983 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 984 if (KERNADDR(p) == ptr) { 985 auich_freemem(sc, p); 986 *pp = p->next; 987 free(p, pool); 988 return; 989 } 990 } 991 } 992 993 size_t 994 auich_round_buffersize(void *v, int direction, size_t size) 995 { 996 997 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 998 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 999 1000 return size; 1001 } 1002 1003 paddr_t 1004 auich_mappage(void *v, void *mem, off_t off, int prot) 1005 { 1006 struct auich_softc *sc = v; 1007 struct auich_dma *p; 1008 1009 if (off < 0) 1010 return (-1); 1011 1012 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1013 ; 1014 if (!p) 1015 return (-1); 1016 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1017 off, prot, BUS_DMA_WAITOK)); 1018 } 1019 1020 int 1021 auich_get_props(void *v) 1022 { 1023 struct auich_softc *sc = v; 1024 int props; 1025 1026 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1027 /* 1028 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1029 * rate because of aurateconv. Applications can't know what rate the 1030 * device can process in the case of mmap(). 1031 */ 1032 if (!IS_FIXED_RATE(sc->codec_if)) 1033 props |= AUDIO_PROP_MMAP; 1034 return props; 1035 } 1036 1037 int 1038 auich_intr(void *v) 1039 { 1040 struct auich_softc *sc = v; 1041 int ret = 0, sts, gsts, i, qptr; 1042 1043 #ifdef DIAGNOSTIC 1044 int csts; 1045 #endif 1046 1047 #ifdef DIAGNOSTIC 1048 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1049 if (csts & PCI_STATUS_MASTER_ABORT) { 1050 printf("auich_intr: PCI master abort\n"); 1051 } 1052 #endif 1053 1054 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 1055 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 1056 1057 if (gsts & ICH_POINT) { 1058 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 1059 DPRINTF(ICH_DEBUG_DMA, 1060 ("auich_intr: osts=0x%x\n", sts)); 1061 1062 if (sts & ICH_FIFOE) { 1063 printf("%s: fifo underrun # %u\n", 1064 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1065 } 1066 1067 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1068 if (sts & (ICH_LVBCI | ICH_CELV)) { 1069 struct auich_dmalist *q; 1070 1071 qptr = sc->ptr_pcmo; 1072 1073 while (qptr != i) { 1074 q = &sc->dmalist_pcmo[qptr]; 1075 1076 q->base = sc->pcmo_p; 1077 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1078 DPRINTF(ICH_DEBUG_DMA, 1079 ("auich_intr: %p, %p = %x @ 0x%x\n", 1080 &sc->dmalist_pcmo[i], q, 1081 sc->pcmo_blksize / 2, sc->pcmo_p)); 1082 1083 sc->pcmo_p += sc->pcmo_blksize; 1084 if (sc->pcmo_p >= sc->pcmo_end) 1085 sc->pcmo_p = sc->pcmo_start; 1086 1087 if (++qptr == ICH_DMALIST_MAX) 1088 qptr = 0; 1089 } 1090 1091 sc->ptr_pcmo = qptr; 1092 bus_space_write_1(sc->iot, sc->aud_ioh, 1093 ICH_PCMO + ICH_LVI, 1094 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1095 } 1096 1097 if (sts & ICH_BCIS && sc->sc_pintr) 1098 sc->sc_pintr(sc->sc_parg); 1099 1100 /* int ack */ 1101 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1102 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1103 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1104 ret++; 1105 } 1106 1107 if (gsts & ICH_PIINT) { 1108 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1109 DPRINTF(ICH_DEBUG_DMA, 1110 ("auich_intr: ists=0x%x\n", sts)); 1111 1112 if (sts & ICH_FIFOE) { 1113 printf("%s: fifo overrun # %u\n", 1114 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1115 } 1116 1117 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1118 if (sts & (ICH_LVBCI | ICH_CELV)) { 1119 struct auich_dmalist *q; 1120 1121 qptr = sc->ptr_pcmi; 1122 1123 while (qptr != i) { 1124 q = &sc->dmalist_pcmi[qptr]; 1125 1126 q->base = sc->pcmi_p; 1127 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1128 DPRINTF(ICH_DEBUG_DMA, 1129 ("auich_intr: %p, %p = %x @ 0x%x\n", 1130 &sc->dmalist_pcmi[i], q, 1131 sc->pcmi_blksize / 2, sc->pcmi_p)); 1132 1133 sc->pcmi_p += sc->pcmi_blksize; 1134 if (sc->pcmi_p >= sc->pcmi_end) 1135 sc->pcmi_p = sc->pcmi_start; 1136 1137 if (++qptr == ICH_DMALIST_MAX) 1138 qptr = 0; 1139 } 1140 1141 sc->ptr_pcmi = qptr; 1142 bus_space_write_1(sc->iot, sc->aud_ioh, 1143 ICH_PCMI + ICH_LVI, 1144 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1145 } 1146 1147 if (sts & ICH_BCIS && sc->sc_rintr) 1148 sc->sc_rintr(sc->sc_rarg); 1149 1150 /* int ack */ 1151 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1152 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1153 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1154 ret++; 1155 } 1156 1157 if (gsts & ICH_MIINT) { 1158 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1159 DPRINTF(ICH_DEBUG_DMA, 1160 ("auich_intr: ists=0x%x\n", sts)); 1161 if (sts & ICH_FIFOE) 1162 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1163 1164 /* TODO mic input DMA */ 1165 1166 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1167 } 1168 1169 return ret; 1170 } 1171 1172 int 1173 auich_trigger_output(void *v, void *start, void *end, int blksize, 1174 void (*intr)(void *), void *arg, struct audio_params *param) 1175 { 1176 struct auich_softc *sc = v; 1177 struct auich_dmalist *q; 1178 struct auich_dma *p; 1179 size_t size; 1180 #ifdef DIAGNOSTIC 1181 int csts; 1182 #endif 1183 1184 DPRINTF(ICH_DEBUG_DMA, 1185 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1186 start, end, blksize, intr, arg, param)); 1187 1188 sc->sc_pintr = intr; 1189 sc->sc_parg = arg; 1190 #ifdef DIAGNOSTIC 1191 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1192 if (csts & PCI_STATUS_MASTER_ABORT) { 1193 printf("auich_trigger_output: PCI master abort\n"); 1194 } 1195 #endif 1196 1197 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1198 ; 1199 if (!p) { 1200 printf("auich_trigger_output: bad addr %p\n", start); 1201 return (EINVAL); 1202 } 1203 1204 size = (size_t)((caddr_t)end - (caddr_t)start); 1205 1206 /* 1207 * The logic behind this is: 1208 * setup one buffer to play, then LVI dump out the rest 1209 * to the scatter-gather chain. 1210 */ 1211 sc->pcmo_start = DMAADDR(p); 1212 sc->pcmo_p = sc->pcmo_start + blksize; 1213 sc->pcmo_end = sc->pcmo_start + size; 1214 sc->pcmo_blksize = blksize; 1215 1216 sc->ptr_pcmo = 0; 1217 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1218 q->base = sc->pcmo_start; 1219 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1220 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1221 sc->ptr_pcmo = 0; 1222 1223 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1224 sc->sc_cddma + ICH_PCMO_OFF(0)); 1225 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1226 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1227 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1228 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1229 1230 return (0); 1231 } 1232 1233 int 1234 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1235 void *v; 1236 void *start, *end; 1237 int blksize; 1238 void (*intr)(void *); 1239 void *arg; 1240 struct audio_params *param; 1241 { 1242 struct auich_softc *sc = v; 1243 struct auich_dmalist *q; 1244 struct auich_dma *p; 1245 size_t size; 1246 #ifdef DIAGNOSTIC 1247 int csts; 1248 #endif 1249 1250 DPRINTF(ICH_DEBUG_DMA, 1251 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1252 start, end, blksize, intr, arg, param)); 1253 1254 sc->sc_rintr = intr; 1255 sc->sc_rarg = arg; 1256 1257 #ifdef DIAGNOSTIC 1258 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1259 if (csts & PCI_STATUS_MASTER_ABORT) { 1260 printf("auich_trigger_input: PCI master abort\n"); 1261 } 1262 #endif 1263 1264 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1265 ; 1266 if (!p) { 1267 printf("auich_trigger_input: bad addr %p\n", start); 1268 return (EINVAL); 1269 } 1270 1271 size = (size_t)((caddr_t)end - (caddr_t)start); 1272 1273 /* 1274 * The logic behind this is: 1275 * setup one buffer to play, then LVI dump out the rest 1276 * to the scatter-gather chain. 1277 */ 1278 sc->pcmi_start = DMAADDR(p); 1279 sc->pcmi_p = sc->pcmi_start + blksize; 1280 sc->pcmi_end = sc->pcmi_start + size; 1281 sc->pcmi_blksize = blksize; 1282 1283 sc->ptr_pcmi = 0; 1284 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1285 q->base = sc->pcmi_start; 1286 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1287 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1288 sc->ptr_pcmi = 0; 1289 1290 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1291 sc->sc_cddma + ICH_PCMI_OFF(0)); 1292 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1293 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1294 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1295 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1296 1297 return (0); 1298 } 1299 1300 int 1301 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1302 struct auich_dma *p) 1303 { 1304 int error; 1305 1306 p->size = size; 1307 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1308 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1309 &p->nsegs, BUS_DMA_NOWAIT); 1310 if (error) 1311 return (error); 1312 1313 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1314 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1315 if (error) 1316 goto free; 1317 1318 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1319 0, BUS_DMA_NOWAIT, &p->map); 1320 if (error) 1321 goto unmap; 1322 1323 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1324 BUS_DMA_NOWAIT); 1325 if (error) 1326 goto destroy; 1327 return (0); 1328 1329 destroy: 1330 bus_dmamap_destroy(sc->dmat, p->map); 1331 unmap: 1332 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1333 free: 1334 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1335 return (error); 1336 } 1337 1338 int 1339 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1340 { 1341 1342 bus_dmamap_unload(sc->dmat, p->map); 1343 bus_dmamap_destroy(sc->dmat, p->map); 1344 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1345 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1346 return (0); 1347 } 1348 1349 int 1350 auich_alloc_cdata(struct auich_softc *sc) 1351 { 1352 bus_dma_segment_t seg; 1353 int error, rseg; 1354 1355 /* 1356 * Allocate the control data structure, and create and load the 1357 * DMA map for it. 1358 */ 1359 if ((error = bus_dmamem_alloc(sc->dmat, 1360 sizeof(struct auich_cdata), 1361 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1362 printf("%s: unable to allocate control data, error = %d\n", 1363 sc->sc_dev.dv_xname, error); 1364 goto fail_0; 1365 } 1366 1367 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1368 sizeof(struct auich_cdata), 1369 (caddr_t *) &sc->sc_cdata, 1370 sc->sc_dmamap_flags)) != 0) { 1371 printf("%s: unable to map control data, error = %d\n", 1372 sc->sc_dev.dv_xname, error); 1373 goto fail_1; 1374 } 1375 1376 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1377 sizeof(struct auich_cdata), 0, 0, 1378 &sc->sc_cddmamap)) != 0) { 1379 printf("%s: unable to create control data DMA map, " 1380 "error = %d\n", sc->sc_dev.dv_xname, error); 1381 goto fail_2; 1382 } 1383 1384 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1385 sc->sc_cdata, sizeof(struct auich_cdata), 1386 NULL, 0)) != 0) { 1387 printf("%s: unable tp load control data DMA map, " 1388 "error = %d\n", sc->sc_dev.dv_xname, error); 1389 goto fail_3; 1390 } 1391 1392 return (0); 1393 1394 fail_3: 1395 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1396 fail_2: 1397 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1398 sizeof(struct auich_cdata)); 1399 fail_1: 1400 bus_dmamem_free(sc->dmat, &seg, rseg); 1401 fail_0: 1402 return (error); 1403 } 1404 1405 void 1406 auich_powerhook(int why, void *addr) 1407 { 1408 struct auich_softc *sc = (struct auich_softc *)addr; 1409 1410 switch (why) { 1411 case PWR_SUSPEND: 1412 case PWR_STANDBY: 1413 /* Power down */ 1414 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1415 sc->sc_suspend = why; 1416 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1417 break; 1418 1419 case PWR_RESUME: 1420 /* Wake up */ 1421 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1422 if (sc->sc_suspend == PWR_RESUME) { 1423 printf("%s: resume without suspend.\n", 1424 sc->sc_dev.dv_xname); 1425 sc->sc_suspend = why; 1426 return; 1427 } 1428 sc->sc_suspend = why; 1429 auich_reset_codec(sc); 1430 DELAY(1000); 1431 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1432 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1433 break; 1434 1435 case PWR_SOFTSUSPEND: 1436 case PWR_SOFTSTANDBY: 1437 case PWR_SOFTRESUME: 1438 break; 1439 } 1440 } 1441 1442 1443 /* -------------------------------------------------------------------- */ 1444 /* Calibrate card (some boards are overclocked and need scaling) */ 1445 1446 void 1447 auich_calibrate(struct auich_softc *sc) 1448 { 1449 struct timeval t1, t2; 1450 u_int8_t ociv, nciv; 1451 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1452 void *temp_buffer; 1453 struct auich_dma *p; 1454 1455 /* 1456 * Grab audio from input for fixed interval and compare how 1457 * much we actually get with what we expect. Interval needs 1458 * to be sufficiently short that no interrupts are 1459 * generated. 1460 */ 1461 1462 /* Setup a buffer */ 1463 bytes = 16000; 1464 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1465 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1466 ; 1467 if (p == NULL) { 1468 printf("auich_calibrate: bad address %p\n", temp_buffer); 1469 return; 1470 } 1471 sc->dmalist_pcmi[0].base = DMAADDR(p); 1472 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size); 1473 1474 /* 1475 * our data format is stereo, 16 bit so each sample is 4 bytes. 1476 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1477 * we're going to start recording with interrupts disabled and measure 1478 * the time taken for one block to complete. we know the block size, 1479 * we know the time in microseconds, we calculate the sample rate: 1480 * 1481 * actual_rate [bps] = bytes / (time [s] * 4) 1482 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1483 * actual_rate [Hz] = (bytes * 250000) / time [us] 1484 */ 1485 1486 /* prepare */ 1487 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1488 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1489 sc->sc_cddma + ICH_PCMI_OFF(0)); 1490 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1491 (0 - 1) & ICH_LVI_MASK); 1492 1493 /* start */ 1494 microtime(&t1); 1495 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1496 1497 /* wait */ 1498 do { 1499 microtime(&t2); 1500 if (t2.tv_sec - t1.tv_sec > 1) 1501 break; 1502 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1503 ICH_PCMI + ICH_CIV); 1504 } while (nciv == ociv); 1505 1506 /* stop */ 1507 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1508 1509 /* reset */ 1510 DELAY(100); 1511 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1512 1513 /* turn time delta into us */ 1514 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1515 1516 auich_freem(sc, temp_buffer, M_DEVBUF); 1517 1518 if (nciv == ociv) { 1519 printf("%s: ac97 link rate calibration timed out after %d us\n", 1520 sc->sc_dev.dv_xname, wait_us); 1521 return; 1522 } 1523 1524 actual_48k_rate = (bytes * 250000U) / wait_us; 1525 1526 if (actual_48k_rate <= 48500) 1527 ac97rate = 48000; 1528 else 1529 ac97rate = actual_48k_rate; 1530 1531 printf("%s: measured ac97 link rate at %d Hz", 1532 sc->sc_dev.dv_xname, actual_48k_rate); 1533 if (ac97rate != actual_48k_rate) 1534 printf(", will use %d Hz", ac97rate); 1535 printf("\n"); 1536 1537 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1538 } 1539
Indexes created Thu Oct 23 22:10:10 GMT 2025