auich.c revision 1.46
1 /* $NetBSD: auich.c,v 1.46 2003/10/23 05:25:29 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * 108 * TODO: 109 * - Add support for the dedicated microphone input. 110 * 111 * NOTE: 112 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 113 * It causes PCI master abort and hangups until cold reboot. 114 * http://www.intel.com/design/chipsets/specupdt/245051.htm 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.46 2003/10/23 05:25:29 kent Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/kernel.h> 123 #include <sys/malloc.h> 124 #include <sys/device.h> 125 #include <sys/fcntl.h> 126 #include <sys/proc.h> 127 128 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 129 130 #include <dev/pci/pcidevs.h> 131 #include <dev/pci/pcivar.h> 132 #include <dev/pci/auichreg.h> 133 134 #include <sys/audioio.h> 135 #include <dev/audio_if.h> 136 #include <dev/mulaw.h> 137 #include <dev/auconv.h> 138 139 #include <machine/bus.h> 140 141 #include <dev/ic/ac97reg.h> 142 #include <dev/ic/ac97var.h> 143 144 struct auich_dma { 145 bus_dmamap_t map; 146 caddr_t addr; 147 bus_dma_segment_t segs[1]; 148 int nsegs; 149 size_t size; 150 struct auich_dma *next; 151 }; 152 153 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 154 #define KERNADDR(p) ((void *)((p)->addr)) 155 156 struct auich_cdata { 157 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 158 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 159 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 160 }; 161 162 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 163 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 164 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 165 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 166 167 struct auich_softc { 168 struct device sc_dev; 169 void *sc_ih; 170 171 audio_device_t sc_audev; 172 173 bus_space_tag_t iot; 174 bus_space_handle_t mix_ioh; 175 bus_space_handle_t aud_ioh; 176 bus_dma_tag_t dmat; 177 178 struct ac97_codec_if *codec_if; 179 struct ac97_host_if host_if; 180 181 /* DMA scatter-gather lists. */ 182 bus_dmamap_t sc_cddmamap; 183 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 184 185 struct auich_cdata *sc_cdata; 186 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 187 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 188 #define dmalist_mici sc_cdata->ic_dmalist_mici 189 190 int ptr_pcmo, 191 ptr_pcmi, 192 ptr_mici; 193 194 /* i/o buffer pointers */ 195 u_int32_t pcmo_start, pcmo_p, pcmo_end; 196 int pcmo_blksize, pcmo_fifoe; 197 198 u_int32_t pcmi_start, pcmi_p, pcmi_end; 199 int pcmi_blksize, pcmi_fifoe; 200 201 u_int32_t mici_start, mici_p, mici_end; 202 int mici_blksize, mici_fifoe; 203 204 struct auich_dma *sc_dmas; 205 206 #ifdef DIAGNOSTIC 207 pci_chipset_tag_t sc_pc; 208 pcitag_t sc_pt; 209 #endif 210 /* SiS 7012 hack */ 211 int sc_sample_size; 212 int sc_sts_reg; 213 /* 440MX workaround */ 214 int sc_dmamap_flags; 215 216 void (*sc_pintr)(void *); 217 void *sc_parg; 218 219 void (*sc_rintr)(void *); 220 void *sc_rarg; 221 222 /* Power Management */ 223 void *sc_powerhook; 224 int sc_suspend; 225 u_int16_t ext_status; 226 }; 227 228 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 229 & AC97_EXT_AUDIO_VRA) 230 #define SUPPORTS_4CH(codec) ((codec)->vtbl->get_extcaps(codec) \ 231 & AC97_EXT_AUDIO_SDAC) 232 #define AC97_6CH_DACS (AC97_EXT_AUDIO_SDAC | AC97_EXT_AUDIO_CDAC \ 233 | AC97_EXT_AUDIO_LDAC) 234 #define SUPPORTS_6CH(codec) (((codec)->vtbl->get_extcaps(codec) \ 235 & AC97_6CH_DACS) == AC97_6CH_DACS) 236 237 /* Debug */ 238 #ifdef AUDIO_DEBUG 239 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 240 int auich_debug = 0xfffe; 241 #define ICH_DEBUG_CODECIO 0x0001 242 #define ICH_DEBUG_DMA 0x0002 243 #define ICH_DEBUG_PARAM 0x0004 244 #else 245 #define DPRINTF(x,y) /* nothing */ 246 #endif 247 248 int auich_match(struct device *, struct cfdata *, void *); 249 void auich_attach(struct device *, struct device *, void *); 250 int auich_intr(void *); 251 252 CFATTACH_DECL(auich, sizeof(struct auich_softc), 253 auich_match, auich_attach, NULL, NULL); 254 255 int auich_open(void *, int); 256 void auich_close(void *); 257 int auich_query_encoding(void *, struct audio_encoding *); 258 int auich_set_params(void *, int, int, struct audio_params *, 259 struct audio_params *); 260 int auich_round_blocksize(void *, int); 261 int auich_halt_output(void *); 262 int auich_halt_input(void *); 263 int auich_getdev(void *, struct audio_device *); 264 int auich_set_port(void *, mixer_ctrl_t *); 265 int auich_get_port(void *, mixer_ctrl_t *); 266 int auich_query_devinfo(void *, mixer_devinfo_t *); 267 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 268 void auich_freem(void *, void *, struct malloc_type *); 269 size_t auich_round_buffersize(void *, int, size_t); 270 paddr_t auich_mappage(void *, void *, off_t, int); 271 int auich_get_props(void *); 272 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 273 void *, struct audio_params *); 274 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 275 void *, struct audio_params *); 276 277 int auich_alloc_cdata(struct auich_softc *); 278 279 int auich_allocmem(struct auich_softc *, size_t, size_t, 280 struct auich_dma *); 281 int auich_freemem(struct auich_softc *, struct auich_dma *); 282 283 void auich_powerhook(int, void *); 284 int auich_set_rate(struct auich_softc *, int, u_long); 285 void auich_finish_attach(struct device *); 286 void auich_calibrate(struct auich_softc *); 287 288 289 struct audio_hw_if auich_hw_if = { 290 auich_open, 291 auich_close, 292 NULL, /* drain */ 293 auich_query_encoding, 294 auich_set_params, 295 auich_round_blocksize, 296 NULL, /* commit_setting */ 297 NULL, /* init_output */ 298 NULL, /* init_input */ 299 NULL, /* start_output */ 300 NULL, /* start_input */ 301 auich_halt_output, 302 auich_halt_input, 303 NULL, /* speaker_ctl */ 304 auich_getdev, 305 NULL, /* getfd */ 306 auich_set_port, 307 auich_get_port, 308 auich_query_devinfo, 309 auich_allocm, 310 auich_freem, 311 auich_round_buffersize, 312 auich_mappage, 313 auich_get_props, 314 auich_trigger_output, 315 auich_trigger_input, 316 NULL, /* dev_ioctl */ 317 }; 318 319 int auich_attach_codec(void *, struct ac97_codec_if *); 320 int auich_read_codec(void *, u_int8_t, u_int16_t *); 321 int auich_write_codec(void *, u_int8_t, u_int16_t); 322 void auich_reset_codec(void *); 323 324 static const struct auich_devtype { 325 int vendor; 326 int product; 327 const char *name; 328 const char *shortname; 329 } auich_devices[] = { 330 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 331 "i82801AA (ICH) AC-97 Audio", "ICH" }, 332 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 333 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 334 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 335 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 336 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 337 "i82440MX AC-97 Audio", "440MX" }, 338 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 339 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 340 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 341 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 342 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 343 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 344 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 345 "SiS 7012 AC-97 Audio", "SiS7012" }, 346 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 347 "nForce MCP AC-97 Audio", "nForce-MCP" }, 348 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 349 "nForce2 MCP-T AC-97 Audio", "nForce-MCP-T" }, 350 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 351 "nForce3 MCP-T AC-97 Audio", "nForce-MCP-T" }, 352 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 353 "AMD768 AC-97 Audio", "AMD768" }, 354 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 355 "AMD8111 AC-97 Audio", "AMD8111" }, 356 { 0, 0, 357 NULL, NULL }, 358 }; 359 360 static const struct auich_devtype * 361 auich_lookup(struct pci_attach_args *pa) 362 { 363 const struct auich_devtype *d; 364 365 for (d = auich_devices; d->name != NULL; d++) { 366 if (PCI_VENDOR(pa->pa_id) == d->vendor 367 && PCI_PRODUCT(pa->pa_id) == d->product) 368 return (d); 369 } 370 371 return (NULL); 372 } 373 374 int 375 auich_match(struct device *parent, struct cfdata *match, void *aux) 376 { 377 struct pci_attach_args *pa = aux; 378 379 if (auich_lookup(pa) != NULL) 380 return (1); 381 382 return (0); 383 } 384 385 void 386 auich_attach(struct device *parent, struct device *self, void *aux) 387 { 388 struct auich_softc *sc = (struct auich_softc *)self; 389 struct pci_attach_args *pa = aux; 390 pci_intr_handle_t ih; 391 bus_size_t mix_size, aud_size; 392 pcireg_t csr; 393 const char *intrstr; 394 const struct auich_devtype *d; 395 396 aprint_naive(": Audio controller\n"); 397 398 d = auich_lookup(pa); 399 if (d == NULL) 400 panic("auich_attach: impossible"); 401 402 #ifdef DIAGNOSTIC 403 sc->sc_pc = pa->pa_pc; 404 sc->sc_pt = pa->pa_tag; 405 #endif 406 407 aprint_normal(": %s\n", d->name); 408 409 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 410 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 411 aprint_error("%s: can't map codec i/o space\n", 412 sc->sc_dev.dv_xname); 413 return; 414 } 415 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 416 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 417 aprint_error("%s: can't map device i/o space\n", 418 sc->sc_dev.dv_xname); 419 return; 420 } 421 sc->dmat = pa->pa_dmat; 422 423 /* enable bus mastering */ 424 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 425 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 426 csr | PCI_COMMAND_MASTER_ENABLE); 427 428 /* Map and establish the interrupt. */ 429 if (pci_intr_map(pa, &ih)) { 430 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 431 return; 432 } 433 intrstr = pci_intr_string(pa->pa_pc, ih); 434 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 435 auich_intr, sc); 436 if (sc->sc_ih == NULL) { 437 aprint_error("%s: can't establish interrupt", 438 sc->sc_dev.dv_xname); 439 if (intrstr != NULL) 440 aprint_normal(" at %s", intrstr); 441 aprint_normal("\n"); 442 return; 443 } 444 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 445 446 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 447 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 448 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 449 450 /* SiS 7012 needs special handling */ 451 if (d->vendor == PCI_VENDOR_SIS 452 && d->product == PCI_PRODUCT_SIS_7012_AC) { 453 sc->sc_sts_reg = ICH_PICB; 454 sc->sc_sample_size = 1; 455 } else { 456 sc->sc_sts_reg = ICH_STS; 457 sc->sc_sample_size = 2; 458 } 459 460 /* Workaround for a 440MX B-stepping erratum */ 461 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 462 if (d->vendor == PCI_VENDOR_INTEL 463 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 464 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 465 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 466 } 467 468 /* Set up DMA lists. */ 469 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 470 auich_alloc_cdata(sc); 471 472 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 473 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 474 475 #if 0 476 /* Reset codec and AC'97 */ 477 auich_reset_codec(sc); 478 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 479 480 /* Reset failure */ 481 if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) { 482 /* It never return ICH_PCR in some cases */ 483 if (d->quirks & QUIRK_IGNORE_CODEC_READY_MAYBE) { 484 sc->sc_ignore_codecready = TRUE; 485 } else { 486 return; 487 } 488 } 489 #endif 490 491 sc->host_if.arg = sc; 492 sc->host_if.attach = auich_attach_codec; 493 sc->host_if.read = auich_read_codec; 494 sc->host_if.write = auich_write_codec; 495 sc->host_if.reset = auich_reset_codec; 496 497 if (ac97_attach(&sc->host_if) != 0) 498 return; 499 500 /* Watch for power change */ 501 sc->sc_suspend = PWR_RESUME; 502 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 503 504 config_interrupts(self, auich_finish_attach); 505 } 506 507 void 508 auich_finish_attach(struct device *self) 509 { 510 struct auich_softc *sc = (void *)self; 511 512 if (!IS_FIXED_RATE(sc->codec_if)) 513 auich_calibrate(sc); 514 515 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 516 } 517 518 #define ICH_CODECIO_INTERVAL 10 519 int 520 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 521 { 522 struct auich_softc *sc = v; 523 int i; 524 uint32_t status; 525 526 /* wait for an access semaphore */ 527 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 528 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 529 DELAY(ICH_CODECIO_INTERVAL)); 530 531 if (i > 0) { 532 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 533 DPRINTF(ICH_DEBUG_CODECIO, 534 ("auich_read_codec(%x, %x)\n", reg, *val)); 535 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 536 if (status & ICH_RCS) { 537 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 538 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 539 *val = 0xffff; 540 } 541 return 0; 542 } else { 543 DPRINTF(ICH_DEBUG_CODECIO, 544 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 545 return -1; 546 } 547 } 548 549 int 550 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 551 { 552 struct auich_softc *sc = v; 553 int i; 554 555 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 556 /* wait for an access semaphore */ 557 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 558 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 559 DELAY(ICH_CODECIO_INTERVAL)); 560 561 if (i > 0) { 562 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 563 return 0; 564 } else { 565 DPRINTF(ICH_DEBUG_CODECIO, 566 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 567 return -1; 568 } 569 } 570 571 int 572 auich_attach_codec(void *v, struct ac97_codec_if *cif) 573 { 574 struct auich_softc *sc = v; 575 576 sc->codec_if = cif; 577 return 0; 578 } 579 580 void 581 auich_reset_codec(void *v) 582 { 583 struct auich_softc *sc = v; 584 int i; 585 uint32_t control; 586 587 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 588 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 589 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 590 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 591 592 for (i = 500000; i-- && 593 !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR); 594 DELAY(1)); /* or ICH_SCR? */ 595 #if 0 596 if (i <= 0) 597 printf("%s: auich_reset_codec: time out\n", 598 sc->sc_dev.dv_xname); 599 #endif 600 } 601 602 int 603 auich_open(void *v, int flags) 604 { 605 return 0; 606 } 607 608 void 609 auich_close(void *v) 610 { 611 struct auich_softc *sc = v; 612 613 auich_halt_output(sc); 614 auich_halt_input(sc); 615 616 sc->sc_pintr = NULL; 617 sc->sc_rintr = NULL; 618 } 619 620 int 621 auich_query_encoding(void *v, struct audio_encoding *aep) 622 { 623 624 switch (aep->index) { 625 case 0: 626 strcpy(aep->name, AudioEulinear); 627 aep->encoding = AUDIO_ENCODING_ULINEAR; 628 aep->precision = 8; 629 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 630 return (0); 631 case 1: 632 strcpy(aep->name, AudioEmulaw); 633 aep->encoding = AUDIO_ENCODING_ULAW; 634 aep->precision = 8; 635 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 636 return (0); 637 case 2: 638 strcpy(aep->name, AudioEalaw); 639 aep->encoding = AUDIO_ENCODING_ALAW; 640 aep->precision = 8; 641 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 642 return (0); 643 case 3: 644 strcpy(aep->name, AudioEslinear); 645 aep->encoding = AUDIO_ENCODING_SLINEAR; 646 aep->precision = 8; 647 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 648 return (0); 649 case 4: 650 strcpy(aep->name, AudioEslinear_le); 651 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 652 aep->precision = 16; 653 aep->flags = 0; 654 return (0); 655 case 5: 656 strcpy(aep->name, AudioEulinear_le); 657 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 658 aep->precision = 16; 659 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 660 return (0); 661 case 6: 662 strcpy(aep->name, AudioEslinear_be); 663 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 664 aep->precision = 16; 665 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 666 return (0); 667 case 7: 668 strcpy(aep->name, AudioEulinear_be); 669 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 670 aep->precision = 16; 671 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 672 return (0); 673 default: 674 return (EINVAL); 675 } 676 } 677 678 int 679 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 680 { 681 int ret; 682 u_long ratetmp; 683 684 ratetmp = srate; 685 if (mode == AUMODE_RECORD) 686 return sc->codec_if->vtbl->set_rate(sc->codec_if, 687 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 688 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 689 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 690 if (ret) 691 return ret; 692 ratetmp = srate; 693 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 694 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 695 if (ret) 696 return ret; 697 ratetmp = srate; 698 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 699 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 700 return ret; 701 } 702 703 int 704 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 705 struct audio_params *rec) 706 { 707 struct auich_softc *sc = v; 708 struct audio_params *p; 709 int mode; 710 u_int32_t control; 711 712 for (mode = AUMODE_RECORD; mode != -1; 713 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 714 if ((setmode & mode) == 0) 715 continue; 716 717 p = mode == AUMODE_PLAY ? play : rec; 718 if (p == NULL) 719 continue; 720 721 if ((p->sample_rate != 8000) && 722 (p->sample_rate != 11025) && 723 (p->sample_rate != 12000) && 724 (p->sample_rate != 16000) && 725 (p->sample_rate != 22050) && 726 (p->sample_rate != 24000) && 727 (p->sample_rate != 32000) && 728 (p->sample_rate != 44100) && 729 (p->sample_rate != 48000)) 730 return (EINVAL); 731 732 p->factor = 1; 733 if (p->precision == 8) 734 p->factor *= 2; 735 736 p->sw_code = NULL; 737 /* setup hardware formats */ 738 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 739 p->hw_precision = 16; 740 741 if (mode == AUMODE_RECORD) { 742 if (p->channels < 1 || p->channels > 2) 743 return EINVAL; 744 } else { 745 switch (p->channels) { 746 case 1: 747 break; 748 case 2: 749 break; 750 case 4: 751 if (!SUPPORTS_4CH(sc->codec_if)) 752 return EINVAL; 753 break; 754 case 6: 755 if (!SUPPORTS_6CH(sc->codec_if)) 756 return EINVAL; 757 break; 758 default: 759 return EINVAL; 760 } 761 } 762 /* If monaural is requested, aurateconv expands a monaural 763 * stream to stereo. */ 764 if (p->channels == 1) 765 p->hw_channels = 2; 766 767 switch (p->encoding) { 768 case AUDIO_ENCODING_SLINEAR_BE: 769 if (p->precision == 16) { 770 p->sw_code = swap_bytes; 771 } else { 772 if (mode == AUMODE_PLAY) 773 p->sw_code = linear8_to_linear16_le; 774 else 775 p->sw_code = linear16_to_linear8_le; 776 } 777 break; 778 779 case AUDIO_ENCODING_SLINEAR_LE: 780 if (p->precision != 16) { 781 if (mode == AUMODE_PLAY) 782 p->sw_code = linear8_to_linear16_le; 783 else 784 p->sw_code = linear16_to_linear8_le; 785 } 786 break; 787 788 case AUDIO_ENCODING_ULINEAR_BE: 789 if (p->precision == 16) { 790 if (mode == AUMODE_PLAY) 791 p->sw_code = 792 swap_bytes_change_sign16_le; 793 else 794 p->sw_code = 795 change_sign16_swap_bytes_le; 796 } else { 797 if (mode == AUMODE_PLAY) 798 p->sw_code = 799 ulinear8_to_slinear16_le; 800 else 801 p->sw_code = 802 slinear16_to_ulinear8_le; 803 } 804 break; 805 806 case AUDIO_ENCODING_ULINEAR_LE: 807 if (p->precision == 16) { 808 p->sw_code = change_sign16_le; 809 } else { 810 if (mode == AUMODE_PLAY) 811 p->sw_code = 812 ulinear8_to_slinear16_le; 813 else 814 p->sw_code = 815 slinear16_to_ulinear8_le; 816 } 817 break; 818 819 case AUDIO_ENCODING_ULAW: 820 if (mode == AUMODE_PLAY) { 821 p->sw_code = mulaw_to_slinear16_le; 822 } else { 823 p->sw_code = slinear16_to_mulaw_le; 824 } 825 break; 826 827 case AUDIO_ENCODING_ALAW: 828 if (mode == AUMODE_PLAY) { 829 p->sw_code = alaw_to_slinear16_le; 830 } else { 831 p->sw_code = slinear16_to_alaw_le; 832 } 833 break; 834 835 default: 836 return (EINVAL); 837 } 838 839 if (IS_FIXED_RATE(sc->codec_if)) { 840 p->hw_sample_rate = AC97_SINGLE_RATE; 841 /* If hw_sample_rate is changed, aurateconv works. */ 842 } else { 843 if (auich_set_rate(sc, mode, p->sample_rate)) 844 return EINVAL; 845 } 846 if (mode == AUMODE_PLAY) { 847 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 848 control &= ~ICH_PCM246_MASK; 849 if (p->channels == 4) { 850 control |= ICH_PCM4; 851 } else if (p->channels == 6) { 852 control |= ICH_PCM6; 853 } 854 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 855 } 856 } 857 858 return (0); 859 } 860 861 int 862 auich_round_blocksize(void *v, int blk) 863 { 864 865 return (blk & ~0x3f); /* keep good alignment */ 866 } 867 868 int 869 auich_halt_output(void *v) 870 { 871 struct auich_softc *sc = v; 872 873 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 874 875 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 876 877 return (0); 878 } 879 880 int 881 auich_halt_input(void *v) 882 { 883 struct auich_softc *sc = v; 884 885 DPRINTF(ICH_DEBUG_DMA, 886 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 887 888 /* XXX halt both unless known otherwise */ 889 890 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 891 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 892 893 return (0); 894 } 895 896 int 897 auich_getdev(void *v, struct audio_device *adp) 898 { 899 struct auich_softc *sc = v; 900 901 *adp = sc->sc_audev; 902 return (0); 903 } 904 905 int 906 auich_set_port(void *v, mixer_ctrl_t *cp) 907 { 908 struct auich_softc *sc = v; 909 910 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 911 } 912 913 int 914 auich_get_port(void *v, mixer_ctrl_t *cp) 915 { 916 struct auich_softc *sc = v; 917 918 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 919 } 920 921 int 922 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 923 { 924 struct auich_softc *sc = v; 925 926 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 927 } 928 929 void * 930 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 931 int flags) 932 { 933 struct auich_softc *sc = v; 934 struct auich_dma *p; 935 int error; 936 937 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 938 return (NULL); 939 940 p = malloc(sizeof(*p), pool, flags|M_ZERO); 941 if (p == NULL) 942 return (NULL); 943 944 error = auich_allocmem(sc, size, 0, p); 945 if (error) { 946 free(p, pool); 947 return (NULL); 948 } 949 950 p->next = sc->sc_dmas; 951 sc->sc_dmas = p; 952 953 return (KERNADDR(p)); 954 } 955 956 void 957 auich_freem(void *v, void *ptr, struct malloc_type *pool) 958 { 959 struct auich_softc *sc = v; 960 struct auich_dma *p, **pp; 961 962 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 963 if (KERNADDR(p) == ptr) { 964 auich_freemem(sc, p); 965 *pp = p->next; 966 free(p, pool); 967 return; 968 } 969 } 970 } 971 972 size_t 973 auich_round_buffersize(void *v, int direction, size_t size) 974 { 975 976 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 977 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 978 979 return size; 980 } 981 982 paddr_t 983 auich_mappage(void *v, void *mem, off_t off, int prot) 984 { 985 struct auich_softc *sc = v; 986 struct auich_dma *p; 987 988 if (off < 0) 989 return (-1); 990 991 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 992 ; 993 if (!p) 994 return (-1); 995 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 996 off, prot, BUS_DMA_WAITOK)); 997 } 998 999 int 1000 auich_get_props(void *v) 1001 { 1002 struct auich_softc *sc = v; 1003 int props; 1004 1005 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1006 /* 1007 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1008 * rate because of aurateconv. Applications can't know what rate the 1009 * device can process in the case of mmap(). 1010 */ 1011 if (!IS_FIXED_RATE(sc->codec_if)) 1012 props |= AUDIO_PROP_MMAP; 1013 return props; 1014 } 1015 1016 int 1017 auich_intr(void *v) 1018 { 1019 struct auich_softc *sc = v; 1020 int ret = 0, sts, gsts, i, qptr; 1021 1022 #ifdef DIAGNOSTIC 1023 int csts; 1024 #endif 1025 1026 #ifdef DIAGNOSTIC 1027 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1028 if (csts & PCI_STATUS_MASTER_ABORT) { 1029 printf("auich_intr: PCI master abort\n"); 1030 } 1031 #endif 1032 1033 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 1034 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 1035 1036 if (gsts & ICH_POINT) { 1037 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 1038 DPRINTF(ICH_DEBUG_DMA, 1039 ("auich_intr: osts=0x%x\n", sts)); 1040 1041 if (sts & ICH_FIFOE) { 1042 printf("%s: fifo underrun # %u\n", 1043 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1044 } 1045 1046 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1047 if (sts & (ICH_LVBCI | ICH_CELV)) { 1048 struct auich_dmalist *q; 1049 1050 qptr = sc->ptr_pcmo; 1051 1052 while (qptr != i) { 1053 q = &sc->dmalist_pcmo[qptr]; 1054 1055 q->base = sc->pcmo_p; 1056 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1057 DPRINTF(ICH_DEBUG_DMA, 1058 ("auich_intr: %p, %p = %x @ 0x%x\n", 1059 &sc->dmalist_pcmo[i], q, 1060 sc->pcmo_blksize / 2, sc->pcmo_p)); 1061 1062 sc->pcmo_p += sc->pcmo_blksize; 1063 if (sc->pcmo_p >= sc->pcmo_end) 1064 sc->pcmo_p = sc->pcmo_start; 1065 1066 if (++qptr == ICH_DMALIST_MAX) 1067 qptr = 0; 1068 } 1069 1070 sc->ptr_pcmo = qptr; 1071 bus_space_write_1(sc->iot, sc->aud_ioh, 1072 ICH_PCMO + ICH_LVI, 1073 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1074 } 1075 1076 if (sts & ICH_BCIS && sc->sc_pintr) 1077 sc->sc_pintr(sc->sc_parg); 1078 1079 /* int ack */ 1080 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1081 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1082 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1083 ret++; 1084 } 1085 1086 if (gsts & ICH_PIINT) { 1087 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1088 DPRINTF(ICH_DEBUG_DMA, 1089 ("auich_intr: ists=0x%x\n", sts)); 1090 1091 if (sts & ICH_FIFOE) { 1092 printf("%s: fifo overrun # %u\n", 1093 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1094 } 1095 1096 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1097 if (sts & (ICH_LVBCI | ICH_CELV)) { 1098 struct auich_dmalist *q; 1099 1100 qptr = sc->ptr_pcmi; 1101 1102 while (qptr != i) { 1103 q = &sc->dmalist_pcmi[qptr]; 1104 1105 q->base = sc->pcmi_p; 1106 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1107 DPRINTF(ICH_DEBUG_DMA, 1108 ("auich_intr: %p, %p = %x @ 0x%x\n", 1109 &sc->dmalist_pcmi[i], q, 1110 sc->pcmi_blksize / 2, sc->pcmi_p)); 1111 1112 sc->pcmi_p += sc->pcmi_blksize; 1113 if (sc->pcmi_p >= sc->pcmi_end) 1114 sc->pcmi_p = sc->pcmi_start; 1115 1116 if (++qptr == ICH_DMALIST_MAX) 1117 qptr = 0; 1118 } 1119 1120 sc->ptr_pcmi = qptr; 1121 bus_space_write_1(sc->iot, sc->aud_ioh, 1122 ICH_PCMI + ICH_LVI, 1123 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1124 } 1125 1126 if (sts & ICH_BCIS && sc->sc_rintr) 1127 sc->sc_rintr(sc->sc_rarg); 1128 1129 /* int ack */ 1130 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1131 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1132 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1133 ret++; 1134 } 1135 1136 if (gsts & ICH_MIINT) { 1137 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1138 DPRINTF(ICH_DEBUG_DMA, 1139 ("auich_intr: ists=0x%x\n", sts)); 1140 if (sts & ICH_FIFOE) 1141 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1142 1143 /* TODO mic input DMA */ 1144 1145 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1146 } 1147 1148 return ret; 1149 } 1150 1151 int 1152 auich_trigger_output(void *v, void *start, void *end, int blksize, 1153 void (*intr)(void *), void *arg, struct audio_params *param) 1154 { 1155 struct auich_softc *sc = v; 1156 struct auich_dmalist *q; 1157 struct auich_dma *p; 1158 size_t size; 1159 #ifdef DIAGNOSTIC 1160 int csts; 1161 #endif 1162 1163 DPRINTF(ICH_DEBUG_DMA, 1164 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1165 start, end, blksize, intr, arg, param)); 1166 1167 sc->sc_pintr = intr; 1168 sc->sc_parg = arg; 1169 #ifdef DIAGNOSTIC 1170 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1171 if (csts & PCI_STATUS_MASTER_ABORT) { 1172 printf("auich_trigger_output: PCI master abort\n"); 1173 } 1174 #endif 1175 1176 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1177 ; 1178 if (!p) { 1179 printf("auich_trigger_output: bad addr %p\n", start); 1180 return (EINVAL); 1181 } 1182 1183 size = (size_t)((caddr_t)end - (caddr_t)start); 1184 1185 /* 1186 * The logic behind this is: 1187 * setup one buffer to play, then LVI dump out the rest 1188 * to the scatter-gather chain. 1189 */ 1190 sc->pcmo_start = DMAADDR(p); 1191 sc->pcmo_p = sc->pcmo_start + blksize; 1192 sc->pcmo_end = sc->pcmo_start + size; 1193 sc->pcmo_blksize = blksize; 1194 1195 sc->ptr_pcmo = 0; 1196 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1197 q->base = sc->pcmo_start; 1198 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1199 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1200 sc->ptr_pcmo = 0; 1201 1202 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1203 sc->sc_cddma + ICH_PCMO_OFF(0)); 1204 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1205 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1206 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1207 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1208 1209 return (0); 1210 } 1211 1212 int 1213 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1214 void *v; 1215 void *start, *end; 1216 int blksize; 1217 void (*intr)(void *); 1218 void *arg; 1219 struct audio_params *param; 1220 { 1221 struct auich_softc *sc = v; 1222 struct auich_dmalist *q; 1223 struct auich_dma *p; 1224 size_t size; 1225 #ifdef DIAGNOSTIC 1226 int csts; 1227 #endif 1228 1229 DPRINTF(ICH_DEBUG_DMA, 1230 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1231 start, end, blksize, intr, arg, param)); 1232 1233 sc->sc_rintr = intr; 1234 sc->sc_rarg = arg; 1235 1236 #ifdef DIAGNOSTIC 1237 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1238 if (csts & PCI_STATUS_MASTER_ABORT) { 1239 printf("auich_trigger_input: PCI master abort\n"); 1240 } 1241 #endif 1242 1243 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1244 ; 1245 if (!p) { 1246 printf("auich_trigger_input: bad addr %p\n", start); 1247 return (EINVAL); 1248 } 1249 1250 size = (size_t)((caddr_t)end - (caddr_t)start); 1251 1252 /* 1253 * The logic behind this is: 1254 * setup one buffer to play, then LVI dump out the rest 1255 * to the scatter-gather chain. 1256 */ 1257 sc->pcmi_start = DMAADDR(p); 1258 sc->pcmi_p = sc->pcmi_start + blksize; 1259 sc->pcmi_end = sc->pcmi_start + size; 1260 sc->pcmi_blksize = blksize; 1261 1262 sc->ptr_pcmi = 0; 1263 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1264 q->base = sc->pcmi_start; 1265 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1266 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1267 sc->ptr_pcmi = 0; 1268 1269 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1270 sc->sc_cddma + ICH_PCMI_OFF(0)); 1271 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1272 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1273 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1274 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1275 1276 return (0); 1277 } 1278 1279 int 1280 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1281 struct auich_dma *p) 1282 { 1283 int error; 1284 1285 p->size = size; 1286 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1287 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1288 &p->nsegs, BUS_DMA_NOWAIT); 1289 if (error) 1290 return (error); 1291 1292 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1293 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1294 if (error) 1295 goto free; 1296 1297 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1298 0, BUS_DMA_NOWAIT, &p->map); 1299 if (error) 1300 goto unmap; 1301 1302 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1303 BUS_DMA_NOWAIT); 1304 if (error) 1305 goto destroy; 1306 return (0); 1307 1308 destroy: 1309 bus_dmamap_destroy(sc->dmat, p->map); 1310 unmap: 1311 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1312 free: 1313 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1314 return (error); 1315 } 1316 1317 int 1318 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1319 { 1320 1321 bus_dmamap_unload(sc->dmat, p->map); 1322 bus_dmamap_destroy(sc->dmat, p->map); 1323 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1324 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1325 return (0); 1326 } 1327 1328 int 1329 auich_alloc_cdata(struct auich_softc *sc) 1330 { 1331 bus_dma_segment_t seg; 1332 int error, rseg; 1333 1334 /* 1335 * Allocate the control data structure, and create and load the 1336 * DMA map for it. 1337 */ 1338 if ((error = bus_dmamem_alloc(sc->dmat, 1339 sizeof(struct auich_cdata), 1340 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1341 printf("%s: unable to allocate control data, error = %d\n", 1342 sc->sc_dev.dv_xname, error); 1343 goto fail_0; 1344 } 1345 1346 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1347 sizeof(struct auich_cdata), 1348 (caddr_t *) &sc->sc_cdata, 1349 sc->sc_dmamap_flags)) != 0) { 1350 printf("%s: unable to map control data, error = %d\n", 1351 sc->sc_dev.dv_xname, error); 1352 goto fail_1; 1353 } 1354 1355 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1356 sizeof(struct auich_cdata), 0, 0, 1357 &sc->sc_cddmamap)) != 0) { 1358 printf("%s: unable to create control data DMA map, " 1359 "error = %d\n", sc->sc_dev.dv_xname, error); 1360 goto fail_2; 1361 } 1362 1363 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1364 sc->sc_cdata, sizeof(struct auich_cdata), 1365 NULL, 0)) != 0) { 1366 printf("%s: unable tp load control data DMA map, " 1367 "error = %d\n", sc->sc_dev.dv_xname, error); 1368 goto fail_3; 1369 } 1370 1371 return (0); 1372 1373 fail_3: 1374 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1375 fail_2: 1376 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1377 sizeof(struct auich_cdata)); 1378 fail_1: 1379 bus_dmamem_free(sc->dmat, &seg, rseg); 1380 fail_0: 1381 return (error); 1382 } 1383 1384 void 1385 auich_powerhook(int why, void *addr) 1386 { 1387 struct auich_softc *sc = (struct auich_softc *)addr; 1388 1389 switch (why) { 1390 case PWR_SUSPEND: 1391 case PWR_STANDBY: 1392 /* Power down */ 1393 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1394 sc->sc_suspend = why; 1395 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1396 break; 1397 1398 case PWR_RESUME: 1399 /* Wake up */ 1400 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1401 if (sc->sc_suspend == PWR_RESUME) { 1402 printf("%s: resume without suspend.\n", 1403 sc->sc_dev.dv_xname); 1404 sc->sc_suspend = why; 1405 return; 1406 } 1407 sc->sc_suspend = why; 1408 auich_reset_codec(sc); 1409 DELAY(1000); 1410 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1411 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1412 break; 1413 1414 case PWR_SOFTSUSPEND: 1415 case PWR_SOFTSTANDBY: 1416 case PWR_SOFTRESUME: 1417 break; 1418 } 1419 } 1420 1421 1422 /* -------------------------------------------------------------------- */ 1423 /* Calibrate card (some boards are overclocked and need scaling) */ 1424 1425 void 1426 auich_calibrate(struct auich_softc *sc) 1427 { 1428 struct timeval t1, t2; 1429 u_int8_t ociv, nciv; 1430 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1431 void *temp_buffer; 1432 struct auich_dma *p; 1433 1434 /* 1435 * Grab audio from input for fixed interval and compare how 1436 * much we actually get with what we expect. Interval needs 1437 * to be sufficiently short that no interrupts are 1438 * generated. 1439 */ 1440 1441 /* Setup a buffer */ 1442 bytes = 16000; 1443 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1444 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1445 ; 1446 if (p == NULL) { 1447 printf("auich_calibrate: bad address %p\n", temp_buffer); 1448 return; 1449 } 1450 sc->dmalist_pcmi[0].base = DMAADDR(p); 1451 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size); 1452 1453 /* 1454 * our data format is stereo, 16 bit so each sample is 4 bytes. 1455 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1456 * we're going to start recording with interrupts disabled and measure 1457 * the time taken for one block to complete. we know the block size, 1458 * we know the time in microseconds, we calculate the sample rate: 1459 * 1460 * actual_rate [bps] = bytes / (time [s] * 4) 1461 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1462 * actual_rate [Hz] = (bytes * 250000) / time [us] 1463 */ 1464 1465 /* prepare */ 1466 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1467 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1468 sc->sc_cddma + ICH_PCMI_OFF(0)); 1469 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1470 (0 - 1) & ICH_LVI_MASK); 1471 1472 /* start */ 1473 microtime(&t1); 1474 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1475 1476 /* wait */ 1477 do { 1478 microtime(&t2); 1479 if (t2.tv_sec - t1.tv_sec > 1) 1480 break; 1481 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1482 ICH_PCMI + ICH_CIV); 1483 } while (nciv == ociv); 1484 1485 /* stop */ 1486 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1487 1488 /* reset */ 1489 DELAY(100); 1490 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1491 1492 /* turn time delta into us */ 1493 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1494 1495 auich_freem(sc, temp_buffer, M_DEVBUF); 1496 1497 if (nciv == ociv) { 1498 printf("%s: ac97 link rate calibration timed out after %d us\n", 1499 sc->sc_dev.dv_xname, wait_us); 1500 return; 1501 } 1502 1503 actual_48k_rate = (bytes * 250000U) / wait_us; 1504 1505 if (actual_48k_rate <= 48500) 1506 ac97rate = 48000; 1507 else 1508 ac97rate = actual_48k_rate; 1509 1510 printf("%s: measured ac97 link rate at %d Hz", 1511 sc->sc_dev.dv_xname, actual_48k_rate); 1512 if (ac97rate != actual_48k_rate) 1513 printf(", will use %d Hz", ac97rate); 1514 printf("\n"); 1515 1516 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1517 } 1518
Indexes created Thu Oct 23 22:10:10 GMT 2025