auich.c revision 1.47
1 /* $NetBSD: auich.c,v 1.47 2003/10/23 17:05:26 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * 108 * TODO: 109 * - Add support for the dedicated microphone input. 110 * 111 * NOTE: 112 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 113 * It causes PCI master abort and hangups until cold reboot. 114 * http://www.intel.com/design/chipsets/specupdt/245051.htm 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.47 2003/10/23 17:05:26 kent Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/kernel.h> 123 #include <sys/malloc.h> 124 #include <sys/device.h> 125 #include <sys/fcntl.h> 126 #include <sys/proc.h> 127 128 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 129 130 #include <dev/pci/pcidevs.h> 131 #include <dev/pci/pcivar.h> 132 #include <dev/pci/auichreg.h> 133 134 #include <sys/audioio.h> 135 #include <dev/audio_if.h> 136 #include <dev/mulaw.h> 137 #include <dev/auconv.h> 138 139 #include <machine/bus.h> 140 141 #include <dev/ic/ac97reg.h> 142 #include <dev/ic/ac97var.h> 143 144 struct auich_dma { 145 bus_dmamap_t map; 146 caddr_t addr; 147 bus_dma_segment_t segs[1]; 148 int nsegs; 149 size_t size; 150 struct auich_dma *next; 151 }; 152 153 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 154 #define KERNADDR(p) ((void *)((p)->addr)) 155 156 struct auich_cdata { 157 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 158 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 159 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 160 }; 161 162 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 163 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 164 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 165 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 166 167 struct auich_softc { 168 struct device sc_dev; 169 void *sc_ih; 170 171 audio_device_t sc_audev; 172 173 bus_space_tag_t iot; 174 bus_space_handle_t mix_ioh; 175 bus_space_handle_t aud_ioh; 176 bus_dma_tag_t dmat; 177 178 struct ac97_codec_if *codec_if; 179 struct ac97_host_if host_if; 180 181 /* DMA scatter-gather lists. */ 182 bus_dmamap_t sc_cddmamap; 183 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 184 185 struct auich_cdata *sc_cdata; 186 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 187 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 188 #define dmalist_mici sc_cdata->ic_dmalist_mici 189 190 int ptr_pcmo, 191 ptr_pcmi, 192 ptr_mici; 193 194 /* i/o buffer pointers */ 195 u_int32_t pcmo_start, pcmo_p, pcmo_end; 196 int pcmo_blksize, pcmo_fifoe; 197 198 u_int32_t pcmi_start, pcmi_p, pcmi_end; 199 int pcmi_blksize, pcmi_fifoe; 200 201 u_int32_t mici_start, mici_p, mici_end; 202 int mici_blksize, mici_fifoe; 203 204 struct auich_dma *sc_dmas; 205 206 #ifdef DIAGNOSTIC 207 pci_chipset_tag_t sc_pc; 208 pcitag_t sc_pt; 209 #endif 210 /* SiS 7012 hack */ 211 int sc_sample_size; 212 int sc_sts_reg; 213 /* 440MX workaround */ 214 int sc_dmamap_flags; 215 216 void (*sc_pintr)(void *); 217 void *sc_parg; 218 219 void (*sc_rintr)(void *); 220 void *sc_rarg; 221 222 /* Power Management */ 223 void *sc_powerhook; 224 int sc_suspend; 225 u_int16_t ext_status; 226 }; 227 228 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 229 & AC97_EXT_AUDIO_VRA) 230 #define SUPPORTS_4CH(codec) ((codec)->vtbl->get_extcaps(codec) \ 231 & AC97_EXT_AUDIO_SDAC) 232 #define AC97_6CH_DACS (AC97_EXT_AUDIO_SDAC | AC97_EXT_AUDIO_CDAC \ 233 | AC97_EXT_AUDIO_LDAC) 234 #define SUPPORTS_6CH(codec) (((codec)->vtbl->get_extcaps(codec) \ 235 & AC97_6CH_DACS) == AC97_6CH_DACS) 236 237 /* Debug */ 238 #ifdef AUDIO_DEBUG 239 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 240 int auich_debug = 0xfffe; 241 #define ICH_DEBUG_CODECIO 0x0001 242 #define ICH_DEBUG_DMA 0x0002 243 #define ICH_DEBUG_PARAM 0x0004 244 #else 245 #define DPRINTF(x,y) /* nothing */ 246 #endif 247 248 int auich_match(struct device *, struct cfdata *, void *); 249 void auich_attach(struct device *, struct device *, void *); 250 int auich_intr(void *); 251 252 CFATTACH_DECL(auich, sizeof(struct auich_softc), 253 auich_match, auich_attach, NULL, NULL); 254 255 int auich_open(void *, int); 256 void auich_close(void *); 257 int auich_query_encoding(void *, struct audio_encoding *); 258 int auich_set_params(void *, int, int, struct audio_params *, 259 struct audio_params *); 260 int auich_round_blocksize(void *, int); 261 int auich_halt_output(void *); 262 int auich_halt_input(void *); 263 int auich_getdev(void *, struct audio_device *); 264 int auich_set_port(void *, mixer_ctrl_t *); 265 int auich_get_port(void *, mixer_ctrl_t *); 266 int auich_query_devinfo(void *, mixer_devinfo_t *); 267 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 268 void auich_freem(void *, void *, struct malloc_type *); 269 size_t auich_round_buffersize(void *, int, size_t); 270 paddr_t auich_mappage(void *, void *, off_t, int); 271 int auich_get_props(void *); 272 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 273 void *, struct audio_params *); 274 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 275 void *, struct audio_params *); 276 277 int auich_alloc_cdata(struct auich_softc *); 278 279 int auich_allocmem(struct auich_softc *, size_t, size_t, 280 struct auich_dma *); 281 int auich_freemem(struct auich_softc *, struct auich_dma *); 282 283 void auich_powerhook(int, void *); 284 int auich_set_rate(struct auich_softc *, int, u_long); 285 void auich_finish_attach(struct device *); 286 void auich_calibrate(struct auich_softc *); 287 288 289 struct audio_hw_if auich_hw_if = { 290 auich_open, 291 auich_close, 292 NULL, /* drain */ 293 auich_query_encoding, 294 auich_set_params, 295 auich_round_blocksize, 296 NULL, /* commit_setting */ 297 NULL, /* init_output */ 298 NULL, /* init_input */ 299 NULL, /* start_output */ 300 NULL, /* start_input */ 301 auich_halt_output, 302 auich_halt_input, 303 NULL, /* speaker_ctl */ 304 auich_getdev, 305 NULL, /* getfd */ 306 auich_set_port, 307 auich_get_port, 308 auich_query_devinfo, 309 auich_allocm, 310 auich_freem, 311 auich_round_buffersize, 312 auich_mappage, 313 auich_get_props, 314 auich_trigger_output, 315 auich_trigger_input, 316 NULL, /* dev_ioctl */ 317 }; 318 319 int auich_attach_codec(void *, struct ac97_codec_if *); 320 int auich_read_codec(void *, u_int8_t, u_int16_t *); 321 int auich_write_codec(void *, u_int8_t, u_int16_t); 322 void auich_reset_codec(void *); 323 324 static const struct auich_devtype { 325 int vendor; 326 int product; 327 const char *name; 328 const char *shortname; 329 } auich_devices[] = { 330 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 331 "i82801AA (ICH) AC-97 Audio", "ICH" }, 332 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 333 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 334 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 335 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 336 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 337 "i82440MX AC-97 Audio", "440MX" }, 338 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 339 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 340 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 341 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 342 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 343 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 344 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 345 "SiS 7012 AC-97 Audio", "SiS7012" }, 346 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 347 "nForce MCP AC-97 Audio", "nForce-MCP" }, 348 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 349 "nForce2 MCP-T AC-97 Audio", "nForce-MCP-T" }, 350 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 351 "nForce3 MCP-T AC-97 Audio", "nForce-MCP-T" }, 352 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 353 "AMD768 AC-97 Audio", "AMD768" }, 354 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 355 "AMD8111 AC-97 Audio", "AMD8111" }, 356 { 0, 0, 357 NULL, NULL }, 358 }; 359 360 static const struct auich_devtype * 361 auich_lookup(struct pci_attach_args *pa) 362 { 363 const struct auich_devtype *d; 364 365 for (d = auich_devices; d->name != NULL; d++) { 366 if (PCI_VENDOR(pa->pa_id) == d->vendor 367 && PCI_PRODUCT(pa->pa_id) == d->product) 368 return (d); 369 } 370 371 return (NULL); 372 } 373 374 int 375 auich_match(struct device *parent, struct cfdata *match, void *aux) 376 { 377 struct pci_attach_args *pa = aux; 378 379 if (auich_lookup(pa) != NULL) 380 return (1); 381 382 return (0); 383 } 384 385 void 386 auich_attach(struct device *parent, struct device *self, void *aux) 387 { 388 struct auich_softc *sc = (struct auich_softc *)self; 389 struct pci_attach_args *pa = aux; 390 pci_intr_handle_t ih; 391 bus_size_t mix_size, aud_size; 392 pcireg_t csr; 393 const char *intrstr; 394 const struct auich_devtype *d; 395 396 aprint_naive(": Audio controller\n"); 397 398 d = auich_lookup(pa); 399 if (d == NULL) 400 panic("auich_attach: impossible"); 401 402 #ifdef DIAGNOSTIC 403 sc->sc_pc = pa->pa_pc; 404 sc->sc_pt = pa->pa_tag; 405 #endif 406 407 aprint_normal(": %s\n", d->name); 408 409 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 410 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 411 aprint_error("%s: can't map codec i/o space\n", 412 sc->sc_dev.dv_xname); 413 return; 414 } 415 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 416 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 417 aprint_error("%s: can't map device i/o space\n", 418 sc->sc_dev.dv_xname); 419 return; 420 } 421 sc->dmat = pa->pa_dmat; 422 423 /* enable bus mastering */ 424 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 425 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 426 csr | PCI_COMMAND_MASTER_ENABLE); 427 428 /* Map and establish the interrupt. */ 429 if (pci_intr_map(pa, &ih)) { 430 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 431 return; 432 } 433 intrstr = pci_intr_string(pa->pa_pc, ih); 434 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 435 auich_intr, sc); 436 if (sc->sc_ih == NULL) { 437 aprint_error("%s: can't establish interrupt", 438 sc->sc_dev.dv_xname); 439 if (intrstr != NULL) 440 aprint_normal(" at %s", intrstr); 441 aprint_normal("\n"); 442 return; 443 } 444 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 445 446 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 447 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 448 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 449 450 /* SiS 7012 needs special handling */ 451 if (d->vendor == PCI_VENDOR_SIS 452 && d->product == PCI_PRODUCT_SIS_7012_AC) { 453 sc->sc_sts_reg = ICH_PICB; 454 sc->sc_sample_size = 1; 455 } else { 456 sc->sc_sts_reg = ICH_STS; 457 sc->sc_sample_size = 2; 458 } 459 460 /* Workaround for a 440MX B-stepping erratum */ 461 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 462 if (d->vendor == PCI_VENDOR_INTEL 463 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 464 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 465 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 466 } 467 468 /* Set up DMA lists. */ 469 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 470 auich_alloc_cdata(sc); 471 472 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 473 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 474 475 sc->host_if.arg = sc; 476 sc->host_if.attach = auich_attach_codec; 477 sc->host_if.read = auich_read_codec; 478 sc->host_if.write = auich_write_codec; 479 sc->host_if.reset = auich_reset_codec; 480 481 if (ac97_attach(&sc->host_if) != 0) 482 return; 483 484 /* Watch for power change */ 485 sc->sc_suspend = PWR_RESUME; 486 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 487 488 config_interrupts(self, auich_finish_attach); 489 } 490 491 void 492 auich_finish_attach(struct device *self) 493 { 494 struct auich_softc *sc = (void *)self; 495 496 if (!IS_FIXED_RATE(sc->codec_if)) 497 auich_calibrate(sc); 498 499 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 500 } 501 502 #define ICH_CODECIO_INTERVAL 10 503 int 504 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 505 { 506 struct auich_softc *sc = v; 507 int i; 508 uint32_t status; 509 510 /* wait for an access semaphore */ 511 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 512 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 513 DELAY(ICH_CODECIO_INTERVAL)); 514 515 if (i > 0) { 516 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 517 DPRINTF(ICH_DEBUG_CODECIO, 518 ("auich_read_codec(%x, %x)\n", reg, *val)); 519 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 520 if (status & ICH_RCS) { 521 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 522 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 523 *val = 0xffff; 524 } 525 return 0; 526 } else { 527 DPRINTF(ICH_DEBUG_CODECIO, 528 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 529 return -1; 530 } 531 } 532 533 int 534 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 535 { 536 struct auich_softc *sc = v; 537 int i; 538 539 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 540 /* wait for an access semaphore */ 541 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 542 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 543 DELAY(ICH_CODECIO_INTERVAL)); 544 545 if (i > 0) { 546 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 547 return 0; 548 } else { 549 DPRINTF(ICH_DEBUG_CODECIO, 550 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 551 return -1; 552 } 553 } 554 555 int 556 auich_attach_codec(void *v, struct ac97_codec_if *cif) 557 { 558 struct auich_softc *sc = v; 559 560 sc->codec_if = cif; 561 return 0; 562 } 563 564 void 565 auich_reset_codec(void *v) 566 { 567 struct auich_softc *sc = v; 568 int i; 569 uint32_t control, status; 570 571 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 572 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 573 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 574 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 575 576 for (i = 500000; i >= 0; i--) { 577 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 578 if (status & ICH_PCR) 579 break; 580 DELAY(1); 581 } 582 if (i <= 0) { 583 printf("%s: auich_reset_codec: time out for the primary codec\n", 584 sc->sc_dev.dv_xname); 585 if (status & ICH_SCR) 586 printf("%s: auich_reset_codec: The 2nd codec is ready.\n", 587 sc->sc_dev.dv_xname); 588 if (status & ICH_S2CR) 589 printf("%s: auich_reset_codec: The 3rd codec is ready.\n", 590 sc->sc_dev.dv_xname); 591 } 592 } 593 594 int 595 auich_open(void *v, int flags) 596 { 597 return 0; 598 } 599 600 void 601 auich_close(void *v) 602 { 603 struct auich_softc *sc = v; 604 605 auich_halt_output(sc); 606 auich_halt_input(sc); 607 608 sc->sc_pintr = NULL; 609 sc->sc_rintr = NULL; 610 } 611 612 int 613 auich_query_encoding(void *v, struct audio_encoding *aep) 614 { 615 616 switch (aep->index) { 617 case 0: 618 strcpy(aep->name, AudioEulinear); 619 aep->encoding = AUDIO_ENCODING_ULINEAR; 620 aep->precision = 8; 621 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 622 return (0); 623 case 1: 624 strcpy(aep->name, AudioEmulaw); 625 aep->encoding = AUDIO_ENCODING_ULAW; 626 aep->precision = 8; 627 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 628 return (0); 629 case 2: 630 strcpy(aep->name, AudioEalaw); 631 aep->encoding = AUDIO_ENCODING_ALAW; 632 aep->precision = 8; 633 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 634 return (0); 635 case 3: 636 strcpy(aep->name, AudioEslinear); 637 aep->encoding = AUDIO_ENCODING_SLINEAR; 638 aep->precision = 8; 639 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 640 return (0); 641 case 4: 642 strcpy(aep->name, AudioEslinear_le); 643 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 644 aep->precision = 16; 645 aep->flags = 0; 646 return (0); 647 case 5: 648 strcpy(aep->name, AudioEulinear_le); 649 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 650 aep->precision = 16; 651 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 652 return (0); 653 case 6: 654 strcpy(aep->name, AudioEslinear_be); 655 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 656 aep->precision = 16; 657 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 658 return (0); 659 case 7: 660 strcpy(aep->name, AudioEulinear_be); 661 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 662 aep->precision = 16; 663 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 664 return (0); 665 default: 666 return (EINVAL); 667 } 668 } 669 670 int 671 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 672 { 673 int ret; 674 u_long ratetmp; 675 676 ratetmp = srate; 677 if (mode == AUMODE_RECORD) 678 return sc->codec_if->vtbl->set_rate(sc->codec_if, 679 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 680 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 681 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 682 if (ret) 683 return ret; 684 ratetmp = srate; 685 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 686 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 687 if (ret) 688 return ret; 689 ratetmp = srate; 690 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 691 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 692 return ret; 693 } 694 695 int 696 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 697 struct audio_params *rec) 698 { 699 struct auich_softc *sc = v; 700 struct audio_params *p; 701 int mode; 702 u_int32_t control; 703 704 for (mode = AUMODE_RECORD; mode != -1; 705 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 706 if ((setmode & mode) == 0) 707 continue; 708 709 p = mode == AUMODE_PLAY ? play : rec; 710 if (p == NULL) 711 continue; 712 713 if ((p->sample_rate != 8000) && 714 (p->sample_rate != 11025) && 715 (p->sample_rate != 12000) && 716 (p->sample_rate != 16000) && 717 (p->sample_rate != 22050) && 718 (p->sample_rate != 24000) && 719 (p->sample_rate != 32000) && 720 (p->sample_rate != 44100) && 721 (p->sample_rate != 48000)) 722 return (EINVAL); 723 724 p->factor = 1; 725 if (p->precision == 8) 726 p->factor *= 2; 727 728 p->sw_code = NULL; 729 /* setup hardware formats */ 730 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 731 p->hw_precision = 16; 732 733 if (mode == AUMODE_RECORD) { 734 if (p->channels < 1 || p->channels > 2) 735 return EINVAL; 736 } else { 737 switch (p->channels) { 738 case 1: 739 break; 740 case 2: 741 break; 742 case 4: 743 if (!SUPPORTS_4CH(sc->codec_if)) 744 return EINVAL; 745 break; 746 case 6: 747 if (!SUPPORTS_6CH(sc->codec_if)) 748 return EINVAL; 749 break; 750 default: 751 return EINVAL; 752 } 753 } 754 /* If monaural is requested, aurateconv expands a monaural 755 * stream to stereo. */ 756 if (p->channels == 1) 757 p->hw_channels = 2; 758 759 switch (p->encoding) { 760 case AUDIO_ENCODING_SLINEAR_BE: 761 if (p->precision == 16) { 762 p->sw_code = swap_bytes; 763 } else { 764 if (mode == AUMODE_PLAY) 765 p->sw_code = linear8_to_linear16_le; 766 else 767 p->sw_code = linear16_to_linear8_le; 768 } 769 break; 770 771 case AUDIO_ENCODING_SLINEAR_LE: 772 if (p->precision != 16) { 773 if (mode == AUMODE_PLAY) 774 p->sw_code = linear8_to_linear16_le; 775 else 776 p->sw_code = linear16_to_linear8_le; 777 } 778 break; 779 780 case AUDIO_ENCODING_ULINEAR_BE: 781 if (p->precision == 16) { 782 if (mode == AUMODE_PLAY) 783 p->sw_code = 784 swap_bytes_change_sign16_le; 785 else 786 p->sw_code = 787 change_sign16_swap_bytes_le; 788 } else { 789 if (mode == AUMODE_PLAY) 790 p->sw_code = 791 ulinear8_to_slinear16_le; 792 else 793 p->sw_code = 794 slinear16_to_ulinear8_le; 795 } 796 break; 797 798 case AUDIO_ENCODING_ULINEAR_LE: 799 if (p->precision == 16) { 800 p->sw_code = change_sign16_le; 801 } else { 802 if (mode == AUMODE_PLAY) 803 p->sw_code = 804 ulinear8_to_slinear16_le; 805 else 806 p->sw_code = 807 slinear16_to_ulinear8_le; 808 } 809 break; 810 811 case AUDIO_ENCODING_ULAW: 812 if (mode == AUMODE_PLAY) { 813 p->sw_code = mulaw_to_slinear16_le; 814 } else { 815 p->sw_code = slinear16_to_mulaw_le; 816 } 817 break; 818 819 case AUDIO_ENCODING_ALAW: 820 if (mode == AUMODE_PLAY) { 821 p->sw_code = alaw_to_slinear16_le; 822 } else { 823 p->sw_code = slinear16_to_alaw_le; 824 } 825 break; 826 827 default: 828 return (EINVAL); 829 } 830 831 if (IS_FIXED_RATE(sc->codec_if)) { 832 p->hw_sample_rate = AC97_SINGLE_RATE; 833 /* If hw_sample_rate is changed, aurateconv works. */ 834 } else { 835 if (auich_set_rate(sc, mode, p->sample_rate)) 836 return EINVAL; 837 } 838 if (mode == AUMODE_PLAY) { 839 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 840 control &= ~ICH_PCM246_MASK; 841 if (p->channels == 4) { 842 control |= ICH_PCM4; 843 } else if (p->channels == 6) { 844 control |= ICH_PCM6; 845 } 846 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 847 } 848 } 849 850 return (0); 851 } 852 853 int 854 auich_round_blocksize(void *v, int blk) 855 { 856 857 return (blk & ~0x3f); /* keep good alignment */ 858 } 859 860 int 861 auich_halt_output(void *v) 862 { 863 struct auich_softc *sc = v; 864 865 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 866 867 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 868 869 return (0); 870 } 871 872 int 873 auich_halt_input(void *v) 874 { 875 struct auich_softc *sc = v; 876 877 DPRINTF(ICH_DEBUG_DMA, 878 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 879 880 /* XXX halt both unless known otherwise */ 881 882 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 883 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 884 885 return (0); 886 } 887 888 int 889 auich_getdev(void *v, struct audio_device *adp) 890 { 891 struct auich_softc *sc = v; 892 893 *adp = sc->sc_audev; 894 return (0); 895 } 896 897 int 898 auich_set_port(void *v, mixer_ctrl_t *cp) 899 { 900 struct auich_softc *sc = v; 901 902 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 903 } 904 905 int 906 auich_get_port(void *v, mixer_ctrl_t *cp) 907 { 908 struct auich_softc *sc = v; 909 910 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 911 } 912 913 int 914 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 915 { 916 struct auich_softc *sc = v; 917 918 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 919 } 920 921 void * 922 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 923 int flags) 924 { 925 struct auich_softc *sc = v; 926 struct auich_dma *p; 927 int error; 928 929 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 930 return (NULL); 931 932 p = malloc(sizeof(*p), pool, flags|M_ZERO); 933 if (p == NULL) 934 return (NULL); 935 936 error = auich_allocmem(sc, size, 0, p); 937 if (error) { 938 free(p, pool); 939 return (NULL); 940 } 941 942 p->next = sc->sc_dmas; 943 sc->sc_dmas = p; 944 945 return (KERNADDR(p)); 946 } 947 948 void 949 auich_freem(void *v, void *ptr, struct malloc_type *pool) 950 { 951 struct auich_softc *sc = v; 952 struct auich_dma *p, **pp; 953 954 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 955 if (KERNADDR(p) == ptr) { 956 auich_freemem(sc, p); 957 *pp = p->next; 958 free(p, pool); 959 return; 960 } 961 } 962 } 963 964 size_t 965 auich_round_buffersize(void *v, int direction, size_t size) 966 { 967 968 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 969 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 970 971 return size; 972 } 973 974 paddr_t 975 auich_mappage(void *v, void *mem, off_t off, int prot) 976 { 977 struct auich_softc *sc = v; 978 struct auich_dma *p; 979 980 if (off < 0) 981 return (-1); 982 983 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 984 ; 985 if (!p) 986 return (-1); 987 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 988 off, prot, BUS_DMA_WAITOK)); 989 } 990 991 int 992 auich_get_props(void *v) 993 { 994 struct auich_softc *sc = v; 995 int props; 996 997 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 998 /* 999 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1000 * rate because of aurateconv. Applications can't know what rate the 1001 * device can process in the case of mmap(). 1002 */ 1003 if (!IS_FIXED_RATE(sc->codec_if)) 1004 props |= AUDIO_PROP_MMAP; 1005 return props; 1006 } 1007 1008 int 1009 auich_intr(void *v) 1010 { 1011 struct auich_softc *sc = v; 1012 int ret = 0, sts, gsts, i, qptr; 1013 1014 #ifdef DIAGNOSTIC 1015 int csts; 1016 #endif 1017 1018 #ifdef DIAGNOSTIC 1019 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1020 if (csts & PCI_STATUS_MASTER_ABORT) { 1021 printf("auich_intr: PCI master abort\n"); 1022 } 1023 #endif 1024 1025 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 1026 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 1027 1028 if (gsts & ICH_POINT) { 1029 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 1030 DPRINTF(ICH_DEBUG_DMA, 1031 ("auich_intr: osts=0x%x\n", sts)); 1032 1033 if (sts & ICH_FIFOE) { 1034 printf("%s: fifo underrun # %u\n", 1035 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1036 } 1037 1038 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1039 if (sts & (ICH_LVBCI | ICH_CELV)) { 1040 struct auich_dmalist *q; 1041 1042 qptr = sc->ptr_pcmo; 1043 1044 while (qptr != i) { 1045 q = &sc->dmalist_pcmo[qptr]; 1046 1047 q->base = sc->pcmo_p; 1048 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1049 DPRINTF(ICH_DEBUG_DMA, 1050 ("auich_intr: %p, %p = %x @ 0x%x\n", 1051 &sc->dmalist_pcmo[i], q, 1052 sc->pcmo_blksize / 2, sc->pcmo_p)); 1053 1054 sc->pcmo_p += sc->pcmo_blksize; 1055 if (sc->pcmo_p >= sc->pcmo_end) 1056 sc->pcmo_p = sc->pcmo_start; 1057 1058 if (++qptr == ICH_DMALIST_MAX) 1059 qptr = 0; 1060 } 1061 1062 sc->ptr_pcmo = qptr; 1063 bus_space_write_1(sc->iot, sc->aud_ioh, 1064 ICH_PCMO + ICH_LVI, 1065 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1066 } 1067 1068 if (sts & ICH_BCIS && sc->sc_pintr) 1069 sc->sc_pintr(sc->sc_parg); 1070 1071 /* int ack */ 1072 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1073 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1074 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1075 ret++; 1076 } 1077 1078 if (gsts & ICH_PIINT) { 1079 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1080 DPRINTF(ICH_DEBUG_DMA, 1081 ("auich_intr: ists=0x%x\n", sts)); 1082 1083 if (sts & ICH_FIFOE) { 1084 printf("%s: fifo overrun # %u\n", 1085 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1086 } 1087 1088 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1089 if (sts & (ICH_LVBCI | ICH_CELV)) { 1090 struct auich_dmalist *q; 1091 1092 qptr = sc->ptr_pcmi; 1093 1094 while (qptr != i) { 1095 q = &sc->dmalist_pcmi[qptr]; 1096 1097 q->base = sc->pcmi_p; 1098 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1099 DPRINTF(ICH_DEBUG_DMA, 1100 ("auich_intr: %p, %p = %x @ 0x%x\n", 1101 &sc->dmalist_pcmi[i], q, 1102 sc->pcmi_blksize / 2, sc->pcmi_p)); 1103 1104 sc->pcmi_p += sc->pcmi_blksize; 1105 if (sc->pcmi_p >= sc->pcmi_end) 1106 sc->pcmi_p = sc->pcmi_start; 1107 1108 if (++qptr == ICH_DMALIST_MAX) 1109 qptr = 0; 1110 } 1111 1112 sc->ptr_pcmi = qptr; 1113 bus_space_write_1(sc->iot, sc->aud_ioh, 1114 ICH_PCMI + ICH_LVI, 1115 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1116 } 1117 1118 if (sts & ICH_BCIS && sc->sc_rintr) 1119 sc->sc_rintr(sc->sc_rarg); 1120 1121 /* int ack */ 1122 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1123 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1124 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1125 ret++; 1126 } 1127 1128 if (gsts & ICH_MIINT) { 1129 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1130 DPRINTF(ICH_DEBUG_DMA, 1131 ("auich_intr: ists=0x%x\n", sts)); 1132 if (sts & ICH_FIFOE) 1133 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1134 1135 /* TODO mic input DMA */ 1136 1137 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1138 } 1139 1140 return ret; 1141 } 1142 1143 int 1144 auich_trigger_output(void *v, void *start, void *end, int blksize, 1145 void (*intr)(void *), void *arg, struct audio_params *param) 1146 { 1147 struct auich_softc *sc = v; 1148 struct auich_dmalist *q; 1149 struct auich_dma *p; 1150 size_t size; 1151 #ifdef DIAGNOSTIC 1152 int csts; 1153 #endif 1154 1155 DPRINTF(ICH_DEBUG_DMA, 1156 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1157 start, end, blksize, intr, arg, param)); 1158 1159 sc->sc_pintr = intr; 1160 sc->sc_parg = arg; 1161 #ifdef DIAGNOSTIC 1162 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1163 if (csts & PCI_STATUS_MASTER_ABORT) { 1164 printf("auich_trigger_output: PCI master abort\n"); 1165 } 1166 #endif 1167 1168 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1169 ; 1170 if (!p) { 1171 printf("auich_trigger_output: bad addr %p\n", start); 1172 return (EINVAL); 1173 } 1174 1175 size = (size_t)((caddr_t)end - (caddr_t)start); 1176 1177 /* 1178 * The logic behind this is: 1179 * setup one buffer to play, then LVI dump out the rest 1180 * to the scatter-gather chain. 1181 */ 1182 sc->pcmo_start = DMAADDR(p); 1183 sc->pcmo_p = sc->pcmo_start + blksize; 1184 sc->pcmo_end = sc->pcmo_start + size; 1185 sc->pcmo_blksize = blksize; 1186 1187 sc->ptr_pcmo = 0; 1188 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1189 q->base = sc->pcmo_start; 1190 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1191 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1192 sc->ptr_pcmo = 0; 1193 1194 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1195 sc->sc_cddma + ICH_PCMO_OFF(0)); 1196 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1197 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1198 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1199 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1200 1201 return (0); 1202 } 1203 1204 int 1205 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1206 void *v; 1207 void *start, *end; 1208 int blksize; 1209 void (*intr)(void *); 1210 void *arg; 1211 struct audio_params *param; 1212 { 1213 struct auich_softc *sc = v; 1214 struct auich_dmalist *q; 1215 struct auich_dma *p; 1216 size_t size; 1217 #ifdef DIAGNOSTIC 1218 int csts; 1219 #endif 1220 1221 DPRINTF(ICH_DEBUG_DMA, 1222 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1223 start, end, blksize, intr, arg, param)); 1224 1225 sc->sc_rintr = intr; 1226 sc->sc_rarg = arg; 1227 1228 #ifdef DIAGNOSTIC 1229 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1230 if (csts & PCI_STATUS_MASTER_ABORT) { 1231 printf("auich_trigger_input: PCI master abort\n"); 1232 } 1233 #endif 1234 1235 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1236 ; 1237 if (!p) { 1238 printf("auich_trigger_input: bad addr %p\n", start); 1239 return (EINVAL); 1240 } 1241 1242 size = (size_t)((caddr_t)end - (caddr_t)start); 1243 1244 /* 1245 * The logic behind this is: 1246 * setup one buffer to play, then LVI dump out the rest 1247 * to the scatter-gather chain. 1248 */ 1249 sc->pcmi_start = DMAADDR(p); 1250 sc->pcmi_p = sc->pcmi_start + blksize; 1251 sc->pcmi_end = sc->pcmi_start + size; 1252 sc->pcmi_blksize = blksize; 1253 1254 sc->ptr_pcmi = 0; 1255 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1256 q->base = sc->pcmi_start; 1257 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1258 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1259 sc->ptr_pcmi = 0; 1260 1261 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1262 sc->sc_cddma + ICH_PCMI_OFF(0)); 1263 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1264 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1265 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1266 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1267 1268 return (0); 1269 } 1270 1271 int 1272 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1273 struct auich_dma *p) 1274 { 1275 int error; 1276 1277 p->size = size; 1278 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1279 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1280 &p->nsegs, BUS_DMA_NOWAIT); 1281 if (error) 1282 return (error); 1283 1284 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1285 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1286 if (error) 1287 goto free; 1288 1289 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1290 0, BUS_DMA_NOWAIT, &p->map); 1291 if (error) 1292 goto unmap; 1293 1294 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1295 BUS_DMA_NOWAIT); 1296 if (error) 1297 goto destroy; 1298 return (0); 1299 1300 destroy: 1301 bus_dmamap_destroy(sc->dmat, p->map); 1302 unmap: 1303 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1304 free: 1305 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1306 return (error); 1307 } 1308 1309 int 1310 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1311 { 1312 1313 bus_dmamap_unload(sc->dmat, p->map); 1314 bus_dmamap_destroy(sc->dmat, p->map); 1315 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1316 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1317 return (0); 1318 } 1319 1320 int 1321 auich_alloc_cdata(struct auich_softc *sc) 1322 { 1323 bus_dma_segment_t seg; 1324 int error, rseg; 1325 1326 /* 1327 * Allocate the control data structure, and create and load the 1328 * DMA map for it. 1329 */ 1330 if ((error = bus_dmamem_alloc(sc->dmat, 1331 sizeof(struct auich_cdata), 1332 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1333 printf("%s: unable to allocate control data, error = %d\n", 1334 sc->sc_dev.dv_xname, error); 1335 goto fail_0; 1336 } 1337 1338 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1339 sizeof(struct auich_cdata), 1340 (caddr_t *) &sc->sc_cdata, 1341 sc->sc_dmamap_flags)) != 0) { 1342 printf("%s: unable to map control data, error = %d\n", 1343 sc->sc_dev.dv_xname, error); 1344 goto fail_1; 1345 } 1346 1347 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1348 sizeof(struct auich_cdata), 0, 0, 1349 &sc->sc_cddmamap)) != 0) { 1350 printf("%s: unable to create control data DMA map, " 1351 "error = %d\n", sc->sc_dev.dv_xname, error); 1352 goto fail_2; 1353 } 1354 1355 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1356 sc->sc_cdata, sizeof(struct auich_cdata), 1357 NULL, 0)) != 0) { 1358 printf("%s: unable tp load control data DMA map, " 1359 "error = %d\n", sc->sc_dev.dv_xname, error); 1360 goto fail_3; 1361 } 1362 1363 return (0); 1364 1365 fail_3: 1366 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1367 fail_2: 1368 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1369 sizeof(struct auich_cdata)); 1370 fail_1: 1371 bus_dmamem_free(sc->dmat, &seg, rseg); 1372 fail_0: 1373 return (error); 1374 } 1375 1376 void 1377 auich_powerhook(int why, void *addr) 1378 { 1379 struct auich_softc *sc = (struct auich_softc *)addr; 1380 1381 switch (why) { 1382 case PWR_SUSPEND: 1383 case PWR_STANDBY: 1384 /* Power down */ 1385 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1386 sc->sc_suspend = why; 1387 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1388 break; 1389 1390 case PWR_RESUME: 1391 /* Wake up */ 1392 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1393 if (sc->sc_suspend == PWR_RESUME) { 1394 printf("%s: resume without suspend.\n", 1395 sc->sc_dev.dv_xname); 1396 sc->sc_suspend = why; 1397 return; 1398 } 1399 sc->sc_suspend = why; 1400 auich_reset_codec(sc); 1401 DELAY(1000); 1402 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1403 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1404 break; 1405 1406 case PWR_SOFTSUSPEND: 1407 case PWR_SOFTSTANDBY: 1408 case PWR_SOFTRESUME: 1409 break; 1410 } 1411 } 1412 1413 1414 /* -------------------------------------------------------------------- */ 1415 /* Calibrate card (some boards are overclocked and need scaling) */ 1416 1417 void 1418 auich_calibrate(struct auich_softc *sc) 1419 { 1420 struct timeval t1, t2; 1421 u_int8_t ociv, nciv; 1422 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1423 void *temp_buffer; 1424 struct auich_dma *p; 1425 1426 /* 1427 * Grab audio from input for fixed interval and compare how 1428 * much we actually get with what we expect. Interval needs 1429 * to be sufficiently short that no interrupts are 1430 * generated. 1431 */ 1432 1433 /* Setup a buffer */ 1434 bytes = 16000; 1435 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1436 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1437 ; 1438 if (p == NULL) { 1439 printf("auich_calibrate: bad address %p\n", temp_buffer); 1440 return; 1441 } 1442 sc->dmalist_pcmi[0].base = DMAADDR(p); 1443 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size); 1444 1445 /* 1446 * our data format is stereo, 16 bit so each sample is 4 bytes. 1447 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1448 * we're going to start recording with interrupts disabled and measure 1449 * the time taken for one block to complete. we know the block size, 1450 * we know the time in microseconds, we calculate the sample rate: 1451 * 1452 * actual_rate [bps] = bytes / (time [s] * 4) 1453 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1454 * actual_rate [Hz] = (bytes * 250000) / time [us] 1455 */ 1456 1457 /* prepare */ 1458 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1459 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1460 sc->sc_cddma + ICH_PCMI_OFF(0)); 1461 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1462 (0 - 1) & ICH_LVI_MASK); 1463 1464 /* start */ 1465 microtime(&t1); 1466 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1467 1468 /* wait */ 1469 do { 1470 microtime(&t2); 1471 if (t2.tv_sec - t1.tv_sec > 1) 1472 break; 1473 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1474 ICH_PCMI + ICH_CIV); 1475 } while (nciv == ociv); 1476 1477 /* stop */ 1478 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1479 1480 /* reset */ 1481 DELAY(100); 1482 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1483 1484 /* turn time delta into us */ 1485 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1486 1487 auich_freem(sc, temp_buffer, M_DEVBUF); 1488 1489 if (nciv == ociv) { 1490 printf("%s: ac97 link rate calibration timed out after %d us\n", 1491 sc->sc_dev.dv_xname, wait_us); 1492 return; 1493 } 1494 1495 actual_48k_rate = (bytes * 250000U) / wait_us; 1496 1497 if (actual_48k_rate <= 48500) 1498 ac97rate = 48000; 1499 else 1500 ac97rate = actual_48k_rate; 1501 1502 printf("%s: measured ac97 link rate at %d Hz", 1503 sc->sc_dev.dv_xname, actual_48k_rate); 1504 if (ac97rate != actual_48k_rate) 1505 printf(", will use %d Hz", ac97rate); 1506 printf("\n"); 1507 1508 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1509 } 1510
Indexes created Wed Oct 22 13:09:56 GMT 2025