auich.c revision 1.48
1 /* $NetBSD: auich.c,v 1.48 2003/10/23 17:14:54 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * 108 * TODO: 109 * - Add support for the dedicated microphone input. 110 * 111 * NOTE: 112 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 113 * It causes PCI master abort and hangups until cold reboot. 114 * http://www.intel.com/design/chipsets/specupdt/245051.htm 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.48 2003/10/23 17:14:54 kent Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/kernel.h> 123 #include <sys/malloc.h> 124 #include <sys/device.h> 125 #include <sys/fcntl.h> 126 #include <sys/proc.h> 127 128 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 129 130 #include <dev/pci/pcidevs.h> 131 #include <dev/pci/pcivar.h> 132 #include <dev/pci/auichreg.h> 133 134 #include <sys/audioio.h> 135 #include <dev/audio_if.h> 136 #include <dev/mulaw.h> 137 #include <dev/auconv.h> 138 139 #include <machine/bus.h> 140 141 #include <dev/ic/ac97reg.h> 142 #include <dev/ic/ac97var.h> 143 144 struct auich_dma { 145 bus_dmamap_t map; 146 caddr_t addr; 147 bus_dma_segment_t segs[1]; 148 int nsegs; 149 size_t size; 150 struct auich_dma *next; 151 }; 152 153 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 154 #define KERNADDR(p) ((void *)((p)->addr)) 155 156 struct auich_cdata { 157 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 158 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 159 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 160 }; 161 162 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 163 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 164 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 165 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 166 167 struct auich_softc { 168 struct device sc_dev; 169 void *sc_ih; 170 171 audio_device_t sc_audev; 172 173 bus_space_tag_t iot; 174 bus_space_handle_t mix_ioh; 175 bus_space_handle_t aud_ioh; 176 bus_dma_tag_t dmat; 177 178 struct ac97_codec_if *codec_if; 179 struct ac97_host_if host_if; 180 181 /* DMA scatter-gather lists. */ 182 bus_dmamap_t sc_cddmamap; 183 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 184 185 struct auich_cdata *sc_cdata; 186 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 187 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 188 #define dmalist_mici sc_cdata->ic_dmalist_mici 189 190 int ptr_pcmo, 191 ptr_pcmi, 192 ptr_mici; 193 194 /* i/o buffer pointers */ 195 u_int32_t pcmo_start, pcmo_p, pcmo_end; 196 int pcmo_blksize, pcmo_fifoe; 197 198 u_int32_t pcmi_start, pcmi_p, pcmi_end; 199 int pcmi_blksize, pcmi_fifoe; 200 201 u_int32_t mici_start, mici_p, mici_end; 202 int mici_blksize, mici_fifoe; 203 204 struct auich_dma *sc_dmas; 205 206 #ifdef DIAGNOSTIC 207 pci_chipset_tag_t sc_pc; 208 pcitag_t sc_pt; 209 #endif 210 /* SiS 7012 hack */ 211 int sc_sample_size; 212 int sc_sts_reg; 213 /* 440MX workaround */ 214 int sc_dmamap_flags; 215 216 void (*sc_pintr)(void *); 217 void *sc_parg; 218 219 void (*sc_rintr)(void *); 220 void *sc_rarg; 221 222 /* Power Management */ 223 void *sc_powerhook; 224 int sc_suspend; 225 u_int16_t ext_status; 226 }; 227 228 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 229 & AC97_EXT_AUDIO_VRA) 230 #define SUPPORTS_4CH(codec) ((codec)->vtbl->get_extcaps(codec) \ 231 & AC97_EXT_AUDIO_SDAC) 232 #define AC97_6CH_DACS (AC97_EXT_AUDIO_SDAC | AC97_EXT_AUDIO_CDAC \ 233 | AC97_EXT_AUDIO_LDAC) 234 #define SUPPORTS_6CH(codec) (((codec)->vtbl->get_extcaps(codec) \ 235 & AC97_6CH_DACS) == AC97_6CH_DACS) 236 237 /* Debug */ 238 #ifdef AUDIO_DEBUG 239 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 240 int auich_debug = 0xfffe; 241 #define ICH_DEBUG_CODECIO 0x0001 242 #define ICH_DEBUG_DMA 0x0002 243 #define ICH_DEBUG_PARAM 0x0004 244 #else 245 #define DPRINTF(x,y) /* nothing */ 246 #endif 247 248 int auich_match(struct device *, struct cfdata *, void *); 249 void auich_attach(struct device *, struct device *, void *); 250 int auich_intr(void *); 251 252 CFATTACH_DECL(auich, sizeof(struct auich_softc), 253 auich_match, auich_attach, NULL, NULL); 254 255 int auich_open(void *, int); 256 void auich_close(void *); 257 int auich_query_encoding(void *, struct audio_encoding *); 258 int auich_set_params(void *, int, int, struct audio_params *, 259 struct audio_params *); 260 int auich_round_blocksize(void *, int); 261 int auich_halt_output(void *); 262 int auich_halt_input(void *); 263 int auich_getdev(void *, struct audio_device *); 264 int auich_set_port(void *, mixer_ctrl_t *); 265 int auich_get_port(void *, mixer_ctrl_t *); 266 int auich_query_devinfo(void *, mixer_devinfo_t *); 267 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 268 void auich_freem(void *, void *, struct malloc_type *); 269 size_t auich_round_buffersize(void *, int, size_t); 270 paddr_t auich_mappage(void *, void *, off_t, int); 271 int auich_get_props(void *); 272 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 273 void *, struct audio_params *); 274 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 275 void *, struct audio_params *); 276 277 int auich_alloc_cdata(struct auich_softc *); 278 279 int auich_allocmem(struct auich_softc *, size_t, size_t, 280 struct auich_dma *); 281 int auich_freemem(struct auich_softc *, struct auich_dma *); 282 283 void auich_powerhook(int, void *); 284 int auich_set_rate(struct auich_softc *, int, u_long); 285 void auich_finish_attach(struct device *); 286 void auich_calibrate(struct auich_softc *); 287 288 289 struct audio_hw_if auich_hw_if = { 290 auich_open, 291 auich_close, 292 NULL, /* drain */ 293 auich_query_encoding, 294 auich_set_params, 295 auich_round_blocksize, 296 NULL, /* commit_setting */ 297 NULL, /* init_output */ 298 NULL, /* init_input */ 299 NULL, /* start_output */ 300 NULL, /* start_input */ 301 auich_halt_output, 302 auich_halt_input, 303 NULL, /* speaker_ctl */ 304 auich_getdev, 305 NULL, /* getfd */ 306 auich_set_port, 307 auich_get_port, 308 auich_query_devinfo, 309 auich_allocm, 310 auich_freem, 311 auich_round_buffersize, 312 auich_mappage, 313 auich_get_props, 314 auich_trigger_output, 315 auich_trigger_input, 316 NULL, /* dev_ioctl */ 317 }; 318 319 int auich_attach_codec(void *, struct ac97_codec_if *); 320 int auich_read_codec(void *, u_int8_t, u_int16_t *); 321 int auich_write_codec(void *, u_int8_t, u_int16_t); 322 void auich_reset_codec(void *); 323 324 static const struct auich_devtype { 325 int vendor; 326 int product; 327 const char *name; 328 const char *shortname; /* must be less than 11 characters */ 329 } auich_devices[] = { 330 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 331 "i82801AA (ICH) AC-97 Audio", "ICH" }, 332 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 333 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 334 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 335 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 336 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 337 "i82440MX AC-97 Audio", "440MX" }, 338 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 339 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 340 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 341 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 342 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 343 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 344 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 345 "SiS 7012 AC-97 Audio", "SiS7012" }, 346 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 347 "nForce MCP AC-97 Audio", "nForce" }, 348 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 349 "nForce2 MCP-T AC-97 Audio", "nForce2" }, 350 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 351 "nForce3 MCP-T AC-97 Audio", "nForce3" }, 352 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 353 "AMD768 AC-97 Audio", "AMD768" }, 354 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 355 "AMD8111 AC-97 Audio", "AMD8111" }, 356 { 0, 0, 357 NULL, NULL }, 358 }; 359 360 static const struct auich_devtype * 361 auich_lookup(struct pci_attach_args *pa) 362 { 363 const struct auich_devtype *d; 364 365 for (d = auich_devices; d->name != NULL; d++) { 366 if (PCI_VENDOR(pa->pa_id) == d->vendor 367 && PCI_PRODUCT(pa->pa_id) == d->product) 368 return (d); 369 } 370 371 return (NULL); 372 } 373 374 int 375 auich_match(struct device *parent, struct cfdata *match, void *aux) 376 { 377 struct pci_attach_args *pa = aux; 378 379 if (auich_lookup(pa) != NULL) 380 return (1); 381 382 return (0); 383 } 384 385 void 386 auich_attach(struct device *parent, struct device *self, void *aux) 387 { 388 struct auich_softc *sc = (struct auich_softc *)self; 389 struct pci_attach_args *pa = aux; 390 pci_intr_handle_t ih; 391 bus_size_t mix_size, aud_size; 392 pcireg_t csr; 393 const char *intrstr; 394 const struct auich_devtype *d; 395 396 aprint_naive(": Audio controller\n"); 397 398 d = auich_lookup(pa); 399 if (d == NULL) 400 panic("auich_attach: impossible"); 401 402 #ifdef DIAGNOSTIC 403 sc->sc_pc = pa->pa_pc; 404 sc->sc_pt = pa->pa_tag; 405 #endif 406 407 aprint_normal(": %s\n", d->name); 408 409 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 410 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 411 aprint_error("%s: can't map codec i/o space\n", 412 sc->sc_dev.dv_xname); 413 return; 414 } 415 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 416 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 417 aprint_error("%s: can't map device i/o space\n", 418 sc->sc_dev.dv_xname); 419 return; 420 } 421 sc->dmat = pa->pa_dmat; 422 423 /* enable bus mastering */ 424 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 425 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 426 csr | PCI_COMMAND_MASTER_ENABLE); 427 428 /* Map and establish the interrupt. */ 429 if (pci_intr_map(pa, &ih)) { 430 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 431 return; 432 } 433 intrstr = pci_intr_string(pa->pa_pc, ih); 434 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 435 auich_intr, sc); 436 if (sc->sc_ih == NULL) { 437 aprint_error("%s: can't establish interrupt", 438 sc->sc_dev.dv_xname); 439 if (intrstr != NULL) 440 aprint_normal(" at %s", intrstr); 441 aprint_normal("\n"); 442 return; 443 } 444 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 445 446 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 447 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 448 "0x%02x", PCI_REVISION(pa->pa_class)); 449 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 450 451 /* SiS 7012 needs special handling */ 452 if (d->vendor == PCI_VENDOR_SIS 453 && d->product == PCI_PRODUCT_SIS_7012_AC) { 454 sc->sc_sts_reg = ICH_PICB; 455 sc->sc_sample_size = 1; 456 } else { 457 sc->sc_sts_reg = ICH_STS; 458 sc->sc_sample_size = 2; 459 } 460 461 /* Workaround for a 440MX B-stepping erratum */ 462 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 463 if (d->vendor == PCI_VENDOR_INTEL 464 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 465 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 466 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 467 } 468 469 /* Set up DMA lists. */ 470 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 471 auich_alloc_cdata(sc); 472 473 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 474 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 475 476 sc->host_if.arg = sc; 477 sc->host_if.attach = auich_attach_codec; 478 sc->host_if.read = auich_read_codec; 479 sc->host_if.write = auich_write_codec; 480 sc->host_if.reset = auich_reset_codec; 481 482 if (ac97_attach(&sc->host_if) != 0) 483 return; 484 485 /* Watch for power change */ 486 sc->sc_suspend = PWR_RESUME; 487 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 488 489 config_interrupts(self, auich_finish_attach); 490 } 491 492 void 493 auich_finish_attach(struct device *self) 494 { 495 struct auich_softc *sc = (void *)self; 496 497 if (!IS_FIXED_RATE(sc->codec_if)) 498 auich_calibrate(sc); 499 500 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 501 } 502 503 #define ICH_CODECIO_INTERVAL 10 504 int 505 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 506 { 507 struct auich_softc *sc = v; 508 int i; 509 uint32_t status; 510 511 /* wait for an access semaphore */ 512 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 513 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 514 DELAY(ICH_CODECIO_INTERVAL)); 515 516 if (i > 0) { 517 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 518 DPRINTF(ICH_DEBUG_CODECIO, 519 ("auich_read_codec(%x, %x)\n", reg, *val)); 520 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 521 if (status & ICH_RCS) { 522 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 523 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 524 *val = 0xffff; 525 } 526 return 0; 527 } else { 528 DPRINTF(ICH_DEBUG_CODECIO, 529 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 530 return -1; 531 } 532 } 533 534 int 535 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 536 { 537 struct auich_softc *sc = v; 538 int i; 539 540 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 541 /* wait for an access semaphore */ 542 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 543 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 544 DELAY(ICH_CODECIO_INTERVAL)); 545 546 if (i > 0) { 547 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 548 return 0; 549 } else { 550 DPRINTF(ICH_DEBUG_CODECIO, 551 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 552 return -1; 553 } 554 } 555 556 int 557 auich_attach_codec(void *v, struct ac97_codec_if *cif) 558 { 559 struct auich_softc *sc = v; 560 561 sc->codec_if = cif; 562 return 0; 563 } 564 565 void 566 auich_reset_codec(void *v) 567 { 568 struct auich_softc *sc = v; 569 int i; 570 uint32_t control, status; 571 572 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 573 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 574 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 575 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 576 577 for (i = 500000; i >= 0; i--) { 578 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 579 if (status & ICH_PCR) 580 break; 581 DELAY(1); 582 } 583 if (i <= 0) { 584 printf("%s: auich_reset_codec: time out for the primary codec\n", 585 sc->sc_dev.dv_xname); 586 if (status & ICH_SCR) 587 printf("%s: auich_reset_codec: The 2nd codec is ready.\n", 588 sc->sc_dev.dv_xname); 589 if (status & ICH_S2CR) 590 printf("%s: auich_reset_codec: The 3rd codec is ready.\n", 591 sc->sc_dev.dv_xname); 592 } 593 } 594 595 int 596 auich_open(void *v, int flags) 597 { 598 return 0; 599 } 600 601 void 602 auich_close(void *v) 603 { 604 struct auich_softc *sc = v; 605 606 auich_halt_output(sc); 607 auich_halt_input(sc); 608 609 sc->sc_pintr = NULL; 610 sc->sc_rintr = NULL; 611 } 612 613 int 614 auich_query_encoding(void *v, struct audio_encoding *aep) 615 { 616 617 switch (aep->index) { 618 case 0: 619 strcpy(aep->name, AudioEulinear); 620 aep->encoding = AUDIO_ENCODING_ULINEAR; 621 aep->precision = 8; 622 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 623 return (0); 624 case 1: 625 strcpy(aep->name, AudioEmulaw); 626 aep->encoding = AUDIO_ENCODING_ULAW; 627 aep->precision = 8; 628 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 629 return (0); 630 case 2: 631 strcpy(aep->name, AudioEalaw); 632 aep->encoding = AUDIO_ENCODING_ALAW; 633 aep->precision = 8; 634 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 635 return (0); 636 case 3: 637 strcpy(aep->name, AudioEslinear); 638 aep->encoding = AUDIO_ENCODING_SLINEAR; 639 aep->precision = 8; 640 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 641 return (0); 642 case 4: 643 strcpy(aep->name, AudioEslinear_le); 644 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 645 aep->precision = 16; 646 aep->flags = 0; 647 return (0); 648 case 5: 649 strcpy(aep->name, AudioEulinear_le); 650 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 651 aep->precision = 16; 652 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 653 return (0); 654 case 6: 655 strcpy(aep->name, AudioEslinear_be); 656 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 657 aep->precision = 16; 658 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 659 return (0); 660 case 7: 661 strcpy(aep->name, AudioEulinear_be); 662 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 663 aep->precision = 16; 664 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 665 return (0); 666 default: 667 return (EINVAL); 668 } 669 } 670 671 int 672 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 673 { 674 int ret; 675 u_long ratetmp; 676 677 ratetmp = srate; 678 if (mode == AUMODE_RECORD) 679 return sc->codec_if->vtbl->set_rate(sc->codec_if, 680 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 681 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 682 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 683 if (ret) 684 return ret; 685 ratetmp = srate; 686 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 687 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 688 if (ret) 689 return ret; 690 ratetmp = srate; 691 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 692 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 693 return ret; 694 } 695 696 int 697 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 698 struct audio_params *rec) 699 { 700 struct auich_softc *sc = v; 701 struct audio_params *p; 702 int mode; 703 u_int32_t control; 704 705 for (mode = AUMODE_RECORD; mode != -1; 706 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 707 if ((setmode & mode) == 0) 708 continue; 709 710 p = mode == AUMODE_PLAY ? play : rec; 711 if (p == NULL) 712 continue; 713 714 if ((p->sample_rate != 8000) && 715 (p->sample_rate != 11025) && 716 (p->sample_rate != 12000) && 717 (p->sample_rate != 16000) && 718 (p->sample_rate != 22050) && 719 (p->sample_rate != 24000) && 720 (p->sample_rate != 32000) && 721 (p->sample_rate != 44100) && 722 (p->sample_rate != 48000)) 723 return (EINVAL); 724 725 p->factor = 1; 726 if (p->precision == 8) 727 p->factor *= 2; 728 729 p->sw_code = NULL; 730 /* setup hardware formats */ 731 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 732 p->hw_precision = 16; 733 734 if (mode == AUMODE_RECORD) { 735 if (p->channels < 1 || p->channels > 2) 736 return EINVAL; 737 } else { 738 switch (p->channels) { 739 case 1: 740 break; 741 case 2: 742 break; 743 case 4: 744 if (!SUPPORTS_4CH(sc->codec_if)) 745 return EINVAL; 746 break; 747 case 6: 748 if (!SUPPORTS_6CH(sc->codec_if)) 749 return EINVAL; 750 break; 751 default: 752 return EINVAL; 753 } 754 } 755 /* If monaural is requested, aurateconv expands a monaural 756 * stream to stereo. */ 757 if (p->channels == 1) 758 p->hw_channels = 2; 759 760 switch (p->encoding) { 761 case AUDIO_ENCODING_SLINEAR_BE: 762 if (p->precision == 16) { 763 p->sw_code = swap_bytes; 764 } else { 765 if (mode == AUMODE_PLAY) 766 p->sw_code = linear8_to_linear16_le; 767 else 768 p->sw_code = linear16_to_linear8_le; 769 } 770 break; 771 772 case AUDIO_ENCODING_SLINEAR_LE: 773 if (p->precision != 16) { 774 if (mode == AUMODE_PLAY) 775 p->sw_code = linear8_to_linear16_le; 776 else 777 p->sw_code = linear16_to_linear8_le; 778 } 779 break; 780 781 case AUDIO_ENCODING_ULINEAR_BE: 782 if (p->precision == 16) { 783 if (mode == AUMODE_PLAY) 784 p->sw_code = 785 swap_bytes_change_sign16_le; 786 else 787 p->sw_code = 788 change_sign16_swap_bytes_le; 789 } else { 790 if (mode == AUMODE_PLAY) 791 p->sw_code = 792 ulinear8_to_slinear16_le; 793 else 794 p->sw_code = 795 slinear16_to_ulinear8_le; 796 } 797 break; 798 799 case AUDIO_ENCODING_ULINEAR_LE: 800 if (p->precision == 16) { 801 p->sw_code = change_sign16_le; 802 } else { 803 if (mode == AUMODE_PLAY) 804 p->sw_code = 805 ulinear8_to_slinear16_le; 806 else 807 p->sw_code = 808 slinear16_to_ulinear8_le; 809 } 810 break; 811 812 case AUDIO_ENCODING_ULAW: 813 if (mode == AUMODE_PLAY) { 814 p->sw_code = mulaw_to_slinear16_le; 815 } else { 816 p->sw_code = slinear16_to_mulaw_le; 817 } 818 break; 819 820 case AUDIO_ENCODING_ALAW: 821 if (mode == AUMODE_PLAY) { 822 p->sw_code = alaw_to_slinear16_le; 823 } else { 824 p->sw_code = slinear16_to_alaw_le; 825 } 826 break; 827 828 default: 829 return (EINVAL); 830 } 831 832 if (IS_FIXED_RATE(sc->codec_if)) { 833 p->hw_sample_rate = AC97_SINGLE_RATE; 834 /* If hw_sample_rate is changed, aurateconv works. */ 835 } else { 836 if (auich_set_rate(sc, mode, p->sample_rate)) 837 return EINVAL; 838 } 839 if (mode == AUMODE_PLAY) { 840 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 841 control &= ~ICH_PCM246_MASK; 842 if (p->channels == 4) { 843 control |= ICH_PCM4; 844 } else if (p->channels == 6) { 845 control |= ICH_PCM6; 846 } 847 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 848 } 849 } 850 851 return (0); 852 } 853 854 int 855 auich_round_blocksize(void *v, int blk) 856 { 857 858 return (blk & ~0x3f); /* keep good alignment */ 859 } 860 861 int 862 auich_halt_output(void *v) 863 { 864 struct auich_softc *sc = v; 865 866 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 867 868 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 869 870 return (0); 871 } 872 873 int 874 auich_halt_input(void *v) 875 { 876 struct auich_softc *sc = v; 877 878 DPRINTF(ICH_DEBUG_DMA, 879 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 880 881 /* XXX halt both unless known otherwise */ 882 883 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 884 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 885 886 return (0); 887 } 888 889 int 890 auich_getdev(void *v, struct audio_device *adp) 891 { 892 struct auich_softc *sc = v; 893 894 *adp = sc->sc_audev; 895 return (0); 896 } 897 898 int 899 auich_set_port(void *v, mixer_ctrl_t *cp) 900 { 901 struct auich_softc *sc = v; 902 903 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 904 } 905 906 int 907 auich_get_port(void *v, mixer_ctrl_t *cp) 908 { 909 struct auich_softc *sc = v; 910 911 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 912 } 913 914 int 915 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 916 { 917 struct auich_softc *sc = v; 918 919 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 920 } 921 922 void * 923 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 924 int flags) 925 { 926 struct auich_softc *sc = v; 927 struct auich_dma *p; 928 int error; 929 930 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 931 return (NULL); 932 933 p = malloc(sizeof(*p), pool, flags|M_ZERO); 934 if (p == NULL) 935 return (NULL); 936 937 error = auich_allocmem(sc, size, 0, p); 938 if (error) { 939 free(p, pool); 940 return (NULL); 941 } 942 943 p->next = sc->sc_dmas; 944 sc->sc_dmas = p; 945 946 return (KERNADDR(p)); 947 } 948 949 void 950 auich_freem(void *v, void *ptr, struct malloc_type *pool) 951 { 952 struct auich_softc *sc = v; 953 struct auich_dma *p, **pp; 954 955 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 956 if (KERNADDR(p) == ptr) { 957 auich_freemem(sc, p); 958 *pp = p->next; 959 free(p, pool); 960 return; 961 } 962 } 963 } 964 965 size_t 966 auich_round_buffersize(void *v, int direction, size_t size) 967 { 968 969 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 970 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 971 972 return size; 973 } 974 975 paddr_t 976 auich_mappage(void *v, void *mem, off_t off, int prot) 977 { 978 struct auich_softc *sc = v; 979 struct auich_dma *p; 980 981 if (off < 0) 982 return (-1); 983 984 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 985 ; 986 if (!p) 987 return (-1); 988 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 989 off, prot, BUS_DMA_WAITOK)); 990 } 991 992 int 993 auich_get_props(void *v) 994 { 995 struct auich_softc *sc = v; 996 int props; 997 998 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 999 /* 1000 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1001 * rate because of aurateconv. Applications can't know what rate the 1002 * device can process in the case of mmap(). 1003 */ 1004 if (!IS_FIXED_RATE(sc->codec_if)) 1005 props |= AUDIO_PROP_MMAP; 1006 return props; 1007 } 1008 1009 int 1010 auich_intr(void *v) 1011 { 1012 struct auich_softc *sc = v; 1013 int ret = 0, sts, gsts, i, qptr; 1014 1015 #ifdef DIAGNOSTIC 1016 int csts; 1017 #endif 1018 1019 #ifdef DIAGNOSTIC 1020 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1021 if (csts & PCI_STATUS_MASTER_ABORT) { 1022 printf("auich_intr: PCI master abort\n"); 1023 } 1024 #endif 1025 1026 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 1027 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 1028 1029 if (gsts & ICH_POINT) { 1030 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 1031 DPRINTF(ICH_DEBUG_DMA, 1032 ("auich_intr: osts=0x%x\n", sts)); 1033 1034 if (sts & ICH_FIFOE) { 1035 printf("%s: fifo underrun # %u\n", 1036 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1037 } 1038 1039 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1040 if (sts & (ICH_LVBCI | ICH_CELV)) { 1041 struct auich_dmalist *q; 1042 1043 qptr = sc->ptr_pcmo; 1044 1045 while (qptr != i) { 1046 q = &sc->dmalist_pcmo[qptr]; 1047 1048 q->base = sc->pcmo_p; 1049 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1050 DPRINTF(ICH_DEBUG_DMA, 1051 ("auich_intr: %p, %p = %x @ 0x%x\n", 1052 &sc->dmalist_pcmo[i], q, 1053 sc->pcmo_blksize / 2, sc->pcmo_p)); 1054 1055 sc->pcmo_p += sc->pcmo_blksize; 1056 if (sc->pcmo_p >= sc->pcmo_end) 1057 sc->pcmo_p = sc->pcmo_start; 1058 1059 if (++qptr == ICH_DMALIST_MAX) 1060 qptr = 0; 1061 } 1062 1063 sc->ptr_pcmo = qptr; 1064 bus_space_write_1(sc->iot, sc->aud_ioh, 1065 ICH_PCMO + ICH_LVI, 1066 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1067 } 1068 1069 if (sts & ICH_BCIS && sc->sc_pintr) 1070 sc->sc_pintr(sc->sc_parg); 1071 1072 /* int ack */ 1073 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1074 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1075 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1076 ret++; 1077 } 1078 1079 if (gsts & ICH_PIINT) { 1080 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1081 DPRINTF(ICH_DEBUG_DMA, 1082 ("auich_intr: ists=0x%x\n", sts)); 1083 1084 if (sts & ICH_FIFOE) { 1085 printf("%s: fifo overrun # %u\n", 1086 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1087 } 1088 1089 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1090 if (sts & (ICH_LVBCI | ICH_CELV)) { 1091 struct auich_dmalist *q; 1092 1093 qptr = sc->ptr_pcmi; 1094 1095 while (qptr != i) { 1096 q = &sc->dmalist_pcmi[qptr]; 1097 1098 q->base = sc->pcmi_p; 1099 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1100 DPRINTF(ICH_DEBUG_DMA, 1101 ("auich_intr: %p, %p = %x @ 0x%x\n", 1102 &sc->dmalist_pcmi[i], q, 1103 sc->pcmi_blksize / 2, sc->pcmi_p)); 1104 1105 sc->pcmi_p += sc->pcmi_blksize; 1106 if (sc->pcmi_p >= sc->pcmi_end) 1107 sc->pcmi_p = sc->pcmi_start; 1108 1109 if (++qptr == ICH_DMALIST_MAX) 1110 qptr = 0; 1111 } 1112 1113 sc->ptr_pcmi = qptr; 1114 bus_space_write_1(sc->iot, sc->aud_ioh, 1115 ICH_PCMI + ICH_LVI, 1116 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1117 } 1118 1119 if (sts & ICH_BCIS && sc->sc_rintr) 1120 sc->sc_rintr(sc->sc_rarg); 1121 1122 /* int ack */ 1123 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1124 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1125 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1126 ret++; 1127 } 1128 1129 if (gsts & ICH_MIINT) { 1130 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1131 DPRINTF(ICH_DEBUG_DMA, 1132 ("auich_intr: ists=0x%x\n", sts)); 1133 if (sts & ICH_FIFOE) 1134 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1135 1136 /* TODO mic input DMA */ 1137 1138 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1139 } 1140 1141 return ret; 1142 } 1143 1144 int 1145 auich_trigger_output(void *v, void *start, void *end, int blksize, 1146 void (*intr)(void *), void *arg, struct audio_params *param) 1147 { 1148 struct auich_softc *sc = v; 1149 struct auich_dmalist *q; 1150 struct auich_dma *p; 1151 size_t size; 1152 #ifdef DIAGNOSTIC 1153 int csts; 1154 #endif 1155 1156 DPRINTF(ICH_DEBUG_DMA, 1157 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1158 start, end, blksize, intr, arg, param)); 1159 1160 sc->sc_pintr = intr; 1161 sc->sc_parg = arg; 1162 #ifdef DIAGNOSTIC 1163 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1164 if (csts & PCI_STATUS_MASTER_ABORT) { 1165 printf("auich_trigger_output: PCI master abort\n"); 1166 } 1167 #endif 1168 1169 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1170 ; 1171 if (!p) { 1172 printf("auich_trigger_output: bad addr %p\n", start); 1173 return (EINVAL); 1174 } 1175 1176 size = (size_t)((caddr_t)end - (caddr_t)start); 1177 1178 /* 1179 * The logic behind this is: 1180 * setup one buffer to play, then LVI dump out the rest 1181 * to the scatter-gather chain. 1182 */ 1183 sc->pcmo_start = DMAADDR(p); 1184 sc->pcmo_p = sc->pcmo_start + blksize; 1185 sc->pcmo_end = sc->pcmo_start + size; 1186 sc->pcmo_blksize = blksize; 1187 1188 sc->ptr_pcmo = 0; 1189 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1190 q->base = sc->pcmo_start; 1191 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1192 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1193 sc->ptr_pcmo = 0; 1194 1195 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1196 sc->sc_cddma + ICH_PCMO_OFF(0)); 1197 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1198 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1199 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1200 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1201 1202 return (0); 1203 } 1204 1205 int 1206 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1207 void *v; 1208 void *start, *end; 1209 int blksize; 1210 void (*intr)(void *); 1211 void *arg; 1212 struct audio_params *param; 1213 { 1214 struct auich_softc *sc = v; 1215 struct auich_dmalist *q; 1216 struct auich_dma *p; 1217 size_t size; 1218 #ifdef DIAGNOSTIC 1219 int csts; 1220 #endif 1221 1222 DPRINTF(ICH_DEBUG_DMA, 1223 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1224 start, end, blksize, intr, arg, param)); 1225 1226 sc->sc_rintr = intr; 1227 sc->sc_rarg = arg; 1228 1229 #ifdef DIAGNOSTIC 1230 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1231 if (csts & PCI_STATUS_MASTER_ABORT) { 1232 printf("auich_trigger_input: PCI master abort\n"); 1233 } 1234 #endif 1235 1236 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1237 ; 1238 if (!p) { 1239 printf("auich_trigger_input: bad addr %p\n", start); 1240 return (EINVAL); 1241 } 1242 1243 size = (size_t)((caddr_t)end - (caddr_t)start); 1244 1245 /* 1246 * The logic behind this is: 1247 * setup one buffer to play, then LVI dump out the rest 1248 * to the scatter-gather chain. 1249 */ 1250 sc->pcmi_start = DMAADDR(p); 1251 sc->pcmi_p = sc->pcmi_start + blksize; 1252 sc->pcmi_end = sc->pcmi_start + size; 1253 sc->pcmi_blksize = blksize; 1254 1255 sc->ptr_pcmi = 0; 1256 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1257 q->base = sc->pcmi_start; 1258 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1259 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1260 sc->ptr_pcmi = 0; 1261 1262 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1263 sc->sc_cddma + ICH_PCMI_OFF(0)); 1264 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1265 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1266 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1267 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1268 1269 return (0); 1270 } 1271 1272 int 1273 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1274 struct auich_dma *p) 1275 { 1276 int error; 1277 1278 p->size = size; 1279 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1280 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1281 &p->nsegs, BUS_DMA_NOWAIT); 1282 if (error) 1283 return (error); 1284 1285 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1286 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1287 if (error) 1288 goto free; 1289 1290 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1291 0, BUS_DMA_NOWAIT, &p->map); 1292 if (error) 1293 goto unmap; 1294 1295 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1296 BUS_DMA_NOWAIT); 1297 if (error) 1298 goto destroy; 1299 return (0); 1300 1301 destroy: 1302 bus_dmamap_destroy(sc->dmat, p->map); 1303 unmap: 1304 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1305 free: 1306 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1307 return (error); 1308 } 1309 1310 int 1311 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1312 { 1313 1314 bus_dmamap_unload(sc->dmat, p->map); 1315 bus_dmamap_destroy(sc->dmat, p->map); 1316 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1317 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1318 return (0); 1319 } 1320 1321 int 1322 auich_alloc_cdata(struct auich_softc *sc) 1323 { 1324 bus_dma_segment_t seg; 1325 int error, rseg; 1326 1327 /* 1328 * Allocate the control data structure, and create and load the 1329 * DMA map for it. 1330 */ 1331 if ((error = bus_dmamem_alloc(sc->dmat, 1332 sizeof(struct auich_cdata), 1333 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1334 printf("%s: unable to allocate control data, error = %d\n", 1335 sc->sc_dev.dv_xname, error); 1336 goto fail_0; 1337 } 1338 1339 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1340 sizeof(struct auich_cdata), 1341 (caddr_t *) &sc->sc_cdata, 1342 sc->sc_dmamap_flags)) != 0) { 1343 printf("%s: unable to map control data, error = %d\n", 1344 sc->sc_dev.dv_xname, error); 1345 goto fail_1; 1346 } 1347 1348 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1349 sizeof(struct auich_cdata), 0, 0, 1350 &sc->sc_cddmamap)) != 0) { 1351 printf("%s: unable to create control data DMA map, " 1352 "error = %d\n", sc->sc_dev.dv_xname, error); 1353 goto fail_2; 1354 } 1355 1356 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1357 sc->sc_cdata, sizeof(struct auich_cdata), 1358 NULL, 0)) != 0) { 1359 printf("%s: unable tp load control data DMA map, " 1360 "error = %d\n", sc->sc_dev.dv_xname, error); 1361 goto fail_3; 1362 } 1363 1364 return (0); 1365 1366 fail_3: 1367 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1368 fail_2: 1369 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1370 sizeof(struct auich_cdata)); 1371 fail_1: 1372 bus_dmamem_free(sc->dmat, &seg, rseg); 1373 fail_0: 1374 return (error); 1375 } 1376 1377 void 1378 auich_powerhook(int why, void *addr) 1379 { 1380 struct auich_softc *sc = (struct auich_softc *)addr; 1381 1382 switch (why) { 1383 case PWR_SUSPEND: 1384 case PWR_STANDBY: 1385 /* Power down */ 1386 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1387 sc->sc_suspend = why; 1388 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1389 break; 1390 1391 case PWR_RESUME: 1392 /* Wake up */ 1393 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1394 if (sc->sc_suspend == PWR_RESUME) { 1395 printf("%s: resume without suspend.\n", 1396 sc->sc_dev.dv_xname); 1397 sc->sc_suspend = why; 1398 return; 1399 } 1400 sc->sc_suspend = why; 1401 auich_reset_codec(sc); 1402 DELAY(1000); 1403 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1404 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1405 break; 1406 1407 case PWR_SOFTSUSPEND: 1408 case PWR_SOFTSTANDBY: 1409 case PWR_SOFTRESUME: 1410 break; 1411 } 1412 } 1413 1414 1415 /* -------------------------------------------------------------------- */ 1416 /* Calibrate card (some boards are overclocked and need scaling) */ 1417 1418 void 1419 auich_calibrate(struct auich_softc *sc) 1420 { 1421 struct timeval t1, t2; 1422 u_int8_t ociv, nciv; 1423 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1424 void *temp_buffer; 1425 struct auich_dma *p; 1426 1427 /* 1428 * Grab audio from input for fixed interval and compare how 1429 * much we actually get with what we expect. Interval needs 1430 * to be sufficiently short that no interrupts are 1431 * generated. 1432 */ 1433 1434 /* Setup a buffer */ 1435 bytes = 16000; 1436 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1437 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1438 ; 1439 if (p == NULL) { 1440 printf("auich_calibrate: bad address %p\n", temp_buffer); 1441 return; 1442 } 1443 sc->dmalist_pcmi[0].base = DMAADDR(p); 1444 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size); 1445 1446 /* 1447 * our data format is stereo, 16 bit so each sample is 4 bytes. 1448 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1449 * we're going to start recording with interrupts disabled and measure 1450 * the time taken for one block to complete. we know the block size, 1451 * we know the time in microseconds, we calculate the sample rate: 1452 * 1453 * actual_rate [bps] = bytes / (time [s] * 4) 1454 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1455 * actual_rate [Hz] = (bytes * 250000) / time [us] 1456 */ 1457 1458 /* prepare */ 1459 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1460 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1461 sc->sc_cddma + ICH_PCMI_OFF(0)); 1462 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1463 (0 - 1) & ICH_LVI_MASK); 1464 1465 /* start */ 1466 microtime(&t1); 1467 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1468 1469 /* wait */ 1470 do { 1471 microtime(&t2); 1472 if (t2.tv_sec - t1.tv_sec > 1) 1473 break; 1474 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1475 ICH_PCMI + ICH_CIV); 1476 } while (nciv == ociv); 1477 1478 /* stop */ 1479 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1480 1481 /* reset */ 1482 DELAY(100); 1483 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1484 1485 /* turn time delta into us */ 1486 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1487 1488 auich_freem(sc, temp_buffer, M_DEVBUF); 1489 1490 if (nciv == ociv) { 1491 printf("%s: ac97 link rate calibration timed out after %d us\n", 1492 sc->sc_dev.dv_xname, wait_us); 1493 return; 1494 } 1495 1496 actual_48k_rate = (bytes * 250000U) / wait_us; 1497 1498 if (actual_48k_rate <= 48500) 1499 ac97rate = 48000; 1500 else 1501 ac97rate = actual_48k_rate; 1502 1503 printf("%s: measured ac97 link rate at %d Hz", 1504 sc->sc_dev.dv_xname, actual_48k_rate); 1505 if (ac97rate != actual_48k_rate) 1506 printf(", will use %d Hz", ac97rate); 1507 printf("\n"); 1508 1509 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1510 } 1511
Indexes created Thu Oct 23 18:09:57 GMT 2025