auich.c revision 1.50
1 /* $NetBSD: auich.c,v 1.50 2003/10/25 18:31:11 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * 108 * TODO: 109 * - Add support for the dedicated microphone input. 110 * 111 * NOTE: 112 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 113 * It causes PCI master abort and hangups until cold reboot. 114 * http://www.intel.com/design/chipsets/specupdt/245051.htm 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.50 2003/10/25 18:31:11 christos Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/kernel.h> 123 #include <sys/malloc.h> 124 #include <sys/device.h> 125 #include <sys/fcntl.h> 126 #include <sys/proc.h> 127 128 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 129 130 #include <dev/pci/pcidevs.h> 131 #include <dev/pci/pcivar.h> 132 #include <dev/pci/auichreg.h> 133 134 #include <sys/audioio.h> 135 #include <dev/audio_if.h> 136 #include <dev/mulaw.h> 137 #include <dev/auconv.h> 138 139 #include <machine/bus.h> 140 141 #include <dev/ic/ac97reg.h> 142 #include <dev/ic/ac97var.h> 143 144 struct auich_dma { 145 bus_dmamap_t map; 146 caddr_t addr; 147 bus_dma_segment_t segs[1]; 148 int nsegs; 149 size_t size; 150 struct auich_dma *next; 151 }; 152 153 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 154 #define KERNADDR(p) ((void *)((p)->addr)) 155 156 struct auich_cdata { 157 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 158 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 159 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 160 }; 161 162 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 163 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 164 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 165 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 166 167 struct auich_softc { 168 struct device sc_dev; 169 void *sc_ih; 170 171 audio_device_t sc_audev; 172 173 bus_space_tag_t iot; 174 bus_space_handle_t mix_ioh; 175 bus_space_handle_t aud_ioh; 176 bus_dma_tag_t dmat; 177 178 struct ac97_codec_if *codec_if; 179 struct ac97_host_if host_if; 180 181 /* DMA scatter-gather lists. */ 182 bus_dmamap_t sc_cddmamap; 183 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 184 185 struct auich_cdata *sc_cdata; 186 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 187 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 188 #define dmalist_mici sc_cdata->ic_dmalist_mici 189 190 int ptr_pcmo, 191 ptr_pcmi, 192 ptr_mici; 193 194 /* i/o buffer pointers */ 195 u_int32_t pcmo_start, pcmo_p, pcmo_end; 196 int pcmo_blksize, pcmo_fifoe; 197 198 u_int32_t pcmi_start, pcmi_p, pcmi_end; 199 int pcmi_blksize, pcmi_fifoe; 200 201 u_int32_t mici_start, mici_p, mici_end; 202 int mici_blksize, mici_fifoe; 203 204 struct auich_dma *sc_dmas; 205 206 #ifdef DIAGNOSTIC 207 pci_chipset_tag_t sc_pc; 208 pcitag_t sc_pt; 209 #endif 210 /* SiS 7012 hack */ 211 int sc_sample_size; 212 int sc_sts_reg; 213 /* 440MX workaround */ 214 int sc_dmamap_flags; 215 216 void (*sc_pintr)(void *); 217 void *sc_parg; 218 219 void (*sc_rintr)(void *); 220 void *sc_rarg; 221 222 /* Power Management */ 223 void *sc_powerhook; 224 int sc_suspend; 225 u_int16_t ext_status; 226 }; 227 228 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 229 & AC97_EXT_AUDIO_VRA) 230 #define SUPPORTS_4CH(codec) ((codec)->vtbl->get_extcaps(codec) \ 231 & AC97_EXT_AUDIO_SDAC) 232 #define AC97_6CH_DACS (AC97_EXT_AUDIO_SDAC | AC97_EXT_AUDIO_CDAC \ 233 | AC97_EXT_AUDIO_LDAC) 234 #define SUPPORTS_6CH(codec) (((codec)->vtbl->get_extcaps(codec) \ 235 & AC97_6CH_DACS) == AC97_6CH_DACS) 236 237 /* Debug */ 238 #ifdef AUDIO_DEBUG 239 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 240 int auich_debug = 0xfffe; 241 #define ICH_DEBUG_CODECIO 0x0001 242 #define ICH_DEBUG_DMA 0x0002 243 #define ICH_DEBUG_PARAM 0x0004 244 #else 245 #define DPRINTF(x,y) /* nothing */ 246 #endif 247 248 int auich_match(struct device *, struct cfdata *, void *); 249 void auich_attach(struct device *, struct device *, void *); 250 int auich_intr(void *); 251 252 CFATTACH_DECL(auich, sizeof(struct auich_softc), 253 auich_match, auich_attach, NULL, NULL); 254 255 int auich_open(void *, int); 256 void auich_close(void *); 257 int auich_query_encoding(void *, struct audio_encoding *); 258 int auich_set_params(void *, int, int, struct audio_params *, 259 struct audio_params *); 260 int auich_round_blocksize(void *, int); 261 int auich_halt_output(void *); 262 int auich_halt_input(void *); 263 int auich_getdev(void *, struct audio_device *); 264 int auich_set_port(void *, mixer_ctrl_t *); 265 int auich_get_port(void *, mixer_ctrl_t *); 266 int auich_query_devinfo(void *, mixer_devinfo_t *); 267 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 268 void auich_freem(void *, void *, struct malloc_type *); 269 size_t auich_round_buffersize(void *, int, size_t); 270 paddr_t auich_mappage(void *, void *, off_t, int); 271 int auich_get_props(void *); 272 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 273 void *, struct audio_params *); 274 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 275 void *, struct audio_params *); 276 277 int auich_alloc_cdata(struct auich_softc *); 278 279 int auich_allocmem(struct auich_softc *, size_t, size_t, 280 struct auich_dma *); 281 int auich_freemem(struct auich_softc *, struct auich_dma *); 282 283 void auich_powerhook(int, void *); 284 int auich_set_rate(struct auich_softc *, int, u_long); 285 void auich_finish_attach(struct device *); 286 void auich_calibrate(struct auich_softc *); 287 288 289 struct audio_hw_if auich_hw_if = { 290 auich_open, 291 auich_close, 292 NULL, /* drain */ 293 auich_query_encoding, 294 auich_set_params, 295 auich_round_blocksize, 296 NULL, /* commit_setting */ 297 NULL, /* init_output */ 298 NULL, /* init_input */ 299 NULL, /* start_output */ 300 NULL, /* start_input */ 301 auich_halt_output, 302 auich_halt_input, 303 NULL, /* speaker_ctl */ 304 auich_getdev, 305 NULL, /* getfd */ 306 auich_set_port, 307 auich_get_port, 308 auich_query_devinfo, 309 auich_allocm, 310 auich_freem, 311 auich_round_buffersize, 312 auich_mappage, 313 auich_get_props, 314 auich_trigger_output, 315 auich_trigger_input, 316 NULL, /* dev_ioctl */ 317 }; 318 319 int auich_attach_codec(void *, struct ac97_codec_if *); 320 int auich_read_codec(void *, u_int8_t, u_int16_t *); 321 int auich_write_codec(void *, u_int8_t, u_int16_t); 322 void auich_reset_codec(void *); 323 324 static const struct auich_devtype { 325 int vendor; 326 int product; 327 const char *name; 328 const char *shortname; /* must be less than 11 characters */ 329 } auich_devices[] = { 330 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 331 "i82801AA (ICH) AC-97 Audio", "ICH" }, 332 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 333 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 334 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 335 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 336 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 337 "i82440MX AC-97 Audio", "440MX" }, 338 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 339 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 340 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 341 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 342 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 343 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 344 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 345 "SiS 7012 AC-97 Audio", "SiS7012" }, 346 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 347 "nForce MCP AC-97 Audio", "nForce" }, 348 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 349 "nForce2 MCP-T AC-97 Audio", "nForce2" }, 350 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 351 "nForce3 MCP-T AC-97 Audio", "nForce3" }, 352 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 353 "AMD768 AC-97 Audio", "AMD768" }, 354 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 355 "AMD8111 AC-97 Audio", "AMD8111" }, 356 { 0, 0, 357 NULL, NULL }, 358 }; 359 360 static const struct auich_devtype * 361 auich_lookup(struct pci_attach_args *pa) 362 { 363 const struct auich_devtype *d; 364 365 for (d = auich_devices; d->name != NULL; d++) { 366 if (PCI_VENDOR(pa->pa_id) == d->vendor 367 && PCI_PRODUCT(pa->pa_id) == d->product) 368 return (d); 369 } 370 371 return (NULL); 372 } 373 374 int 375 auich_match(struct device *parent, struct cfdata *match, void *aux) 376 { 377 struct pci_attach_args *pa = aux; 378 379 if (auich_lookup(pa) != NULL) 380 return (1); 381 382 return (0); 383 } 384 385 void 386 auich_attach(struct device *parent, struct device *self, void *aux) 387 { 388 struct auich_softc *sc = (struct auich_softc *)self; 389 struct pci_attach_args *pa = aux; 390 pci_intr_handle_t ih; 391 bus_size_t mix_size, aud_size; 392 pcireg_t csr; 393 const char *intrstr; 394 const struct auich_devtype *d; 395 396 aprint_naive(": Audio controller\n"); 397 398 d = auich_lookup(pa); 399 if (d == NULL) 400 panic("auich_attach: impossible"); 401 402 #ifdef DIAGNOSTIC 403 sc->sc_pc = pa->pa_pc; 404 sc->sc_pt = pa->pa_tag; 405 #endif 406 407 aprint_normal(": %s\n", d->name); 408 409 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 410 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 411 aprint_error("%s: can't map codec i/o space\n", 412 sc->sc_dev.dv_xname); 413 return; 414 } 415 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 416 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 417 aprint_error("%s: can't map device i/o space\n", 418 sc->sc_dev.dv_xname); 419 return; 420 } 421 sc->dmat = pa->pa_dmat; 422 423 /* enable bus mastering */ 424 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 425 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 426 csr | PCI_COMMAND_MASTER_ENABLE); 427 428 /* Map and establish the interrupt. */ 429 if (pci_intr_map(pa, &ih)) { 430 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 431 return; 432 } 433 intrstr = pci_intr_string(pa->pa_pc, ih); 434 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 435 auich_intr, sc); 436 if (sc->sc_ih == NULL) { 437 aprint_error("%s: can't establish interrupt", 438 sc->sc_dev.dv_xname); 439 if (intrstr != NULL) 440 aprint_normal(" at %s", intrstr); 441 aprint_normal("\n"); 442 return; 443 } 444 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 445 446 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 447 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 448 "0x%02x", PCI_REVISION(pa->pa_class)); 449 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 450 451 /* SiS 7012 needs special handling */ 452 if (d->vendor == PCI_VENDOR_SIS 453 && d->product == PCI_PRODUCT_SIS_7012_AC) { 454 sc->sc_sts_reg = ICH_PICB; 455 sc->sc_sample_size = 1; 456 } else { 457 sc->sc_sts_reg = ICH_STS; 458 sc->sc_sample_size = 2; 459 } 460 461 /* Workaround for a 440MX B-stepping erratum */ 462 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 463 if (d->vendor == PCI_VENDOR_INTEL 464 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 465 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 466 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 467 } 468 469 /* Set up DMA lists. */ 470 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 471 auich_alloc_cdata(sc); 472 473 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 474 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 475 476 sc->host_if.arg = sc; 477 sc->host_if.attach = auich_attach_codec; 478 sc->host_if.read = auich_read_codec; 479 sc->host_if.write = auich_write_codec; 480 sc->host_if.reset = auich_reset_codec; 481 482 if (ac97_attach(&sc->host_if) != 0) 483 return; 484 485 /* Watch for power change */ 486 sc->sc_suspend = PWR_RESUME; 487 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 488 489 config_interrupts(self, auich_finish_attach); 490 } 491 492 void 493 auich_finish_attach(struct device *self) 494 { 495 struct auich_softc *sc = (void *)self; 496 497 if (!IS_FIXED_RATE(sc->codec_if)) 498 auich_calibrate(sc); 499 500 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 501 } 502 503 #define ICH_CODECIO_INTERVAL 10 504 int 505 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 506 { 507 struct auich_softc *sc = v; 508 int i; 509 uint32_t status; 510 511 /* wait for an access semaphore */ 512 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 513 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 514 DELAY(ICH_CODECIO_INTERVAL)); 515 516 if (i > 0) { 517 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 518 DPRINTF(ICH_DEBUG_CODECIO, 519 ("auich_read_codec(%x, %x)\n", reg, *val)); 520 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 521 if (status & ICH_RCS) { 522 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 523 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 524 *val = 0xffff; 525 } 526 return 0; 527 } else { 528 DPRINTF(ICH_DEBUG_CODECIO, 529 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 530 return -1; 531 } 532 } 533 534 int 535 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 536 { 537 struct auich_softc *sc = v; 538 int i; 539 540 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 541 /* wait for an access semaphore */ 542 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 543 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 544 DELAY(ICH_CODECIO_INTERVAL)); 545 546 if (i > 0) { 547 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 548 return 0; 549 } else { 550 DPRINTF(ICH_DEBUG_CODECIO, 551 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 552 return -1; 553 } 554 } 555 556 int 557 auich_attach_codec(void *v, struct ac97_codec_if *cif) 558 { 559 struct auich_softc *sc = v; 560 561 sc->codec_if = cif; 562 return 0; 563 } 564 565 void 566 auich_reset_codec(void *v) 567 { 568 struct auich_softc *sc = v; 569 int i; 570 uint32_t control, status; 571 572 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 573 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 574 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 575 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 576 577 for (i = 500000; i >= 0; i--) { 578 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 579 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 580 break; 581 DELAY(1); 582 } 583 if (i <= 0) { 584 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 585 /* XXX: should not attach the audio device */ 586 } else { 587 if (status & ICH_SCR) 588 printf("%s: The 2nd codec is ready.\n", 589 sc->sc_dev.dv_xname); 590 if (status & ICH_S2CR) 591 printf("%s: The 3rd codec is ready.\n", 592 sc->sc_dev.dv_xname); 593 } 594 } 595 596 int 597 auich_open(void *v, int flags) 598 { 599 return 0; 600 } 601 602 void 603 auich_close(void *v) 604 { 605 struct auich_softc *sc = v; 606 607 auich_halt_output(sc); 608 auich_halt_input(sc); 609 610 sc->sc_pintr = NULL; 611 sc->sc_rintr = NULL; 612 } 613 614 int 615 auich_query_encoding(void *v, struct audio_encoding *aep) 616 { 617 618 switch (aep->index) { 619 case 0: 620 strcpy(aep->name, AudioEulinear); 621 aep->encoding = AUDIO_ENCODING_ULINEAR; 622 aep->precision = 8; 623 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 624 return (0); 625 case 1: 626 strcpy(aep->name, AudioEmulaw); 627 aep->encoding = AUDIO_ENCODING_ULAW; 628 aep->precision = 8; 629 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 630 return (0); 631 case 2: 632 strcpy(aep->name, AudioEalaw); 633 aep->encoding = AUDIO_ENCODING_ALAW; 634 aep->precision = 8; 635 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 636 return (0); 637 case 3: 638 strcpy(aep->name, AudioEslinear); 639 aep->encoding = AUDIO_ENCODING_SLINEAR; 640 aep->precision = 8; 641 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 642 return (0); 643 case 4: 644 strcpy(aep->name, AudioEslinear_le); 645 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 646 aep->precision = 16; 647 aep->flags = 0; 648 return (0); 649 case 5: 650 strcpy(aep->name, AudioEulinear_le); 651 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 652 aep->precision = 16; 653 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 654 return (0); 655 case 6: 656 strcpy(aep->name, AudioEslinear_be); 657 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 658 aep->precision = 16; 659 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 660 return (0); 661 case 7: 662 strcpy(aep->name, AudioEulinear_be); 663 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 664 aep->precision = 16; 665 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 666 return (0); 667 default: 668 return (EINVAL); 669 } 670 } 671 672 int 673 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 674 { 675 int ret; 676 u_long ratetmp; 677 678 ratetmp = srate; 679 if (mode == AUMODE_RECORD) 680 return sc->codec_if->vtbl->set_rate(sc->codec_if, 681 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 682 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 683 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 684 if (ret) 685 return ret; 686 ratetmp = srate; 687 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 688 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 689 if (ret) 690 return ret; 691 ratetmp = srate; 692 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 693 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 694 return ret; 695 } 696 697 int 698 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 699 struct audio_params *rec) 700 { 701 struct auich_softc *sc = v; 702 struct audio_params *p; 703 int mode; 704 u_int32_t control; 705 706 for (mode = AUMODE_RECORD; mode != -1; 707 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 708 if ((setmode & mode) == 0) 709 continue; 710 711 p = mode == AUMODE_PLAY ? play : rec; 712 if (p == NULL) 713 continue; 714 715 if ((p->sample_rate != 8000) && 716 (p->sample_rate != 11025) && 717 (p->sample_rate != 12000) && 718 (p->sample_rate != 16000) && 719 (p->sample_rate != 22050) && 720 (p->sample_rate != 24000) && 721 (p->sample_rate != 32000) && 722 (p->sample_rate != 44100) && 723 (p->sample_rate != 48000)) 724 return (EINVAL); 725 726 p->factor = 1; 727 if (p->precision == 8) 728 p->factor *= 2; 729 730 p->sw_code = NULL; 731 /* setup hardware formats */ 732 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 733 p->hw_precision = 16; 734 735 if (mode == AUMODE_RECORD) { 736 if (p->channels < 1 || p->channels > 2) 737 return EINVAL; 738 } else { 739 switch (p->channels) { 740 case 1: 741 break; 742 case 2: 743 break; 744 case 4: 745 if (!SUPPORTS_4CH(sc->codec_if)) 746 return EINVAL; 747 break; 748 case 6: 749 if (!SUPPORTS_6CH(sc->codec_if)) 750 return EINVAL; 751 break; 752 default: 753 return EINVAL; 754 } 755 } 756 /* If monaural is requested, aurateconv expands a monaural 757 * stream to stereo. */ 758 if (p->channels == 1) 759 p->hw_channels = 2; 760 761 switch (p->encoding) { 762 case AUDIO_ENCODING_SLINEAR_BE: 763 if (p->precision == 16) { 764 p->sw_code = swap_bytes; 765 } else { 766 if (mode == AUMODE_PLAY) 767 p->sw_code = linear8_to_linear16_le; 768 else 769 p->sw_code = linear16_to_linear8_le; 770 } 771 break; 772 773 case AUDIO_ENCODING_SLINEAR_LE: 774 if (p->precision != 16) { 775 if (mode == AUMODE_PLAY) 776 p->sw_code = linear8_to_linear16_le; 777 else 778 p->sw_code = linear16_to_linear8_le; 779 } 780 break; 781 782 case AUDIO_ENCODING_ULINEAR_BE: 783 if (p->precision == 16) { 784 if (mode == AUMODE_PLAY) 785 p->sw_code = 786 swap_bytes_change_sign16_le; 787 else 788 p->sw_code = 789 change_sign16_swap_bytes_le; 790 } else { 791 if (mode == AUMODE_PLAY) 792 p->sw_code = 793 ulinear8_to_slinear16_le; 794 else 795 p->sw_code = 796 slinear16_to_ulinear8_le; 797 } 798 break; 799 800 case AUDIO_ENCODING_ULINEAR_LE: 801 if (p->precision == 16) { 802 p->sw_code = change_sign16_le; 803 } else { 804 if (mode == AUMODE_PLAY) 805 p->sw_code = 806 ulinear8_to_slinear16_le; 807 else 808 p->sw_code = 809 slinear16_to_ulinear8_le; 810 } 811 break; 812 813 case AUDIO_ENCODING_ULAW: 814 if (mode == AUMODE_PLAY) { 815 p->sw_code = mulaw_to_slinear16_le; 816 } else { 817 p->sw_code = slinear16_to_mulaw_le; 818 } 819 break; 820 821 case AUDIO_ENCODING_ALAW: 822 if (mode == AUMODE_PLAY) { 823 p->sw_code = alaw_to_slinear16_le; 824 } else { 825 p->sw_code = slinear16_to_alaw_le; 826 } 827 break; 828 829 default: 830 return (EINVAL); 831 } 832 833 if (IS_FIXED_RATE(sc->codec_if)) { 834 p->hw_sample_rate = AC97_SINGLE_RATE; 835 /* If hw_sample_rate is changed, aurateconv works. */ 836 } else { 837 if (auich_set_rate(sc, mode, p->sample_rate)) 838 return EINVAL; 839 } 840 if (mode == AUMODE_PLAY) { 841 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 842 control &= ~ICH_PCM246_MASK; 843 if (p->channels == 4) { 844 control |= ICH_PCM4; 845 } else if (p->channels == 6) { 846 control |= ICH_PCM6; 847 } 848 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 849 } 850 } 851 852 return (0); 853 } 854 855 int 856 auich_round_blocksize(void *v, int blk) 857 { 858 859 return (blk & ~0x3f); /* keep good alignment */ 860 } 861 862 int 863 auich_halt_output(void *v) 864 { 865 struct auich_softc *sc = v; 866 867 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 868 869 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 870 871 return (0); 872 } 873 874 int 875 auich_halt_input(void *v) 876 { 877 struct auich_softc *sc = v; 878 879 DPRINTF(ICH_DEBUG_DMA, 880 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 881 882 /* XXX halt both unless known otherwise */ 883 884 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 885 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 886 887 return (0); 888 } 889 890 int 891 auich_getdev(void *v, struct audio_device *adp) 892 { 893 struct auich_softc *sc = v; 894 895 *adp = sc->sc_audev; 896 return (0); 897 } 898 899 int 900 auich_set_port(void *v, mixer_ctrl_t *cp) 901 { 902 struct auich_softc *sc = v; 903 904 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 905 } 906 907 int 908 auich_get_port(void *v, mixer_ctrl_t *cp) 909 { 910 struct auich_softc *sc = v; 911 912 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 913 } 914 915 int 916 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 917 { 918 struct auich_softc *sc = v; 919 920 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 921 } 922 923 void * 924 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 925 int flags) 926 { 927 struct auich_softc *sc = v; 928 struct auich_dma *p; 929 int error; 930 931 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 932 return (NULL); 933 934 p = malloc(sizeof(*p), pool, flags|M_ZERO); 935 if (p == NULL) 936 return (NULL); 937 938 error = auich_allocmem(sc, size, 0, p); 939 if (error) { 940 free(p, pool); 941 return (NULL); 942 } 943 944 p->next = sc->sc_dmas; 945 sc->sc_dmas = p; 946 947 return (KERNADDR(p)); 948 } 949 950 void 951 auich_freem(void *v, void *ptr, struct malloc_type *pool) 952 { 953 struct auich_softc *sc = v; 954 struct auich_dma *p, **pp; 955 956 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 957 if (KERNADDR(p) == ptr) { 958 auich_freemem(sc, p); 959 *pp = p->next; 960 free(p, pool); 961 return; 962 } 963 } 964 } 965 966 size_t 967 auich_round_buffersize(void *v, int direction, size_t size) 968 { 969 970 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 971 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 972 973 return size; 974 } 975 976 paddr_t 977 auich_mappage(void *v, void *mem, off_t off, int prot) 978 { 979 struct auich_softc *sc = v; 980 struct auich_dma *p; 981 982 if (off < 0) 983 return (-1); 984 985 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 986 ; 987 if (!p) 988 return (-1); 989 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 990 off, prot, BUS_DMA_WAITOK)); 991 } 992 993 int 994 auich_get_props(void *v) 995 { 996 struct auich_softc *sc = v; 997 int props; 998 999 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1000 /* 1001 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1002 * rate because of aurateconv. Applications can't know what rate the 1003 * device can process in the case of mmap(). 1004 */ 1005 if (!IS_FIXED_RATE(sc->codec_if)) 1006 props |= AUDIO_PROP_MMAP; 1007 return props; 1008 } 1009 1010 int 1011 auich_intr(void *v) 1012 { 1013 struct auich_softc *sc = v; 1014 int ret = 0, sts, gsts, i, qptr; 1015 1016 #ifdef DIAGNOSTIC 1017 int csts; 1018 #endif 1019 1020 #ifdef DIAGNOSTIC 1021 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1022 if (csts & PCI_STATUS_MASTER_ABORT) { 1023 printf("auich_intr: PCI master abort\n"); 1024 } 1025 #endif 1026 1027 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 1028 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 1029 1030 if (gsts & ICH_POINT) { 1031 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 1032 DPRINTF(ICH_DEBUG_DMA, 1033 ("auich_intr: osts=0x%x\n", sts)); 1034 1035 if (sts & ICH_FIFOE) { 1036 printf("%s: fifo underrun # %u\n", 1037 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1038 } 1039 1040 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1041 if (sts & (ICH_LVBCI | ICH_CELV)) { 1042 struct auich_dmalist *q; 1043 1044 qptr = sc->ptr_pcmo; 1045 1046 while (qptr != i) { 1047 q = &sc->dmalist_pcmo[qptr]; 1048 1049 q->base = sc->pcmo_p; 1050 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1051 DPRINTF(ICH_DEBUG_DMA, 1052 ("auich_intr: %p, %p = %x @ 0x%x\n", 1053 &sc->dmalist_pcmo[i], q, 1054 sc->pcmo_blksize / 2, sc->pcmo_p)); 1055 1056 sc->pcmo_p += sc->pcmo_blksize; 1057 if (sc->pcmo_p >= sc->pcmo_end) 1058 sc->pcmo_p = sc->pcmo_start; 1059 1060 if (++qptr == ICH_DMALIST_MAX) 1061 qptr = 0; 1062 } 1063 1064 sc->ptr_pcmo = qptr; 1065 bus_space_write_1(sc->iot, sc->aud_ioh, 1066 ICH_PCMO + ICH_LVI, 1067 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1068 } 1069 1070 if (sts & ICH_BCIS && sc->sc_pintr) 1071 sc->sc_pintr(sc->sc_parg); 1072 1073 /* int ack */ 1074 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1075 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1076 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1077 ret++; 1078 } 1079 1080 if (gsts & ICH_PIINT) { 1081 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1082 DPRINTF(ICH_DEBUG_DMA, 1083 ("auich_intr: ists=0x%x\n", sts)); 1084 1085 if (sts & ICH_FIFOE) { 1086 printf("%s: fifo overrun # %u\n", 1087 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1088 } 1089 1090 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1091 if (sts & (ICH_LVBCI | ICH_CELV)) { 1092 struct auich_dmalist *q; 1093 1094 qptr = sc->ptr_pcmi; 1095 1096 while (qptr != i) { 1097 q = &sc->dmalist_pcmi[qptr]; 1098 1099 q->base = sc->pcmi_p; 1100 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1101 DPRINTF(ICH_DEBUG_DMA, 1102 ("auich_intr: %p, %p = %x @ 0x%x\n", 1103 &sc->dmalist_pcmi[i], q, 1104 sc->pcmi_blksize / 2, sc->pcmi_p)); 1105 1106 sc->pcmi_p += sc->pcmi_blksize; 1107 if (sc->pcmi_p >= sc->pcmi_end) 1108 sc->pcmi_p = sc->pcmi_start; 1109 1110 if (++qptr == ICH_DMALIST_MAX) 1111 qptr = 0; 1112 } 1113 1114 sc->ptr_pcmi = qptr; 1115 bus_space_write_1(sc->iot, sc->aud_ioh, 1116 ICH_PCMI + ICH_LVI, 1117 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1118 } 1119 1120 if (sts & ICH_BCIS && sc->sc_rintr) 1121 sc->sc_rintr(sc->sc_rarg); 1122 1123 /* int ack */ 1124 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1125 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1126 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1127 ret++; 1128 } 1129 1130 if (gsts & ICH_MIINT) { 1131 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1132 DPRINTF(ICH_DEBUG_DMA, 1133 ("auich_intr: ists=0x%x\n", sts)); 1134 if (sts & ICH_FIFOE) 1135 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1136 1137 /* TODO mic input DMA */ 1138 1139 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1140 } 1141 1142 return ret; 1143 } 1144 1145 int 1146 auich_trigger_output(void *v, void *start, void *end, int blksize, 1147 void (*intr)(void *), void *arg, struct audio_params *param) 1148 { 1149 struct auich_softc *sc = v; 1150 struct auich_dmalist *q; 1151 struct auich_dma *p; 1152 size_t size; 1153 #ifdef DIAGNOSTIC 1154 int csts; 1155 #endif 1156 1157 DPRINTF(ICH_DEBUG_DMA, 1158 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1159 start, end, blksize, intr, arg, param)); 1160 1161 sc->sc_pintr = intr; 1162 sc->sc_parg = arg; 1163 #ifdef DIAGNOSTIC 1164 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1165 if (csts & PCI_STATUS_MASTER_ABORT) { 1166 printf("auich_trigger_output: PCI master abort\n"); 1167 } 1168 #endif 1169 1170 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1171 ; 1172 if (!p) { 1173 printf("auich_trigger_output: bad addr %p\n", start); 1174 return (EINVAL); 1175 } 1176 1177 size = (size_t)((caddr_t)end - (caddr_t)start); 1178 1179 /* 1180 * The logic behind this is: 1181 * setup one buffer to play, then LVI dump out the rest 1182 * to the scatter-gather chain. 1183 */ 1184 sc->pcmo_start = DMAADDR(p); 1185 sc->pcmo_p = sc->pcmo_start + blksize; 1186 sc->pcmo_end = sc->pcmo_start + size; 1187 sc->pcmo_blksize = blksize; 1188 1189 sc->ptr_pcmo = 0; 1190 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1191 q->base = sc->pcmo_start; 1192 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1193 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1194 sc->ptr_pcmo = 0; 1195 1196 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1197 sc->sc_cddma + ICH_PCMO_OFF(0)); 1198 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1199 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1200 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1201 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1202 1203 return (0); 1204 } 1205 1206 int 1207 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1208 void *v; 1209 void *start, *end; 1210 int blksize; 1211 void (*intr)(void *); 1212 void *arg; 1213 struct audio_params *param; 1214 { 1215 struct auich_softc *sc = v; 1216 struct auich_dmalist *q; 1217 struct auich_dma *p; 1218 size_t size; 1219 #ifdef DIAGNOSTIC 1220 int csts; 1221 #endif 1222 1223 DPRINTF(ICH_DEBUG_DMA, 1224 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1225 start, end, blksize, intr, arg, param)); 1226 1227 sc->sc_rintr = intr; 1228 sc->sc_rarg = arg; 1229 1230 #ifdef DIAGNOSTIC 1231 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1232 if (csts & PCI_STATUS_MASTER_ABORT) { 1233 printf("auich_trigger_input: PCI master abort\n"); 1234 } 1235 #endif 1236 1237 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1238 ; 1239 if (!p) { 1240 printf("auich_trigger_input: bad addr %p\n", start); 1241 return (EINVAL); 1242 } 1243 1244 size = (size_t)((caddr_t)end - (caddr_t)start); 1245 1246 /* 1247 * The logic behind this is: 1248 * setup one buffer to play, then LVI dump out the rest 1249 * to the scatter-gather chain. 1250 */ 1251 sc->pcmi_start = DMAADDR(p); 1252 sc->pcmi_p = sc->pcmi_start + blksize; 1253 sc->pcmi_end = sc->pcmi_start + size; 1254 sc->pcmi_blksize = blksize; 1255 1256 sc->ptr_pcmi = 0; 1257 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1258 q->base = sc->pcmi_start; 1259 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1260 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1261 sc->ptr_pcmi = 0; 1262 1263 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1264 sc->sc_cddma + ICH_PCMI_OFF(0)); 1265 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1266 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1267 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1268 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1269 1270 return (0); 1271 } 1272 1273 int 1274 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1275 struct auich_dma *p) 1276 { 1277 int error; 1278 1279 p->size = size; 1280 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1281 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1282 &p->nsegs, BUS_DMA_NOWAIT); 1283 if (error) 1284 return (error); 1285 1286 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1287 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1288 if (error) 1289 goto free; 1290 1291 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1292 0, BUS_DMA_NOWAIT, &p->map); 1293 if (error) 1294 goto unmap; 1295 1296 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1297 BUS_DMA_NOWAIT); 1298 if (error) 1299 goto destroy; 1300 return (0); 1301 1302 destroy: 1303 bus_dmamap_destroy(sc->dmat, p->map); 1304 unmap: 1305 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1306 free: 1307 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1308 return (error); 1309 } 1310 1311 int 1312 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1313 { 1314 1315 bus_dmamap_unload(sc->dmat, p->map); 1316 bus_dmamap_destroy(sc->dmat, p->map); 1317 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1318 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1319 return (0); 1320 } 1321 1322 int 1323 auich_alloc_cdata(struct auich_softc *sc) 1324 { 1325 bus_dma_segment_t seg; 1326 int error, rseg; 1327 1328 /* 1329 * Allocate the control data structure, and create and load the 1330 * DMA map for it. 1331 */ 1332 if ((error = bus_dmamem_alloc(sc->dmat, 1333 sizeof(struct auich_cdata), 1334 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1335 printf("%s: unable to allocate control data, error = %d\n", 1336 sc->sc_dev.dv_xname, error); 1337 goto fail_0; 1338 } 1339 1340 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1341 sizeof(struct auich_cdata), 1342 (caddr_t *) &sc->sc_cdata, 1343 sc->sc_dmamap_flags)) != 0) { 1344 printf("%s: unable to map control data, error = %d\n", 1345 sc->sc_dev.dv_xname, error); 1346 goto fail_1; 1347 } 1348 1349 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1350 sizeof(struct auich_cdata), 0, 0, 1351 &sc->sc_cddmamap)) != 0) { 1352 printf("%s: unable to create control data DMA map, " 1353 "error = %d\n", sc->sc_dev.dv_xname, error); 1354 goto fail_2; 1355 } 1356 1357 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1358 sc->sc_cdata, sizeof(struct auich_cdata), 1359 NULL, 0)) != 0) { 1360 printf("%s: unable tp load control data DMA map, " 1361 "error = %d\n", sc->sc_dev.dv_xname, error); 1362 goto fail_3; 1363 } 1364 1365 return (0); 1366 1367 fail_3: 1368 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1369 fail_2: 1370 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1371 sizeof(struct auich_cdata)); 1372 fail_1: 1373 bus_dmamem_free(sc->dmat, &seg, rseg); 1374 fail_0: 1375 return (error); 1376 } 1377 1378 void 1379 auich_powerhook(int why, void *addr) 1380 { 1381 struct auich_softc *sc = (struct auich_softc *)addr; 1382 1383 switch (why) { 1384 case PWR_SUSPEND: 1385 case PWR_STANDBY: 1386 /* Power down */ 1387 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1388 sc->sc_suspend = why; 1389 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1390 break; 1391 1392 case PWR_RESUME: 1393 /* Wake up */ 1394 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1395 if (sc->sc_suspend == PWR_RESUME) { 1396 printf("%s: resume without suspend.\n", 1397 sc->sc_dev.dv_xname); 1398 sc->sc_suspend = why; 1399 return; 1400 } 1401 sc->sc_suspend = why; 1402 auich_reset_codec(sc); 1403 DELAY(1000); 1404 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1405 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1406 break; 1407 1408 case PWR_SOFTSUSPEND: 1409 case PWR_SOFTSTANDBY: 1410 case PWR_SOFTRESUME: 1411 break; 1412 } 1413 } 1414 1415 1416 /* -------------------------------------------------------------------- */ 1417 /* Calibrate card (some boards are overclocked and need scaling) */ 1418 1419 void 1420 auich_calibrate(struct auich_softc *sc) 1421 { 1422 struct timeval t1, t2; 1423 u_int8_t ociv, nciv = 0; 1424 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1425 void *temp_buffer; 1426 struct auich_dma *p; 1427 1428 /* 1429 * Grab audio from input for fixed interval and compare how 1430 * much we actually get with what we expect. Interval needs 1431 * to be sufficiently short that no interrupts are 1432 * generated. 1433 */ 1434 1435 /* Setup a buffer */ 1436 bytes = 16000; 1437 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1438 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1439 ; 1440 if (p == NULL) { 1441 printf("auich_calibrate: bad address %p\n", temp_buffer); 1442 return; 1443 } 1444 sc->dmalist_pcmi[0].base = DMAADDR(p); 1445 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size); 1446 1447 /* 1448 * our data format is stereo, 16 bit so each sample is 4 bytes. 1449 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1450 * we're going to start recording with interrupts disabled and measure 1451 * the time taken for one block to complete. we know the block size, 1452 * we know the time in microseconds, we calculate the sample rate: 1453 * 1454 * actual_rate [bps] = bytes / (time [s] * 4) 1455 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1456 * actual_rate [Hz] = (bytes * 250000) / time [us] 1457 */ 1458 1459 /* prepare */ 1460 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1461 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1462 sc->sc_cddma + ICH_PCMI_OFF(0)); 1463 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1464 (0 - 1) & ICH_LVI_MASK); 1465 1466 /* start */ 1467 microtime(&t1); 1468 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1469 1470 /* wait */ 1471 do { 1472 microtime(&t2); 1473 if (t2.tv_sec - t1.tv_sec > 1) 1474 break; 1475 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1476 ICH_PCMI + ICH_CIV); 1477 } while (nciv == ociv); 1478 1479 /* stop */ 1480 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1481 1482 /* reset */ 1483 DELAY(100); 1484 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1485 1486 /* turn time delta into us */ 1487 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1488 1489 auich_freem(sc, temp_buffer, M_DEVBUF); 1490 1491 if (nciv == ociv) { 1492 printf("%s: ac97 link rate calibration timed out after %d us\n", 1493 sc->sc_dev.dv_xname, wait_us); 1494 return; 1495 } 1496 1497 actual_48k_rate = (bytes * 250000U) / wait_us; 1498 1499 if (actual_48k_rate <= 48500) 1500 ac97rate = 48000; 1501 else 1502 ac97rate = actual_48k_rate; 1503 1504 printf("%s: measured ac97 link rate at %d Hz", 1505 sc->sc_dev.dv_xname, actual_48k_rate); 1506 if (ac97rate != actual_48k_rate) 1507 printf(", will use %d Hz", ac97rate); 1508 printf("\n"); 1509 1510 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1511 } 1512
Indexes created Wed Oct 22 13:09:56 GMT 2025