auich.c revision 1.54
1 /* $NetBSD: auich.c,v 1.54 2003/11/06 07:13:33 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.54 2003/11/06 07:13:33 mycroft Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 131 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 132 133 #include <dev/pci/pcidevs.h> 134 #include <dev/pci/pcivar.h> 135 #include <dev/pci/auichreg.h> 136 137 #include <sys/audioio.h> 138 #include <dev/audio_if.h> 139 #include <dev/mulaw.h> 140 #include <dev/auconv.h> 141 142 #include <machine/bus.h> 143 144 #include <dev/ic/ac97reg.h> 145 #include <dev/ic/ac97var.h> 146 147 struct auich_dma { 148 bus_dmamap_t map; 149 caddr_t addr; 150 bus_dma_segment_t segs[1]; 151 int nsegs; 152 size_t size; 153 struct auich_dma *next; 154 }; 155 156 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 157 #define KERNADDR(p) ((void *)((p)->addr)) 158 159 struct auich_cdata { 160 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 161 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 163 }; 164 165 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 166 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 167 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 168 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 169 170 struct auich_softc { 171 struct device sc_dev; 172 void *sc_ih; 173 174 audio_device_t sc_audev; 175 176 bus_space_tag_t iot; 177 bus_space_handle_t mix_ioh; 178 bus_space_handle_t aud_ioh; 179 bus_dma_tag_t dmat; 180 181 struct ac97_codec_if *codec_if; 182 struct ac97_host_if host_if; 183 184 /* DMA scatter-gather lists. */ 185 bus_dmamap_t sc_cddmamap; 186 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 187 188 struct auich_cdata *sc_cdata; 189 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 190 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 191 #define dmalist_mici sc_cdata->ic_dmalist_mici 192 193 int ptr_pcmo, 194 ptr_pcmi, 195 ptr_mici; 196 197 /* i/o buffer pointers */ 198 u_int32_t pcmo_start, pcmo_p, pcmo_end; 199 int pcmo_blksize, pcmo_fifoe; 200 201 u_int32_t pcmi_start, pcmi_p, pcmi_end; 202 int pcmi_blksize, pcmi_fifoe; 203 204 u_int32_t mici_start, mici_p, mici_end; 205 int mici_blksize, mici_fifoe; 206 207 struct auich_dma *sc_dmas; 208 209 #ifdef DIAGNOSTIC 210 pci_chipset_tag_t sc_pc; 211 pcitag_t sc_pt; 212 #endif 213 /* SiS 7012 hack */ 214 int sc_sample_size; 215 int sc_sts_reg; 216 /* 440MX workaround */ 217 int sc_dmamap_flags; 218 219 void (*sc_pintr)(void *); 220 void *sc_parg; 221 222 void (*sc_rintr)(void *); 223 void *sc_rarg; 224 225 /* Power Management */ 226 void *sc_powerhook; 227 int sc_suspend; 228 u_int16_t ext_status; 229 }; 230 231 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 232 & AC97_EXT_AUDIO_VRA) 233 #define SUPPORTS_4CH(codec) ((codec)->vtbl->get_extcaps(codec) \ 234 & AC97_EXT_AUDIO_SDAC) 235 #define AC97_6CH_DACS (AC97_EXT_AUDIO_SDAC | AC97_EXT_AUDIO_CDAC \ 236 | AC97_EXT_AUDIO_LDAC) 237 #define SUPPORTS_6CH(codec) (((codec)->vtbl->get_extcaps(codec) \ 238 & AC97_6CH_DACS) == AC97_6CH_DACS) 239 240 /* Debug */ 241 #ifdef AUDIO_DEBUG 242 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 243 int auich_debug = 0xfffe; 244 #define ICH_DEBUG_CODECIO 0x0001 245 #define ICH_DEBUG_DMA 0x0002 246 #define ICH_DEBUG_PARAM 0x0004 247 #else 248 #define DPRINTF(x,y) /* nothing */ 249 #endif 250 251 int auich_match(struct device *, struct cfdata *, void *); 252 void auich_attach(struct device *, struct device *, void *); 253 int auich_intr(void *); 254 255 CFATTACH_DECL(auich, sizeof(struct auich_softc), 256 auich_match, auich_attach, NULL, NULL); 257 258 int auich_open(void *, int); 259 void auich_close(void *); 260 int auich_query_encoding(void *, struct audio_encoding *); 261 int auich_set_params(void *, int, int, struct audio_params *, 262 struct audio_params *); 263 int auich_round_blocksize(void *, int); 264 int auich_halt_output(void *); 265 int auich_halt_input(void *); 266 int auich_getdev(void *, struct audio_device *); 267 int auich_set_port(void *, mixer_ctrl_t *); 268 int auich_get_port(void *, mixer_ctrl_t *); 269 int auich_query_devinfo(void *, mixer_devinfo_t *); 270 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 271 void auich_freem(void *, void *, struct malloc_type *); 272 size_t auich_round_buffersize(void *, int, size_t); 273 paddr_t auich_mappage(void *, void *, off_t, int); 274 int auich_get_props(void *); 275 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 276 void *, struct audio_params *); 277 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 278 void *, struct audio_params *); 279 280 int auich_alloc_cdata(struct auich_softc *); 281 282 int auich_allocmem(struct auich_softc *, size_t, size_t, 283 struct auich_dma *); 284 int auich_freemem(struct auich_softc *, struct auich_dma *); 285 286 void auich_powerhook(int, void *); 287 int auich_set_rate(struct auich_softc *, int, u_long); 288 void auich_finish_attach(struct device *); 289 void auich_calibrate(struct auich_softc *); 290 291 292 struct audio_hw_if auich_hw_if = { 293 auich_open, 294 auich_close, 295 NULL, /* drain */ 296 auich_query_encoding, 297 auich_set_params, 298 auich_round_blocksize, 299 NULL, /* commit_setting */ 300 NULL, /* init_output */ 301 NULL, /* init_input */ 302 NULL, /* start_output */ 303 NULL, /* start_input */ 304 auich_halt_output, 305 auich_halt_input, 306 NULL, /* speaker_ctl */ 307 auich_getdev, 308 NULL, /* getfd */ 309 auich_set_port, 310 auich_get_port, 311 auich_query_devinfo, 312 auich_allocm, 313 auich_freem, 314 auich_round_buffersize, 315 auich_mappage, 316 auich_get_props, 317 auich_trigger_output, 318 auich_trigger_input, 319 NULL, /* dev_ioctl */ 320 }; 321 322 int auich_attach_codec(void *, struct ac97_codec_if *); 323 int auich_read_codec(void *, u_int8_t, u_int16_t *); 324 int auich_write_codec(void *, u_int8_t, u_int16_t); 325 void auich_reset_codec(void *); 326 327 static const struct auich_devtype { 328 int vendor; 329 int product; 330 const char *name; 331 const char *shortname; /* must be less than 11 characters */ 332 } auich_devices[] = { 333 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 334 "i82801AA (ICH) AC-97 Audio", "ICH" }, 335 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 336 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 337 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 338 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 339 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 340 "i82440MX AC-97 Audio", "440MX" }, 341 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 342 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 343 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 344 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 345 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 346 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 347 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 348 "SiS 7012 AC-97 Audio", "SiS7012" }, 349 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 350 "nForce MCP AC-97 Audio", "nForce" }, 351 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 352 "nForce2 MCP-T AC-97 Audio", "nForce2" }, 353 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 354 "nForce3 MCP-T AC-97 Audio", "nForce3" }, 355 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 356 "AMD768 AC-97 Audio", "AMD768" }, 357 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 358 "AMD8111 AC-97 Audio", "AMD8111" }, 359 { 0, 0, 360 NULL, NULL }, 361 }; 362 363 static const struct auich_devtype * 364 auich_lookup(struct pci_attach_args *pa) 365 { 366 const struct auich_devtype *d; 367 368 for (d = auich_devices; d->name != NULL; d++) { 369 if (PCI_VENDOR(pa->pa_id) == d->vendor 370 && PCI_PRODUCT(pa->pa_id) == d->product) 371 return (d); 372 } 373 374 return (NULL); 375 } 376 377 int 378 auich_match(struct device *parent, struct cfdata *match, void *aux) 379 { 380 struct pci_attach_args *pa = aux; 381 382 if (auich_lookup(pa) != NULL) 383 return (1); 384 385 return (0); 386 } 387 388 void 389 auich_attach(struct device *parent, struct device *self, void *aux) 390 { 391 struct auich_softc *sc = (struct auich_softc *)self; 392 struct pci_attach_args *pa = aux; 393 pci_intr_handle_t ih; 394 bus_size_t mix_size, aud_size; 395 pcireg_t v; 396 const char *intrstr; 397 const struct auich_devtype *d; 398 399 aprint_naive(": Audio controller\n"); 400 401 d = auich_lookup(pa); 402 if (d == NULL) 403 panic("auich_attach: impossible"); 404 405 #ifdef DIAGNOSTIC 406 sc->sc_pc = pa->pa_pc; 407 sc->sc_pt = pa->pa_tag; 408 #endif 409 410 aprint_normal(": %s\n", d->name); 411 412 /* 413 * For ICH4/ICH5, make sure the compatible BARs are writable. 414 * We can not access all registers of ICH4/ICH5 with NAMBAR 415 * and NABMBAR. But they are sufficient for the current driver. 416 */ 417 if ((d->vendor == PCI_VENDOR_INTEL 418 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) 419 || (d->vendor == PCI_VENDOR_INTEL 420 && d->product == PCI_PRODUCT_INTEL_82801EB_AC)) { 421 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 422 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, v | ICH_CFG_IOSE); 423 } 424 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 425 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 426 aprint_error("%s: can't map codec i/o space\n", 427 sc->sc_dev.dv_xname); 428 return; 429 } 430 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 431 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 432 aprint_error("%s: can't map device i/o space\n", 433 sc->sc_dev.dv_xname); 434 return; 435 } 436 sc->dmat = pa->pa_dmat; 437 438 /* enable bus mastering */ 439 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 440 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 441 v | PCI_COMMAND_MASTER_ENABLE); 442 443 /* Map and establish the interrupt. */ 444 if (pci_intr_map(pa, &ih)) { 445 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 446 return; 447 } 448 intrstr = pci_intr_string(pa->pa_pc, ih); 449 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 450 auich_intr, sc); 451 if (sc->sc_ih == NULL) { 452 aprint_error("%s: can't establish interrupt", 453 sc->sc_dev.dv_xname); 454 if (intrstr != NULL) 455 aprint_normal(" at %s", intrstr); 456 aprint_normal("\n"); 457 return; 458 } 459 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 460 461 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 462 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 463 "0x%02x", PCI_REVISION(pa->pa_class)); 464 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 465 466 /* SiS 7012 needs special handling */ 467 if (d->vendor == PCI_VENDOR_SIS 468 && d->product == PCI_PRODUCT_SIS_7012_AC) { 469 sc->sc_sts_reg = ICH_PICB; 470 sc->sc_sample_size = 1; 471 } else { 472 sc->sc_sts_reg = ICH_STS; 473 sc->sc_sample_size = 2; 474 } 475 476 /* Workaround for a 440MX B-stepping erratum */ 477 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 478 if (d->vendor == PCI_VENDOR_INTEL 479 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 480 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 481 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 482 } 483 484 /* Set up DMA lists. */ 485 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 486 auich_alloc_cdata(sc); 487 488 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 489 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 490 491 sc->host_if.arg = sc; 492 sc->host_if.attach = auich_attach_codec; 493 sc->host_if.read = auich_read_codec; 494 sc->host_if.write = auich_write_codec; 495 sc->host_if.reset = auich_reset_codec; 496 497 if (ac97_attach(&sc->host_if) != 0) 498 return; 499 500 /* Watch for power change */ 501 sc->sc_suspend = PWR_RESUME; 502 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 503 504 config_interrupts(self, auich_finish_attach); 505 } 506 507 void 508 auich_finish_attach(struct device *self) 509 { 510 struct auich_softc *sc = (void *)self; 511 512 if (!IS_FIXED_RATE(sc->codec_if)) 513 auich_calibrate(sc); 514 515 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 516 } 517 518 #define ICH_CODECIO_INTERVAL 10 519 int 520 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 521 { 522 struct auich_softc *sc = v; 523 int i; 524 uint32_t status; 525 526 /* wait for an access semaphore */ 527 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 528 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 529 DELAY(ICH_CODECIO_INTERVAL)); 530 531 if (i > 0) { 532 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 533 DPRINTF(ICH_DEBUG_CODECIO, 534 ("auich_read_codec(%x, %x)\n", reg, *val)); 535 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 536 if (status & ICH_RCS) { 537 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 538 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 539 *val = 0xffff; 540 } 541 return 0; 542 } else { 543 DPRINTF(ICH_DEBUG_CODECIO, 544 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 545 return -1; 546 } 547 } 548 549 int 550 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 551 { 552 struct auich_softc *sc = v; 553 int i; 554 555 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 556 /* wait for an access semaphore */ 557 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 558 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 559 DELAY(ICH_CODECIO_INTERVAL)); 560 561 if (i > 0) { 562 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 563 return 0; 564 } else { 565 DPRINTF(ICH_DEBUG_CODECIO, 566 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 567 return -1; 568 } 569 } 570 571 int 572 auich_attach_codec(void *v, struct ac97_codec_if *cif) 573 { 574 struct auich_softc *sc = v; 575 576 sc->codec_if = cif; 577 return 0; 578 } 579 580 void 581 auich_reset_codec(void *v) 582 { 583 struct auich_softc *sc = v; 584 int i; 585 uint32_t control, status; 586 587 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 588 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 589 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 590 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 591 592 for (i = 500000; i >= 0; i--) { 593 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 594 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 595 break; 596 DELAY(1); 597 } 598 if (i <= 0) { 599 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 600 /* XXX: should not attach the audio device */ 601 } else { 602 if (status & ICH_SCR) 603 printf("%s: The 2nd codec is ready.\n", 604 sc->sc_dev.dv_xname); 605 if (status & ICH_S2CR) 606 printf("%s: The 3rd codec is ready.\n", 607 sc->sc_dev.dv_xname); 608 } 609 } 610 611 int 612 auich_open(void *v, int flags) 613 { 614 return 0; 615 } 616 617 void 618 auich_close(void *v) 619 { 620 struct auich_softc *sc = v; 621 622 auich_halt_output(sc); 623 auich_halt_input(sc); 624 625 sc->sc_pintr = NULL; 626 sc->sc_rintr = NULL; 627 } 628 629 int 630 auich_query_encoding(void *v, struct audio_encoding *aep) 631 { 632 633 switch (aep->index) { 634 case 0: 635 strcpy(aep->name, AudioEulinear); 636 aep->encoding = AUDIO_ENCODING_ULINEAR; 637 aep->precision = 8; 638 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 639 return (0); 640 case 1: 641 strcpy(aep->name, AudioEmulaw); 642 aep->encoding = AUDIO_ENCODING_ULAW; 643 aep->precision = 8; 644 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 645 return (0); 646 case 2: 647 strcpy(aep->name, AudioEalaw); 648 aep->encoding = AUDIO_ENCODING_ALAW; 649 aep->precision = 8; 650 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 651 return (0); 652 case 3: 653 strcpy(aep->name, AudioEslinear); 654 aep->encoding = AUDIO_ENCODING_SLINEAR; 655 aep->precision = 8; 656 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 657 return (0); 658 case 4: 659 strcpy(aep->name, AudioEslinear_le); 660 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 661 aep->precision = 16; 662 aep->flags = 0; 663 return (0); 664 case 5: 665 strcpy(aep->name, AudioEulinear_le); 666 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 667 aep->precision = 16; 668 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 669 return (0); 670 case 6: 671 strcpy(aep->name, AudioEslinear_be); 672 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 673 aep->precision = 16; 674 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 675 return (0); 676 case 7: 677 strcpy(aep->name, AudioEulinear_be); 678 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 679 aep->precision = 16; 680 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 681 return (0); 682 default: 683 return (EINVAL); 684 } 685 } 686 687 int 688 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 689 { 690 int ret; 691 u_long ratetmp; 692 693 ratetmp = srate; 694 if (mode == AUMODE_RECORD) 695 return sc->codec_if->vtbl->set_rate(sc->codec_if, 696 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 697 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 698 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 699 if (ret) 700 return ret; 701 ratetmp = srate; 702 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 703 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 704 if (ret) 705 return ret; 706 ratetmp = srate; 707 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 708 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 709 return ret; 710 } 711 712 int 713 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 714 struct audio_params *rec) 715 { 716 struct auich_softc *sc = v; 717 struct audio_params *p; 718 int mode; 719 u_int32_t control; 720 721 for (mode = AUMODE_RECORD; mode != -1; 722 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 723 if ((setmode & mode) == 0) 724 continue; 725 726 p = mode == AUMODE_PLAY ? play : rec; 727 if (p == NULL) 728 continue; 729 730 if ((p->sample_rate != 8000) && 731 (p->sample_rate != 11025) && 732 (p->sample_rate != 12000) && 733 (p->sample_rate != 16000) && 734 (p->sample_rate != 22050) && 735 (p->sample_rate != 24000) && 736 (p->sample_rate != 32000) && 737 (p->sample_rate != 44100) && 738 (p->sample_rate != 48000)) 739 return (EINVAL); 740 741 p->factor = 1; 742 if (p->precision == 8) 743 p->factor *= 2; 744 745 p->sw_code = NULL; 746 /* setup hardware formats */ 747 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 748 p->hw_precision = 16; 749 750 if (mode == AUMODE_RECORD) { 751 if (p->channels < 1 || p->channels > 2) 752 return EINVAL; 753 } else { 754 switch (p->channels) { 755 case 1: 756 break; 757 case 2: 758 break; 759 case 4: 760 if (!SUPPORTS_4CH(sc->codec_if)) 761 return EINVAL; 762 break; 763 case 6: 764 if (!SUPPORTS_6CH(sc->codec_if)) 765 return EINVAL; 766 break; 767 default: 768 return EINVAL; 769 } 770 } 771 /* If monaural is requested, aurateconv expands a monaural 772 * stream to stereo. */ 773 if (p->channels == 1) 774 p->hw_channels = 2; 775 776 switch (p->encoding) { 777 case AUDIO_ENCODING_SLINEAR_BE: 778 if (p->precision == 16) { 779 p->sw_code = swap_bytes; 780 } else { 781 if (mode == AUMODE_PLAY) 782 p->sw_code = linear8_to_linear16_le; 783 else 784 p->sw_code = linear16_to_linear8_le; 785 } 786 break; 787 788 case AUDIO_ENCODING_SLINEAR_LE: 789 if (p->precision != 16) { 790 if (mode == AUMODE_PLAY) 791 p->sw_code = linear8_to_linear16_le; 792 else 793 p->sw_code = linear16_to_linear8_le; 794 } 795 break; 796 797 case AUDIO_ENCODING_ULINEAR_BE: 798 if (p->precision == 16) { 799 if (mode == AUMODE_PLAY) 800 p->sw_code = 801 swap_bytes_change_sign16_le; 802 else 803 p->sw_code = 804 change_sign16_swap_bytes_le; 805 } else { 806 if (mode == AUMODE_PLAY) 807 p->sw_code = 808 ulinear8_to_slinear16_le; 809 else 810 p->sw_code = 811 slinear16_to_ulinear8_le; 812 } 813 break; 814 815 case AUDIO_ENCODING_ULINEAR_LE: 816 if (p->precision == 16) { 817 p->sw_code = change_sign16_le; 818 } else { 819 if (mode == AUMODE_PLAY) 820 p->sw_code = 821 ulinear8_to_slinear16_le; 822 else 823 p->sw_code = 824 slinear16_to_ulinear8_le; 825 } 826 break; 827 828 case AUDIO_ENCODING_ULAW: 829 if (mode == AUMODE_PLAY) { 830 p->sw_code = mulaw_to_slinear16_le; 831 } else { 832 p->sw_code = slinear16_to_mulaw_le; 833 } 834 break; 835 836 case AUDIO_ENCODING_ALAW: 837 if (mode == AUMODE_PLAY) { 838 p->sw_code = alaw_to_slinear16_le; 839 } else { 840 p->sw_code = slinear16_to_alaw_le; 841 } 842 break; 843 844 default: 845 return (EINVAL); 846 } 847 848 if (IS_FIXED_RATE(sc->codec_if)) { 849 p->hw_sample_rate = AC97_SINGLE_RATE; 850 /* If hw_sample_rate is changed, aurateconv works. */ 851 } else { 852 if (auich_set_rate(sc, mode, p->sample_rate)) 853 return EINVAL; 854 } 855 if (mode == AUMODE_PLAY) { 856 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 857 control &= ~ICH_PCM246_MASK; 858 if (p->channels == 4) { 859 control |= ICH_PCM4; 860 } else if (p->channels == 6) { 861 control |= ICH_PCM6; 862 } 863 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 864 } 865 } 866 867 return (0); 868 } 869 870 int 871 auich_round_blocksize(void *v, int blk) 872 { 873 874 return (blk & ~0x3f); /* keep good alignment */ 875 } 876 877 int 878 auich_halt_output(void *v) 879 { 880 struct auich_softc *sc = v; 881 882 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 883 884 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 885 886 return (0); 887 } 888 889 int 890 auich_halt_input(void *v) 891 { 892 struct auich_softc *sc = v; 893 894 DPRINTF(ICH_DEBUG_DMA, 895 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 896 897 /* XXX halt both unless known otherwise */ 898 899 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 900 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 901 902 return (0); 903 } 904 905 int 906 auich_getdev(void *v, struct audio_device *adp) 907 { 908 struct auich_softc *sc = v; 909 910 *adp = sc->sc_audev; 911 return (0); 912 } 913 914 int 915 auich_set_port(void *v, mixer_ctrl_t *cp) 916 { 917 struct auich_softc *sc = v; 918 919 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 920 } 921 922 int 923 auich_get_port(void *v, mixer_ctrl_t *cp) 924 { 925 struct auich_softc *sc = v; 926 927 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 928 } 929 930 int 931 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 932 { 933 struct auich_softc *sc = v; 934 935 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 936 } 937 938 void * 939 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 940 int flags) 941 { 942 struct auich_softc *sc = v; 943 struct auich_dma *p; 944 int error; 945 946 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 947 return (NULL); 948 949 p = malloc(sizeof(*p), pool, flags|M_ZERO); 950 if (p == NULL) 951 return (NULL); 952 953 error = auich_allocmem(sc, size, 0, p); 954 if (error) { 955 free(p, pool); 956 return (NULL); 957 } 958 959 p->next = sc->sc_dmas; 960 sc->sc_dmas = p; 961 962 return (KERNADDR(p)); 963 } 964 965 void 966 auich_freem(void *v, void *ptr, struct malloc_type *pool) 967 { 968 struct auich_softc *sc = v; 969 struct auich_dma *p, **pp; 970 971 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 972 if (KERNADDR(p) == ptr) { 973 auich_freemem(sc, p); 974 *pp = p->next; 975 free(p, pool); 976 return; 977 } 978 } 979 } 980 981 size_t 982 auich_round_buffersize(void *v, int direction, size_t size) 983 { 984 985 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 986 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 987 988 return size; 989 } 990 991 paddr_t 992 auich_mappage(void *v, void *mem, off_t off, int prot) 993 { 994 struct auich_softc *sc = v; 995 struct auich_dma *p; 996 997 if (off < 0) 998 return (-1); 999 1000 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1001 ; 1002 if (!p) 1003 return (-1); 1004 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1005 off, prot, BUS_DMA_WAITOK)); 1006 } 1007 1008 int 1009 auich_get_props(void *v) 1010 { 1011 struct auich_softc *sc = v; 1012 int props; 1013 1014 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1015 /* 1016 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1017 * rate because of aurateconv. Applications can't know what rate the 1018 * device can process in the case of mmap(). 1019 */ 1020 if (!IS_FIXED_RATE(sc->codec_if)) 1021 props |= AUDIO_PROP_MMAP; 1022 return props; 1023 } 1024 1025 int 1026 auich_intr(void *v) 1027 { 1028 struct auich_softc *sc = v; 1029 int ret = 0, sts, gsts, i, qptr; 1030 1031 #ifdef DIAGNOSTIC 1032 int csts; 1033 #endif 1034 1035 #ifdef DIAGNOSTIC 1036 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1037 if (csts & PCI_STATUS_MASTER_ABORT) { 1038 printf("auich_intr: PCI master abort\n"); 1039 } 1040 #endif 1041 1042 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 1043 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 1044 1045 if (gsts & ICH_POINT) { 1046 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 1047 DPRINTF(ICH_DEBUG_DMA, 1048 ("auich_intr: osts=0x%x\n", sts)); 1049 1050 if (sts & ICH_FIFOE) { 1051 printf("%s: fifo underrun # %u\n", 1052 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1053 } 1054 1055 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1056 if (sts & (ICH_LVBCI | ICH_CELV)) { 1057 struct auich_dmalist *q; 1058 1059 qptr = sc->ptr_pcmo; 1060 1061 while (qptr != i) { 1062 q = &sc->dmalist_pcmo[qptr]; 1063 1064 q->base = sc->pcmo_p; 1065 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1066 DPRINTF(ICH_DEBUG_DMA, 1067 ("auich_intr: %p, %p = %x @ 0x%x\n", 1068 &sc->dmalist_pcmo[i], q, 1069 sc->pcmo_blksize / 2, sc->pcmo_p)); 1070 1071 sc->pcmo_p += sc->pcmo_blksize; 1072 if (sc->pcmo_p >= sc->pcmo_end) 1073 sc->pcmo_p = sc->pcmo_start; 1074 1075 if (++qptr == ICH_DMALIST_MAX) 1076 qptr = 0; 1077 } 1078 1079 sc->ptr_pcmo = qptr; 1080 bus_space_write_1(sc->iot, sc->aud_ioh, 1081 ICH_PCMO + ICH_LVI, 1082 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1083 } 1084 1085 if (sts & ICH_BCIS && sc->sc_pintr) 1086 sc->sc_pintr(sc->sc_parg); 1087 1088 /* int ack */ 1089 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1090 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1091 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1092 ret++; 1093 } 1094 1095 if (gsts & ICH_PIINT) { 1096 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1097 DPRINTF(ICH_DEBUG_DMA, 1098 ("auich_intr: ists=0x%x\n", sts)); 1099 1100 if (sts & ICH_FIFOE) { 1101 printf("%s: fifo overrun # %u\n", 1102 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1103 } 1104 1105 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1106 if (sts & (ICH_LVBCI | ICH_CELV)) { 1107 struct auich_dmalist *q; 1108 1109 qptr = sc->ptr_pcmi; 1110 1111 while (qptr != i) { 1112 q = &sc->dmalist_pcmi[qptr]; 1113 1114 q->base = sc->pcmi_p; 1115 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1116 DPRINTF(ICH_DEBUG_DMA, 1117 ("auich_intr: %p, %p = %x @ 0x%x\n", 1118 &sc->dmalist_pcmi[i], q, 1119 sc->pcmi_blksize / 2, sc->pcmi_p)); 1120 1121 sc->pcmi_p += sc->pcmi_blksize; 1122 if (sc->pcmi_p >= sc->pcmi_end) 1123 sc->pcmi_p = sc->pcmi_start; 1124 1125 if (++qptr == ICH_DMALIST_MAX) 1126 qptr = 0; 1127 } 1128 1129 sc->ptr_pcmi = qptr; 1130 bus_space_write_1(sc->iot, sc->aud_ioh, 1131 ICH_PCMI + ICH_LVI, 1132 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1133 } 1134 1135 if (sts & ICH_BCIS && sc->sc_rintr) 1136 sc->sc_rintr(sc->sc_rarg); 1137 1138 /* int ack */ 1139 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1140 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1141 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1142 ret++; 1143 } 1144 1145 if (gsts & ICH_MIINT) { 1146 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1147 DPRINTF(ICH_DEBUG_DMA, 1148 ("auich_intr: ists=0x%x\n", sts)); 1149 if (sts & ICH_FIFOE) 1150 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1151 1152 /* TODO mic input DMA */ 1153 1154 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1155 } 1156 1157 return ret; 1158 } 1159 1160 int 1161 auich_trigger_output(void *v, void *start, void *end, int blksize, 1162 void (*intr)(void *), void *arg, struct audio_params *param) 1163 { 1164 struct auich_softc *sc = v; 1165 struct auich_dmalist *q; 1166 struct auich_dma *p; 1167 size_t size; 1168 #ifdef DIAGNOSTIC 1169 int csts; 1170 #endif 1171 1172 DPRINTF(ICH_DEBUG_DMA, 1173 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1174 start, end, blksize, intr, arg, param)); 1175 1176 sc->sc_pintr = intr; 1177 sc->sc_parg = arg; 1178 #ifdef DIAGNOSTIC 1179 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1180 if (csts & PCI_STATUS_MASTER_ABORT) { 1181 printf("auich_trigger_output: PCI master abort\n"); 1182 } 1183 #endif 1184 1185 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1186 ; 1187 if (!p) { 1188 printf("auich_trigger_output: bad addr %p\n", start); 1189 return (EINVAL); 1190 } 1191 1192 size = (size_t)((caddr_t)end - (caddr_t)start); 1193 1194 /* 1195 * The logic behind this is: 1196 * setup one buffer to play, then LVI dump out the rest 1197 * to the scatter-gather chain. 1198 */ 1199 sc->pcmo_start = DMAADDR(p); 1200 sc->pcmo_p = sc->pcmo_start + blksize; 1201 sc->pcmo_end = sc->pcmo_start + size; 1202 sc->pcmo_blksize = blksize; 1203 1204 sc->ptr_pcmo = 0; 1205 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1206 q->base = sc->pcmo_start; 1207 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1208 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1209 sc->ptr_pcmo = 0; 1210 1211 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1212 sc->sc_cddma + ICH_PCMO_OFF(0)); 1213 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1214 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1215 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1216 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1217 1218 return (0); 1219 } 1220 1221 int 1222 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1223 void *v; 1224 void *start, *end; 1225 int blksize; 1226 void (*intr)(void *); 1227 void *arg; 1228 struct audio_params *param; 1229 { 1230 struct auich_softc *sc = v; 1231 struct auich_dmalist *q; 1232 struct auich_dma *p; 1233 size_t size; 1234 #ifdef DIAGNOSTIC 1235 int csts; 1236 #endif 1237 1238 DPRINTF(ICH_DEBUG_DMA, 1239 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1240 start, end, blksize, intr, arg, param)); 1241 1242 sc->sc_rintr = intr; 1243 sc->sc_rarg = arg; 1244 1245 #ifdef DIAGNOSTIC 1246 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1247 if (csts & PCI_STATUS_MASTER_ABORT) { 1248 printf("auich_trigger_input: PCI master abort\n"); 1249 } 1250 #endif 1251 1252 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1253 ; 1254 if (!p) { 1255 printf("auich_trigger_input: bad addr %p\n", start); 1256 return (EINVAL); 1257 } 1258 1259 size = (size_t)((caddr_t)end - (caddr_t)start); 1260 1261 /* 1262 * The logic behind this is: 1263 * setup one buffer to play, then LVI dump out the rest 1264 * to the scatter-gather chain. 1265 */ 1266 sc->pcmi_start = DMAADDR(p); 1267 sc->pcmi_p = sc->pcmi_start + blksize; 1268 sc->pcmi_end = sc->pcmi_start + size; 1269 sc->pcmi_blksize = blksize; 1270 1271 sc->ptr_pcmi = 0; 1272 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1273 q->base = sc->pcmi_start; 1274 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1275 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1276 sc->ptr_pcmi = 0; 1277 1278 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1279 sc->sc_cddma + ICH_PCMI_OFF(0)); 1280 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1281 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1282 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1283 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1284 1285 return (0); 1286 } 1287 1288 int 1289 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1290 struct auich_dma *p) 1291 { 1292 int error; 1293 1294 p->size = size; 1295 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1296 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1297 &p->nsegs, BUS_DMA_NOWAIT); 1298 if (error) 1299 return (error); 1300 1301 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1302 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1303 if (error) 1304 goto free; 1305 1306 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1307 0, BUS_DMA_NOWAIT, &p->map); 1308 if (error) 1309 goto unmap; 1310 1311 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1312 BUS_DMA_NOWAIT); 1313 if (error) 1314 goto destroy; 1315 return (0); 1316 1317 destroy: 1318 bus_dmamap_destroy(sc->dmat, p->map); 1319 unmap: 1320 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1321 free: 1322 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1323 return (error); 1324 } 1325 1326 int 1327 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1328 { 1329 1330 bus_dmamap_unload(sc->dmat, p->map); 1331 bus_dmamap_destroy(sc->dmat, p->map); 1332 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1333 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1334 return (0); 1335 } 1336 1337 int 1338 auich_alloc_cdata(struct auich_softc *sc) 1339 { 1340 bus_dma_segment_t seg; 1341 int error, rseg; 1342 1343 /* 1344 * Allocate the control data structure, and create and load the 1345 * DMA map for it. 1346 */ 1347 if ((error = bus_dmamem_alloc(sc->dmat, 1348 sizeof(struct auich_cdata), 1349 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1350 printf("%s: unable to allocate control data, error = %d\n", 1351 sc->sc_dev.dv_xname, error); 1352 goto fail_0; 1353 } 1354 1355 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1356 sizeof(struct auich_cdata), 1357 (caddr_t *) &sc->sc_cdata, 1358 sc->sc_dmamap_flags)) != 0) { 1359 printf("%s: unable to map control data, error = %d\n", 1360 sc->sc_dev.dv_xname, error); 1361 goto fail_1; 1362 } 1363 1364 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1365 sizeof(struct auich_cdata), 0, 0, 1366 &sc->sc_cddmamap)) != 0) { 1367 printf("%s: unable to create control data DMA map, " 1368 "error = %d\n", sc->sc_dev.dv_xname, error); 1369 goto fail_2; 1370 } 1371 1372 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1373 sc->sc_cdata, sizeof(struct auich_cdata), 1374 NULL, 0)) != 0) { 1375 printf("%s: unable tp load control data DMA map, " 1376 "error = %d\n", sc->sc_dev.dv_xname, error); 1377 goto fail_3; 1378 } 1379 1380 return (0); 1381 1382 fail_3: 1383 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1384 fail_2: 1385 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1386 sizeof(struct auich_cdata)); 1387 fail_1: 1388 bus_dmamem_free(sc->dmat, &seg, rseg); 1389 fail_0: 1390 return (error); 1391 } 1392 1393 void 1394 auich_powerhook(int why, void *addr) 1395 { 1396 struct auich_softc *sc = (struct auich_softc *)addr; 1397 1398 switch (why) { 1399 case PWR_SUSPEND: 1400 case PWR_STANDBY: 1401 /* Power down */ 1402 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1403 sc->sc_suspend = why; 1404 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1405 break; 1406 1407 case PWR_RESUME: 1408 /* Wake up */ 1409 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1410 if (sc->sc_suspend == PWR_RESUME) { 1411 printf("%s: resume without suspend.\n", 1412 sc->sc_dev.dv_xname); 1413 sc->sc_suspend = why; 1414 return; 1415 } 1416 sc->sc_suspend = why; 1417 auich_reset_codec(sc); 1418 DELAY(1000); 1419 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1420 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1421 break; 1422 1423 case PWR_SOFTSUSPEND: 1424 case PWR_SOFTSTANDBY: 1425 case PWR_SOFTRESUME: 1426 break; 1427 } 1428 } 1429 1430 1431 /* -------------------------------------------------------------------- */ 1432 /* Calibrate card (some boards are overclocked and need scaling) */ 1433 1434 void 1435 auich_calibrate(struct auich_softc *sc) 1436 { 1437 struct timeval t1, t2; 1438 uint8_t ociv, nciv; 1439 uint64_t wait_us; 1440 uint32_t actual_48k_rate, bytes, ac97rate; 1441 void *temp_buffer; 1442 struct auich_dma *p; 1443 u_long rate; 1444 1445 /* 1446 * Grab audio from input for fixed interval and compare how 1447 * much we actually get with what we expect. Interval needs 1448 * to be sufficiently short that no interrupts are 1449 * generated. 1450 */ 1451 1452 /* Force the codec to a known state first. */ 1453 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1454 rate = 48000; 1455 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1456 &rate); 1457 1458 /* Setup a buffer */ 1459 bytes = 64000; 1460 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1461 1462 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1463 ; 1464 if (p == NULL) { 1465 printf("auich_calibrate: bad address %p\n", temp_buffer); 1466 return; 1467 } 1468 sc->dmalist_pcmi[0].base = DMAADDR(p); 1469 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size); 1470 1471 /* 1472 * our data format is stereo, 16 bit so each sample is 4 bytes. 1473 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1474 * we're going to start recording with interrupts disabled and measure 1475 * the time taken for one block to complete. we know the block size, 1476 * we know the time in microseconds, we calculate the sample rate: 1477 * 1478 * actual_rate [bps] = bytes / (time [s] * 4) 1479 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1480 * actual_rate [Hz] = (bytes * 250000) / time [us] 1481 */ 1482 1483 /* prepare */ 1484 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1485 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1486 sc->sc_cddma + ICH_PCMI_OFF(0)); 1487 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1488 (0 - 1) & ICH_LVI_MASK); 1489 1490 /* start */ 1491 microtime(&t1); 1492 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1493 1494 /* wait */ 1495 nciv = ociv; 1496 do { 1497 microtime(&t2); 1498 if (t2.tv_sec - t1.tv_sec > 1) 1499 break; 1500 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1501 ICH_PCMI + ICH_CIV); 1502 } while (nciv == ociv); 1503 microtime(&t2); 1504 1505 /* stop */ 1506 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1507 1508 /* reset */ 1509 DELAY(100); 1510 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1511 1512 /* turn time delta into us */ 1513 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1514 1515 auich_freem(sc, temp_buffer, M_DEVBUF); 1516 1517 if (nciv == ociv) { 1518 printf("%s: ac97 link rate calibration timed out after %" 1519 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1520 return; 1521 } 1522 1523 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1524 1525 if (actual_48k_rate < 50000) 1526 ac97rate = 48000; 1527 else 1528 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1529 1530 printf("%s: measured ac97 link rate at %d Hz", 1531 sc->sc_dev.dv_xname, actual_48k_rate); 1532 if (ac97rate != actual_48k_rate) 1533 printf(", will use %d Hz", ac97rate); 1534 printf("\n"); 1535 1536 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1537 } 1538
Indexes created Thu Oct 23 18:09:57 GMT 2025