auich.c revision 1.55
1 /* $NetBSD: auich.c,v 1.55 2003/11/22 08:49:41 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.55 2003/11/22 08:49:41 kent Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 131 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 132 133 #include <dev/pci/pcidevs.h> 134 #include <dev/pci/pcivar.h> 135 #include <dev/pci/auichreg.h> 136 137 #include <sys/audioio.h> 138 #include <dev/audio_if.h> 139 #include <dev/mulaw.h> 140 #include <dev/auconv.h> 141 142 #include <machine/bus.h> 143 144 #include <dev/ic/ac97reg.h> 145 #include <dev/ic/ac97var.h> 146 147 struct auich_dma { 148 bus_dmamap_t map; 149 caddr_t addr; 150 bus_dma_segment_t segs[1]; 151 int nsegs; 152 size_t size; 153 struct auich_dma *next; 154 }; 155 156 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 157 #define KERNADDR(p) ((void *)((p)->addr)) 158 159 struct auich_cdata { 160 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 161 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 163 }; 164 165 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 166 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 167 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 168 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 169 170 struct auich_softc { 171 struct device sc_dev; 172 void *sc_ih; 173 174 audio_device_t sc_audev; 175 176 bus_space_tag_t iot; 177 bus_space_handle_t mix_ioh; 178 bus_space_handle_t aud_ioh; 179 bus_dma_tag_t dmat; 180 181 struct ac97_codec_if *codec_if; 182 struct ac97_host_if host_if; 183 184 /* DMA scatter-gather lists. */ 185 bus_dmamap_t sc_cddmamap; 186 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 187 188 struct auich_cdata *sc_cdata; 189 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 190 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 191 #define dmalist_mici sc_cdata->ic_dmalist_mici 192 193 int ptr_pcmo, 194 ptr_pcmi, 195 ptr_mici; 196 197 /* i/o buffer pointers */ 198 u_int32_t pcmo_start, pcmo_p, pcmo_end; 199 int pcmo_blksize, pcmo_fifoe; 200 201 u_int32_t pcmi_start, pcmi_p, pcmi_end; 202 int pcmi_blksize, pcmi_fifoe; 203 204 u_int32_t mici_start, mici_p, mici_end; 205 int mici_blksize, mici_fifoe; 206 207 struct auich_dma *sc_dmas; 208 209 #ifdef DIAGNOSTIC 210 pci_chipset_tag_t sc_pc; 211 pcitag_t sc_pt; 212 #endif 213 /* SiS 7012 hack */ 214 int sc_sample_size; 215 int sc_sts_reg; 216 /* 440MX workaround */ 217 int sc_dmamap_flags; 218 219 void (*sc_pintr)(void *); 220 void *sc_parg; 221 222 void (*sc_rintr)(void *); 223 void *sc_rarg; 224 225 /* Power Management */ 226 void *sc_powerhook; 227 int sc_suspend; 228 u_int16_t ext_status; 229 }; 230 231 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 232 & AC97_EXT_AUDIO_VRA) 233 #define SUPPORTS_4CH(codec) ((codec)->vtbl->get_extcaps(codec) \ 234 & AC97_EXT_AUDIO_SDAC) 235 #define AC97_6CH_DACS (AC97_EXT_AUDIO_SDAC | AC97_EXT_AUDIO_CDAC \ 236 | AC97_EXT_AUDIO_LDAC) 237 #define SUPPORTS_6CH(codec) (((codec)->vtbl->get_extcaps(codec) \ 238 & AC97_6CH_DACS) == AC97_6CH_DACS) 239 240 /* Debug */ 241 #ifdef AUDIO_DEBUG 242 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 243 int auich_debug = 0xfffe; 244 #define ICH_DEBUG_CODECIO 0x0001 245 #define ICH_DEBUG_DMA 0x0002 246 #define ICH_DEBUG_PARAM 0x0004 247 #else 248 #define DPRINTF(x,y) /* nothing */ 249 #endif 250 251 int auich_match(struct device *, struct cfdata *, void *); 252 void auich_attach(struct device *, struct device *, void *); 253 int auich_intr(void *); 254 255 CFATTACH_DECL(auich, sizeof(struct auich_softc), 256 auich_match, auich_attach, NULL, NULL); 257 258 int auich_open(void *, int); 259 void auich_close(void *); 260 int auich_query_encoding(void *, struct audio_encoding *); 261 int auich_set_params(void *, int, int, struct audio_params *, 262 struct audio_params *); 263 int auich_round_blocksize(void *, int); 264 int auich_halt_output(void *); 265 int auich_halt_input(void *); 266 int auich_getdev(void *, struct audio_device *); 267 int auich_set_port(void *, mixer_ctrl_t *); 268 int auich_get_port(void *, mixer_ctrl_t *); 269 int auich_query_devinfo(void *, mixer_devinfo_t *); 270 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 271 void auich_freem(void *, void *, struct malloc_type *); 272 size_t auich_round_buffersize(void *, int, size_t); 273 paddr_t auich_mappage(void *, void *, off_t, int); 274 int auich_get_props(void *); 275 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 276 void *, struct audio_params *); 277 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 278 void *, struct audio_params *); 279 280 int auich_alloc_cdata(struct auich_softc *); 281 282 int auich_allocmem(struct auich_softc *, size_t, size_t, 283 struct auich_dma *); 284 int auich_freemem(struct auich_softc *, struct auich_dma *); 285 286 void auich_powerhook(int, void *); 287 int auich_set_rate(struct auich_softc *, int, u_long); 288 void auich_finish_attach(struct device *); 289 void auich_calibrate(struct auich_softc *); 290 291 292 struct audio_hw_if auich_hw_if = { 293 auich_open, 294 auich_close, 295 NULL, /* drain */ 296 auich_query_encoding, 297 auich_set_params, 298 auich_round_blocksize, 299 NULL, /* commit_setting */ 300 NULL, /* init_output */ 301 NULL, /* init_input */ 302 NULL, /* start_output */ 303 NULL, /* start_input */ 304 auich_halt_output, 305 auich_halt_input, 306 NULL, /* speaker_ctl */ 307 auich_getdev, 308 NULL, /* getfd */ 309 auich_set_port, 310 auich_get_port, 311 auich_query_devinfo, 312 auich_allocm, 313 auich_freem, 314 auich_round_buffersize, 315 auich_mappage, 316 auich_get_props, 317 auich_trigger_output, 318 auich_trigger_input, 319 NULL, /* dev_ioctl */ 320 }; 321 322 int auich_attach_codec(void *, struct ac97_codec_if *); 323 int auich_read_codec(void *, u_int8_t, u_int16_t *); 324 int auich_write_codec(void *, u_int8_t, u_int16_t); 325 void auich_reset_codec(void *); 326 327 static const struct auich_devtype { 328 int vendor; 329 int product; 330 const char *name; 331 const char *shortname; /* must be less than 11 characters */ 332 } auich_devices[] = { 333 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 334 "i82801AA (ICH) AC-97 Audio", "ICH" }, 335 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 336 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 337 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 338 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 339 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 340 "i82440MX AC-97 Audio", "440MX" }, 341 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 342 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 343 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 344 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 345 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 346 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 347 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 348 "SiS 7012 AC-97 Audio", "SiS7012" }, 349 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 350 "nForce MCP AC-97 Audio", "nForce" }, 351 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 352 "nForce2 MCP-T AC-97 Audio", "nForce2" }, 353 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 354 "nForce3 MCP-T AC-97 Audio", "nForce3" }, 355 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 356 "AMD768 AC-97 Audio", "AMD768" }, 357 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 358 "AMD8111 AC-97 Audio", "AMD8111" }, 359 { 0, 0, 360 NULL, NULL }, 361 }; 362 363 static const struct auich_devtype * 364 auich_lookup(struct pci_attach_args *pa) 365 { 366 const struct auich_devtype *d; 367 368 for (d = auich_devices; d->name != NULL; d++) { 369 if (PCI_VENDOR(pa->pa_id) == d->vendor 370 && PCI_PRODUCT(pa->pa_id) == d->product) 371 return (d); 372 } 373 374 return (NULL); 375 } 376 377 int 378 auich_match(struct device *parent, struct cfdata *match, void *aux) 379 { 380 struct pci_attach_args *pa = aux; 381 382 if (auich_lookup(pa) != NULL) 383 return (1); 384 385 return (0); 386 } 387 388 void 389 auich_attach(struct device *parent, struct device *self, void *aux) 390 { 391 struct auich_softc *sc = (struct auich_softc *)self; 392 struct pci_attach_args *pa = aux; 393 pci_intr_handle_t ih; 394 bus_size_t mix_size, aud_size; 395 pcireg_t v; 396 const char *intrstr; 397 const struct auich_devtype *d; 398 399 aprint_naive(": Audio controller\n"); 400 401 d = auich_lookup(pa); 402 if (d == NULL) 403 panic("auich_attach: impossible"); 404 405 #ifdef DIAGNOSTIC 406 sc->sc_pc = pa->pa_pc; 407 sc->sc_pt = pa->pa_tag; 408 #endif 409 410 aprint_normal(": %s\n", d->name); 411 412 if ((d->vendor == PCI_VENDOR_INTEL 413 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) 414 || (d->vendor == PCI_VENDOR_INTEL 415 && d->product == PCI_PRODUCT_INTEL_82801EB_AC)) { 416 /* 417 * Use native mode for ICH4/ICH5 418 */ 419 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 420 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 421 aprint_error("%s: can't map codec i/o space\n", 422 sc->sc_dev.dv_xname); 423 return; 424 } 425 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 426 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 427 aprint_error("%s: can't map device i/o space\n", 428 sc->sc_dev.dv_xname); 429 return; 430 } 431 } else { 432 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 433 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 434 aprint_error("%s: can't map codec i/o space\n", 435 sc->sc_dev.dv_xname); 436 return; 437 } 438 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 439 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 440 aprint_error("%s: can't map device i/o space\n", 441 sc->sc_dev.dv_xname); 442 return; 443 } 444 } 445 sc->dmat = pa->pa_dmat; 446 447 /* enable bus mastering */ 448 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 449 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 450 v | PCI_COMMAND_MASTER_ENABLE); 451 452 /* Map and establish the interrupt. */ 453 if (pci_intr_map(pa, &ih)) { 454 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 455 return; 456 } 457 intrstr = pci_intr_string(pa->pa_pc, ih); 458 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 459 auich_intr, sc); 460 if (sc->sc_ih == NULL) { 461 aprint_error("%s: can't establish interrupt", 462 sc->sc_dev.dv_xname); 463 if (intrstr != NULL) 464 aprint_normal(" at %s", intrstr); 465 aprint_normal("\n"); 466 return; 467 } 468 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 469 470 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 471 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 472 "0x%02x", PCI_REVISION(pa->pa_class)); 473 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 474 475 /* SiS 7012 needs special handling */ 476 if (d->vendor == PCI_VENDOR_SIS 477 && d->product == PCI_PRODUCT_SIS_7012_AC) { 478 sc->sc_sts_reg = ICH_PICB; 479 sc->sc_sample_size = 1; 480 } else { 481 sc->sc_sts_reg = ICH_STS; 482 sc->sc_sample_size = 2; 483 } 484 485 /* Workaround for a 440MX B-stepping erratum */ 486 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 487 if (d->vendor == PCI_VENDOR_INTEL 488 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 489 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 490 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 491 } 492 493 /* Set up DMA lists. */ 494 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 495 auich_alloc_cdata(sc); 496 497 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 498 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 499 500 sc->host_if.arg = sc; 501 sc->host_if.attach = auich_attach_codec; 502 sc->host_if.read = auich_read_codec; 503 sc->host_if.write = auich_write_codec; 504 sc->host_if.reset = auich_reset_codec; 505 506 if (ac97_attach(&sc->host_if) != 0) 507 return; 508 509 /* Watch for power change */ 510 sc->sc_suspend = PWR_RESUME; 511 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 512 513 config_interrupts(self, auich_finish_attach); 514 } 515 516 void 517 auich_finish_attach(struct device *self) 518 { 519 struct auich_softc *sc = (void *)self; 520 521 if (!IS_FIXED_RATE(sc->codec_if)) 522 auich_calibrate(sc); 523 524 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 525 } 526 527 #define ICH_CODECIO_INTERVAL 10 528 int 529 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 530 { 531 struct auich_softc *sc = v; 532 int i; 533 uint32_t status; 534 535 /* wait for an access semaphore */ 536 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 537 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 538 DELAY(ICH_CODECIO_INTERVAL)); 539 540 if (i > 0) { 541 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 542 DPRINTF(ICH_DEBUG_CODECIO, 543 ("auich_read_codec(%x, %x)\n", reg, *val)); 544 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 545 if (status & ICH_RCS) { 546 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 547 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 548 *val = 0xffff; 549 } 550 return 0; 551 } else { 552 DPRINTF(ICH_DEBUG_CODECIO, 553 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 554 return -1; 555 } 556 } 557 558 int 559 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 560 { 561 struct auich_softc *sc = v; 562 int i; 563 564 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 565 /* wait for an access semaphore */ 566 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 567 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 568 DELAY(ICH_CODECIO_INTERVAL)); 569 570 if (i > 0) { 571 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 572 return 0; 573 } else { 574 DPRINTF(ICH_DEBUG_CODECIO, 575 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 576 return -1; 577 } 578 } 579 580 int 581 auich_attach_codec(void *v, struct ac97_codec_if *cif) 582 { 583 struct auich_softc *sc = v; 584 585 sc->codec_if = cif; 586 return 0; 587 } 588 589 void 590 auich_reset_codec(void *v) 591 { 592 struct auich_softc *sc = v; 593 int i; 594 uint32_t control, status; 595 596 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 597 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 598 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 599 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 600 601 for (i = 500000; i >= 0; i--) { 602 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 603 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 604 break; 605 DELAY(1); 606 } 607 if (i <= 0) { 608 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 609 /* XXX: should not attach the audio device */ 610 } else { 611 if (status & ICH_SCR) 612 printf("%s: The 2nd codec is ready.\n", 613 sc->sc_dev.dv_xname); 614 if (status & ICH_S2CR) 615 printf("%s: The 3rd codec is ready.\n", 616 sc->sc_dev.dv_xname); 617 } 618 } 619 620 int 621 auich_open(void *v, int flags) 622 { 623 return 0; 624 } 625 626 void 627 auich_close(void *v) 628 { 629 struct auich_softc *sc = v; 630 631 auich_halt_output(sc); 632 auich_halt_input(sc); 633 634 sc->sc_pintr = NULL; 635 sc->sc_rintr = NULL; 636 } 637 638 int 639 auich_query_encoding(void *v, struct audio_encoding *aep) 640 { 641 642 switch (aep->index) { 643 case 0: 644 strcpy(aep->name, AudioEulinear); 645 aep->encoding = AUDIO_ENCODING_ULINEAR; 646 aep->precision = 8; 647 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 648 return (0); 649 case 1: 650 strcpy(aep->name, AudioEmulaw); 651 aep->encoding = AUDIO_ENCODING_ULAW; 652 aep->precision = 8; 653 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 654 return (0); 655 case 2: 656 strcpy(aep->name, AudioEalaw); 657 aep->encoding = AUDIO_ENCODING_ALAW; 658 aep->precision = 8; 659 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 660 return (0); 661 case 3: 662 strcpy(aep->name, AudioEslinear); 663 aep->encoding = AUDIO_ENCODING_SLINEAR; 664 aep->precision = 8; 665 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 666 return (0); 667 case 4: 668 strcpy(aep->name, AudioEslinear_le); 669 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 670 aep->precision = 16; 671 aep->flags = 0; 672 return (0); 673 case 5: 674 strcpy(aep->name, AudioEulinear_le); 675 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 676 aep->precision = 16; 677 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 678 return (0); 679 case 6: 680 strcpy(aep->name, AudioEslinear_be); 681 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 682 aep->precision = 16; 683 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 684 return (0); 685 case 7: 686 strcpy(aep->name, AudioEulinear_be); 687 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 688 aep->precision = 16; 689 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 690 return (0); 691 default: 692 return (EINVAL); 693 } 694 } 695 696 int 697 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 698 { 699 int ret; 700 u_long ratetmp; 701 702 ratetmp = srate; 703 if (mode == AUMODE_RECORD) 704 return sc->codec_if->vtbl->set_rate(sc->codec_if, 705 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 706 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 707 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 708 if (ret) 709 return ret; 710 ratetmp = srate; 711 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 712 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 713 if (ret) 714 return ret; 715 ratetmp = srate; 716 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 717 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 718 return ret; 719 } 720 721 int 722 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 723 struct audio_params *rec) 724 { 725 struct auich_softc *sc = v; 726 struct audio_params *p; 727 int mode; 728 u_int32_t control; 729 730 for (mode = AUMODE_RECORD; mode != -1; 731 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 732 if ((setmode & mode) == 0) 733 continue; 734 735 p = mode == AUMODE_PLAY ? play : rec; 736 if (p == NULL) 737 continue; 738 739 if ((p->sample_rate != 8000) && 740 (p->sample_rate != 11025) && 741 (p->sample_rate != 12000) && 742 (p->sample_rate != 16000) && 743 (p->sample_rate != 22050) && 744 (p->sample_rate != 24000) && 745 (p->sample_rate != 32000) && 746 (p->sample_rate != 44100) && 747 (p->sample_rate != 48000)) 748 return (EINVAL); 749 750 p->factor = 1; 751 if (p->precision == 8) 752 p->factor *= 2; 753 754 p->sw_code = NULL; 755 /* setup hardware formats */ 756 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 757 p->hw_precision = 16; 758 759 if (mode == AUMODE_RECORD) { 760 if (p->channels < 1 || p->channels > 2) 761 return EINVAL; 762 } else { 763 switch (p->channels) { 764 case 1: 765 break; 766 case 2: 767 break; 768 case 4: 769 if (!SUPPORTS_4CH(sc->codec_if)) 770 return EINVAL; 771 break; 772 case 6: 773 if (!SUPPORTS_6CH(sc->codec_if)) 774 return EINVAL; 775 break; 776 default: 777 return EINVAL; 778 } 779 } 780 /* If monaural is requested, aurateconv expands a monaural 781 * stream to stereo. */ 782 if (p->channels == 1) 783 p->hw_channels = 2; 784 785 switch (p->encoding) { 786 case AUDIO_ENCODING_SLINEAR_BE: 787 if (p->precision == 16) { 788 p->sw_code = swap_bytes; 789 } else { 790 if (mode == AUMODE_PLAY) 791 p->sw_code = linear8_to_linear16_le; 792 else 793 p->sw_code = linear16_to_linear8_le; 794 } 795 break; 796 797 case AUDIO_ENCODING_SLINEAR_LE: 798 if (p->precision != 16) { 799 if (mode == AUMODE_PLAY) 800 p->sw_code = linear8_to_linear16_le; 801 else 802 p->sw_code = linear16_to_linear8_le; 803 } 804 break; 805 806 case AUDIO_ENCODING_ULINEAR_BE: 807 if (p->precision == 16) { 808 if (mode == AUMODE_PLAY) 809 p->sw_code = 810 swap_bytes_change_sign16_le; 811 else 812 p->sw_code = 813 change_sign16_swap_bytes_le; 814 } else { 815 if (mode == AUMODE_PLAY) 816 p->sw_code = 817 ulinear8_to_slinear16_le; 818 else 819 p->sw_code = 820 slinear16_to_ulinear8_le; 821 } 822 break; 823 824 case AUDIO_ENCODING_ULINEAR_LE: 825 if (p->precision == 16) { 826 p->sw_code = change_sign16_le; 827 } else { 828 if (mode == AUMODE_PLAY) 829 p->sw_code = 830 ulinear8_to_slinear16_le; 831 else 832 p->sw_code = 833 slinear16_to_ulinear8_le; 834 } 835 break; 836 837 case AUDIO_ENCODING_ULAW: 838 if (mode == AUMODE_PLAY) { 839 p->sw_code = mulaw_to_slinear16_le; 840 } else { 841 p->sw_code = slinear16_to_mulaw_le; 842 } 843 break; 844 845 case AUDIO_ENCODING_ALAW: 846 if (mode == AUMODE_PLAY) { 847 p->sw_code = alaw_to_slinear16_le; 848 } else { 849 p->sw_code = slinear16_to_alaw_le; 850 } 851 break; 852 853 default: 854 return (EINVAL); 855 } 856 857 if (IS_FIXED_RATE(sc->codec_if)) { 858 p->hw_sample_rate = AC97_SINGLE_RATE; 859 /* If hw_sample_rate is changed, aurateconv works. */ 860 } else { 861 if (auich_set_rate(sc, mode, p->sample_rate)) 862 return EINVAL; 863 } 864 if (mode == AUMODE_PLAY) { 865 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 866 control &= ~ICH_PCM246_MASK; 867 if (p->channels == 4) { 868 control |= ICH_PCM4; 869 } else if (p->channels == 6) { 870 control |= ICH_PCM6; 871 } 872 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 873 } 874 } 875 876 return (0); 877 } 878 879 int 880 auich_round_blocksize(void *v, int blk) 881 { 882 883 return (blk & ~0x3f); /* keep good alignment */ 884 } 885 886 int 887 auich_halt_output(void *v) 888 { 889 struct auich_softc *sc = v; 890 891 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 892 893 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 894 895 return (0); 896 } 897 898 int 899 auich_halt_input(void *v) 900 { 901 struct auich_softc *sc = v; 902 903 DPRINTF(ICH_DEBUG_DMA, 904 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 905 906 /* XXX halt both unless known otherwise */ 907 908 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 909 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 910 911 return (0); 912 } 913 914 int 915 auich_getdev(void *v, struct audio_device *adp) 916 { 917 struct auich_softc *sc = v; 918 919 *adp = sc->sc_audev; 920 return (0); 921 } 922 923 int 924 auich_set_port(void *v, mixer_ctrl_t *cp) 925 { 926 struct auich_softc *sc = v; 927 928 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 929 } 930 931 int 932 auich_get_port(void *v, mixer_ctrl_t *cp) 933 { 934 struct auich_softc *sc = v; 935 936 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 937 } 938 939 int 940 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 941 { 942 struct auich_softc *sc = v; 943 944 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 945 } 946 947 void * 948 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 949 int flags) 950 { 951 struct auich_softc *sc = v; 952 struct auich_dma *p; 953 int error; 954 955 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 956 return (NULL); 957 958 p = malloc(sizeof(*p), pool, flags|M_ZERO); 959 if (p == NULL) 960 return (NULL); 961 962 error = auich_allocmem(sc, size, 0, p); 963 if (error) { 964 free(p, pool); 965 return (NULL); 966 } 967 968 p->next = sc->sc_dmas; 969 sc->sc_dmas = p; 970 971 return (KERNADDR(p)); 972 } 973 974 void 975 auich_freem(void *v, void *ptr, struct malloc_type *pool) 976 { 977 struct auich_softc *sc = v; 978 struct auich_dma *p, **pp; 979 980 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 981 if (KERNADDR(p) == ptr) { 982 auich_freemem(sc, p); 983 *pp = p->next; 984 free(p, pool); 985 return; 986 } 987 } 988 } 989 990 size_t 991 auich_round_buffersize(void *v, int direction, size_t size) 992 { 993 994 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 995 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 996 997 return size; 998 } 999 1000 paddr_t 1001 auich_mappage(void *v, void *mem, off_t off, int prot) 1002 { 1003 struct auich_softc *sc = v; 1004 struct auich_dma *p; 1005 1006 if (off < 0) 1007 return (-1); 1008 1009 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1010 ; 1011 if (!p) 1012 return (-1); 1013 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1014 off, prot, BUS_DMA_WAITOK)); 1015 } 1016 1017 int 1018 auich_get_props(void *v) 1019 { 1020 struct auich_softc *sc = v; 1021 int props; 1022 1023 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1024 /* 1025 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1026 * rate because of aurateconv. Applications can't know what rate the 1027 * device can process in the case of mmap(). 1028 */ 1029 if (!IS_FIXED_RATE(sc->codec_if)) 1030 props |= AUDIO_PROP_MMAP; 1031 return props; 1032 } 1033 1034 int 1035 auich_intr(void *v) 1036 { 1037 struct auich_softc *sc = v; 1038 int ret = 0, sts, gsts, i, qptr; 1039 1040 #ifdef DIAGNOSTIC 1041 int csts; 1042 #endif 1043 1044 #ifdef DIAGNOSTIC 1045 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1046 if (csts & PCI_STATUS_MASTER_ABORT) { 1047 printf("auich_intr: PCI master abort\n"); 1048 } 1049 #endif 1050 1051 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 1052 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 1053 1054 if (gsts & ICH_POINT) { 1055 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 1056 DPRINTF(ICH_DEBUG_DMA, 1057 ("auich_intr: osts=0x%x\n", sts)); 1058 1059 if (sts & ICH_FIFOE) { 1060 printf("%s: fifo underrun # %u\n", 1061 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1062 } 1063 1064 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1065 if (sts & (ICH_LVBCI | ICH_CELV)) { 1066 struct auich_dmalist *q; 1067 1068 qptr = sc->ptr_pcmo; 1069 1070 while (qptr != i) { 1071 q = &sc->dmalist_pcmo[qptr]; 1072 1073 q->base = sc->pcmo_p; 1074 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1075 DPRINTF(ICH_DEBUG_DMA, 1076 ("auich_intr: %p, %p = %x @ 0x%x\n", 1077 &sc->dmalist_pcmo[i], q, 1078 sc->pcmo_blksize / 2, sc->pcmo_p)); 1079 1080 sc->pcmo_p += sc->pcmo_blksize; 1081 if (sc->pcmo_p >= sc->pcmo_end) 1082 sc->pcmo_p = sc->pcmo_start; 1083 1084 if (++qptr == ICH_DMALIST_MAX) 1085 qptr = 0; 1086 } 1087 1088 sc->ptr_pcmo = qptr; 1089 bus_space_write_1(sc->iot, sc->aud_ioh, 1090 ICH_PCMO + ICH_LVI, 1091 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1092 } 1093 1094 if (sts & ICH_BCIS && sc->sc_pintr) 1095 sc->sc_pintr(sc->sc_parg); 1096 1097 /* int ack */ 1098 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1099 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1100 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1101 ret++; 1102 } 1103 1104 if (gsts & ICH_PIINT) { 1105 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1106 DPRINTF(ICH_DEBUG_DMA, 1107 ("auich_intr: ists=0x%x\n", sts)); 1108 1109 if (sts & ICH_FIFOE) { 1110 printf("%s: fifo overrun # %u\n", 1111 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1112 } 1113 1114 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1115 if (sts & (ICH_LVBCI | ICH_CELV)) { 1116 struct auich_dmalist *q; 1117 1118 qptr = sc->ptr_pcmi; 1119 1120 while (qptr != i) { 1121 q = &sc->dmalist_pcmi[qptr]; 1122 1123 q->base = sc->pcmi_p; 1124 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1125 DPRINTF(ICH_DEBUG_DMA, 1126 ("auich_intr: %p, %p = %x @ 0x%x\n", 1127 &sc->dmalist_pcmi[i], q, 1128 sc->pcmi_blksize / 2, sc->pcmi_p)); 1129 1130 sc->pcmi_p += sc->pcmi_blksize; 1131 if (sc->pcmi_p >= sc->pcmi_end) 1132 sc->pcmi_p = sc->pcmi_start; 1133 1134 if (++qptr == ICH_DMALIST_MAX) 1135 qptr = 0; 1136 } 1137 1138 sc->ptr_pcmi = qptr; 1139 bus_space_write_1(sc->iot, sc->aud_ioh, 1140 ICH_PCMI + ICH_LVI, 1141 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1142 } 1143 1144 if (sts & ICH_BCIS && sc->sc_rintr) 1145 sc->sc_rintr(sc->sc_rarg); 1146 1147 /* int ack */ 1148 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1149 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1150 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1151 ret++; 1152 } 1153 1154 if (gsts & ICH_MIINT) { 1155 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1156 DPRINTF(ICH_DEBUG_DMA, 1157 ("auich_intr: ists=0x%x\n", sts)); 1158 if (sts & ICH_FIFOE) 1159 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1160 1161 /* TODO mic input DMA */ 1162 1163 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1164 } 1165 1166 return ret; 1167 } 1168 1169 int 1170 auich_trigger_output(void *v, void *start, void *end, int blksize, 1171 void (*intr)(void *), void *arg, struct audio_params *param) 1172 { 1173 struct auich_softc *sc = v; 1174 struct auich_dmalist *q; 1175 struct auich_dma *p; 1176 size_t size; 1177 #ifdef DIAGNOSTIC 1178 int csts; 1179 #endif 1180 1181 DPRINTF(ICH_DEBUG_DMA, 1182 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1183 start, end, blksize, intr, arg, param)); 1184 1185 sc->sc_pintr = intr; 1186 sc->sc_parg = arg; 1187 #ifdef DIAGNOSTIC 1188 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1189 if (csts & PCI_STATUS_MASTER_ABORT) { 1190 printf("auich_trigger_output: PCI master abort\n"); 1191 } 1192 #endif 1193 1194 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1195 ; 1196 if (!p) { 1197 printf("auich_trigger_output: bad addr %p\n", start); 1198 return (EINVAL); 1199 } 1200 1201 size = (size_t)((caddr_t)end - (caddr_t)start); 1202 1203 /* 1204 * The logic behind this is: 1205 * setup one buffer to play, then LVI dump out the rest 1206 * to the scatter-gather chain. 1207 */ 1208 sc->pcmo_start = DMAADDR(p); 1209 sc->pcmo_p = sc->pcmo_start + blksize; 1210 sc->pcmo_end = sc->pcmo_start + size; 1211 sc->pcmo_blksize = blksize; 1212 1213 sc->ptr_pcmo = 0; 1214 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1215 q->base = sc->pcmo_start; 1216 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1217 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1218 sc->ptr_pcmo = 0; 1219 1220 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1221 sc->sc_cddma + ICH_PCMO_OFF(0)); 1222 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1223 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1224 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1225 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1226 1227 return (0); 1228 } 1229 1230 int 1231 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1232 void *v; 1233 void *start, *end; 1234 int blksize; 1235 void (*intr)(void *); 1236 void *arg; 1237 struct audio_params *param; 1238 { 1239 struct auich_softc *sc = v; 1240 struct auich_dmalist *q; 1241 struct auich_dma *p; 1242 size_t size; 1243 #ifdef DIAGNOSTIC 1244 int csts; 1245 #endif 1246 1247 DPRINTF(ICH_DEBUG_DMA, 1248 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1249 start, end, blksize, intr, arg, param)); 1250 1251 sc->sc_rintr = intr; 1252 sc->sc_rarg = arg; 1253 1254 #ifdef DIAGNOSTIC 1255 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1256 if (csts & PCI_STATUS_MASTER_ABORT) { 1257 printf("auich_trigger_input: PCI master abort\n"); 1258 } 1259 #endif 1260 1261 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1262 ; 1263 if (!p) { 1264 printf("auich_trigger_input: bad addr %p\n", start); 1265 return (EINVAL); 1266 } 1267 1268 size = (size_t)((caddr_t)end - (caddr_t)start); 1269 1270 /* 1271 * The logic behind this is: 1272 * setup one buffer to play, then LVI dump out the rest 1273 * to the scatter-gather chain. 1274 */ 1275 sc->pcmi_start = DMAADDR(p); 1276 sc->pcmi_p = sc->pcmi_start + blksize; 1277 sc->pcmi_end = sc->pcmi_start + size; 1278 sc->pcmi_blksize = blksize; 1279 1280 sc->ptr_pcmi = 0; 1281 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1282 q->base = sc->pcmi_start; 1283 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1284 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1285 sc->ptr_pcmi = 0; 1286 1287 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1288 sc->sc_cddma + ICH_PCMI_OFF(0)); 1289 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1290 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1291 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1292 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1293 1294 return (0); 1295 } 1296 1297 int 1298 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1299 struct auich_dma *p) 1300 { 1301 int error; 1302 1303 p->size = size; 1304 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1305 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1306 &p->nsegs, BUS_DMA_NOWAIT); 1307 if (error) 1308 return (error); 1309 1310 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1311 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1312 if (error) 1313 goto free; 1314 1315 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1316 0, BUS_DMA_NOWAIT, &p->map); 1317 if (error) 1318 goto unmap; 1319 1320 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1321 BUS_DMA_NOWAIT); 1322 if (error) 1323 goto destroy; 1324 return (0); 1325 1326 destroy: 1327 bus_dmamap_destroy(sc->dmat, p->map); 1328 unmap: 1329 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1330 free: 1331 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1332 return (error); 1333 } 1334 1335 int 1336 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1337 { 1338 1339 bus_dmamap_unload(sc->dmat, p->map); 1340 bus_dmamap_destroy(sc->dmat, p->map); 1341 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1342 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1343 return (0); 1344 } 1345 1346 int 1347 auich_alloc_cdata(struct auich_softc *sc) 1348 { 1349 bus_dma_segment_t seg; 1350 int error, rseg; 1351 1352 /* 1353 * Allocate the control data structure, and create and load the 1354 * DMA map for it. 1355 */ 1356 if ((error = bus_dmamem_alloc(sc->dmat, 1357 sizeof(struct auich_cdata), 1358 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1359 printf("%s: unable to allocate control data, error = %d\n", 1360 sc->sc_dev.dv_xname, error); 1361 goto fail_0; 1362 } 1363 1364 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1365 sizeof(struct auich_cdata), 1366 (caddr_t *) &sc->sc_cdata, 1367 sc->sc_dmamap_flags)) != 0) { 1368 printf("%s: unable to map control data, error = %d\n", 1369 sc->sc_dev.dv_xname, error); 1370 goto fail_1; 1371 } 1372 1373 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1374 sizeof(struct auich_cdata), 0, 0, 1375 &sc->sc_cddmamap)) != 0) { 1376 printf("%s: unable to create control data DMA map, " 1377 "error = %d\n", sc->sc_dev.dv_xname, error); 1378 goto fail_2; 1379 } 1380 1381 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1382 sc->sc_cdata, sizeof(struct auich_cdata), 1383 NULL, 0)) != 0) { 1384 printf("%s: unable tp load control data DMA map, " 1385 "error = %d\n", sc->sc_dev.dv_xname, error); 1386 goto fail_3; 1387 } 1388 1389 return (0); 1390 1391 fail_3: 1392 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1393 fail_2: 1394 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1395 sizeof(struct auich_cdata)); 1396 fail_1: 1397 bus_dmamem_free(sc->dmat, &seg, rseg); 1398 fail_0: 1399 return (error); 1400 } 1401 1402 void 1403 auich_powerhook(int why, void *addr) 1404 { 1405 struct auich_softc *sc = (struct auich_softc *)addr; 1406 1407 switch (why) { 1408 case PWR_SUSPEND: 1409 case PWR_STANDBY: 1410 /* Power down */ 1411 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1412 sc->sc_suspend = why; 1413 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1414 break; 1415 1416 case PWR_RESUME: 1417 /* Wake up */ 1418 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1419 if (sc->sc_suspend == PWR_RESUME) { 1420 printf("%s: resume without suspend.\n", 1421 sc->sc_dev.dv_xname); 1422 sc->sc_suspend = why; 1423 return; 1424 } 1425 sc->sc_suspend = why; 1426 auich_reset_codec(sc); 1427 DELAY(1000); 1428 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1429 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1430 break; 1431 1432 case PWR_SOFTSUSPEND: 1433 case PWR_SOFTSTANDBY: 1434 case PWR_SOFTRESUME: 1435 break; 1436 } 1437 } 1438 1439 1440 /* -------------------------------------------------------------------- */ 1441 /* Calibrate card (some boards are overclocked and need scaling) */ 1442 1443 void 1444 auich_calibrate(struct auich_softc *sc) 1445 { 1446 struct timeval t1, t2; 1447 uint8_t ociv, nciv; 1448 uint64_t wait_us; 1449 uint32_t actual_48k_rate, bytes, ac97rate; 1450 void *temp_buffer; 1451 struct auich_dma *p; 1452 u_long rate; 1453 1454 /* 1455 * Grab audio from input for fixed interval and compare how 1456 * much we actually get with what we expect. Interval needs 1457 * to be sufficiently short that no interrupts are 1458 * generated. 1459 */ 1460 1461 /* Force the codec to a known state first. */ 1462 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1463 rate = 48000; 1464 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1465 &rate); 1466 1467 /* Setup a buffer */ 1468 bytes = 64000; 1469 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1470 1471 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1472 ; 1473 if (p == NULL) { 1474 printf("auich_calibrate: bad address %p\n", temp_buffer); 1475 return; 1476 } 1477 sc->dmalist_pcmi[0].base = DMAADDR(p); 1478 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size); 1479 1480 /* 1481 * our data format is stereo, 16 bit so each sample is 4 bytes. 1482 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1483 * we're going to start recording with interrupts disabled and measure 1484 * the time taken for one block to complete. we know the block size, 1485 * we know the time in microseconds, we calculate the sample rate: 1486 * 1487 * actual_rate [bps] = bytes / (time [s] * 4) 1488 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1489 * actual_rate [Hz] = (bytes * 250000) / time [us] 1490 */ 1491 1492 /* prepare */ 1493 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1494 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1495 sc->sc_cddma + ICH_PCMI_OFF(0)); 1496 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1497 (0 - 1) & ICH_LVI_MASK); 1498 1499 /* start */ 1500 microtime(&t1); 1501 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1502 1503 /* wait */ 1504 nciv = ociv; 1505 do { 1506 microtime(&t2); 1507 if (t2.tv_sec - t1.tv_sec > 1) 1508 break; 1509 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1510 ICH_PCMI + ICH_CIV); 1511 } while (nciv == ociv); 1512 microtime(&t2); 1513 1514 /* stop */ 1515 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1516 1517 /* reset */ 1518 DELAY(100); 1519 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1520 1521 /* turn time delta into us */ 1522 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1523 1524 auich_freem(sc, temp_buffer, M_DEVBUF); 1525 1526 if (nciv == ociv) { 1527 printf("%s: ac97 link rate calibration timed out after %" 1528 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1529 return; 1530 } 1531 1532 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1533 1534 if (actual_48k_rate < 50000) 1535 ac97rate = 48000; 1536 else 1537 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1538 1539 printf("%s: measured ac97 link rate at %d Hz", 1540 sc->sc_dev.dv_xname, actual_48k_rate); 1541 if (ac97rate != actual_48k_rate) 1542 printf(", will use %d Hz", ac97rate); 1543 printf("\n"); 1544 1545 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1546 } 1547
Indexes created Thu Oct 23 22:10:10 GMT 2025