auich.c revision 1.56
1 /* $NetBSD: auich.c,v 1.56 2003/12/28 12:31:30 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.56 2003/12/28 12:31:30 kent Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 131 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 132 133 #include <dev/pci/pcidevs.h> 134 #include <dev/pci/pcivar.h> 135 #include <dev/pci/auichreg.h> 136 137 #include <sys/audioio.h> 138 #include <dev/audio_if.h> 139 #include <dev/mulaw.h> 140 #include <dev/auconv.h> 141 142 #include <machine/bus.h> 143 144 #include <dev/ic/ac97reg.h> 145 #include <dev/ic/ac97var.h> 146 147 struct auich_dma { 148 bus_dmamap_t map; 149 caddr_t addr; 150 bus_dma_segment_t segs[1]; 151 int nsegs; 152 size_t size; 153 struct auich_dma *next; 154 }; 155 156 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 157 #define KERNADDR(p) ((void *)((p)->addr)) 158 159 struct auich_cdata { 160 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 161 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 163 }; 164 165 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 166 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 167 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 168 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 169 170 struct auich_softc { 171 struct device sc_dev; 172 void *sc_ih; 173 174 audio_device_t sc_audev; 175 176 bus_space_tag_t iot; 177 bus_space_handle_t mix_ioh; 178 bus_space_handle_t aud_ioh; 179 bus_dma_tag_t dmat; 180 181 struct ac97_codec_if *codec_if; 182 struct ac97_host_if host_if; 183 184 /* DMA scatter-gather lists. */ 185 bus_dmamap_t sc_cddmamap; 186 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 187 188 struct auich_cdata *sc_cdata; 189 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 190 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 191 #define dmalist_mici sc_cdata->ic_dmalist_mici 192 193 int ptr_pcmo, 194 ptr_pcmi, 195 ptr_mici; 196 197 /* i/o buffer pointers */ 198 u_int32_t pcmo_start, pcmo_p, pcmo_end; 199 int pcmo_blksize, pcmo_fifoe; 200 201 u_int32_t pcmi_start, pcmi_p, pcmi_end; 202 int pcmi_blksize, pcmi_fifoe; 203 204 u_int32_t mici_start, mici_p, mici_end; 205 int mici_blksize, mici_fifoe; 206 207 struct auich_dma *sc_dmas; 208 209 #ifdef DIAGNOSTIC 210 pci_chipset_tag_t sc_pc; 211 pcitag_t sc_pt; 212 #endif 213 /* SiS 7012 hack */ 214 int sc_sample_size; 215 int sc_sts_reg; 216 /* 440MX workaround */ 217 int sc_dmamap_flags; 218 219 void (*sc_pintr)(void *); 220 void *sc_parg; 221 222 void (*sc_rintr)(void *); 223 void *sc_rarg; 224 225 /* Power Management */ 226 void *sc_powerhook; 227 int sc_suspend; 228 u_int16_t ext_status; 229 }; 230 231 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 232 & AC97_EXT_AUDIO_VRA) 233 #define SUPPORTS_4CH(codec) ((codec)->vtbl->get_extcaps(codec) \ 234 & AC97_EXT_AUDIO_SDAC) 235 #define AC97_6CH_DACS (AC97_EXT_AUDIO_SDAC | AC97_EXT_AUDIO_CDAC \ 236 | AC97_EXT_AUDIO_LDAC) 237 #define SUPPORTS_6CH(codec) (((codec)->vtbl->get_extcaps(codec) \ 238 & AC97_6CH_DACS) == AC97_6CH_DACS) 239 240 /* Debug */ 241 #ifdef AUDIO_DEBUG 242 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 243 int auich_debug = 0xfffe; 244 #define ICH_DEBUG_CODECIO 0x0001 245 #define ICH_DEBUG_DMA 0x0002 246 #define ICH_DEBUG_PARAM 0x0004 247 #else 248 #define DPRINTF(x,y) /* nothing */ 249 #endif 250 251 int auich_match(struct device *, struct cfdata *, void *); 252 void auich_attach(struct device *, struct device *, void *); 253 int auich_intr(void *); 254 255 CFATTACH_DECL(auich, sizeof(struct auich_softc), 256 auich_match, auich_attach, NULL, NULL); 257 258 int auich_open(void *, int); 259 void auich_close(void *); 260 int auich_query_encoding(void *, struct audio_encoding *); 261 int auich_set_params(void *, int, int, struct audio_params *, 262 struct audio_params *); 263 int auich_round_blocksize(void *, int); 264 int auich_halt_output(void *); 265 int auich_halt_input(void *); 266 int auich_getdev(void *, struct audio_device *); 267 int auich_set_port(void *, mixer_ctrl_t *); 268 int auich_get_port(void *, mixer_ctrl_t *); 269 int auich_query_devinfo(void *, mixer_devinfo_t *); 270 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 271 void auich_freem(void *, void *, struct malloc_type *); 272 size_t auich_round_buffersize(void *, int, size_t); 273 paddr_t auich_mappage(void *, void *, off_t, int); 274 int auich_get_props(void *); 275 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 276 void *, struct audio_params *); 277 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 278 void *, struct audio_params *); 279 280 int auich_alloc_cdata(struct auich_softc *); 281 282 int auich_allocmem(struct auich_softc *, size_t, size_t, 283 struct auich_dma *); 284 int auich_freemem(struct auich_softc *, struct auich_dma *); 285 286 void auich_powerhook(int, void *); 287 int auich_set_rate(struct auich_softc *, int, u_long); 288 void auich_finish_attach(struct device *); 289 void auich_calibrate(struct auich_softc *); 290 291 292 struct audio_hw_if auich_hw_if = { 293 auich_open, 294 auich_close, 295 NULL, /* drain */ 296 auich_query_encoding, 297 auich_set_params, 298 auich_round_blocksize, 299 NULL, /* commit_setting */ 300 NULL, /* init_output */ 301 NULL, /* init_input */ 302 NULL, /* start_output */ 303 NULL, /* start_input */ 304 auich_halt_output, 305 auich_halt_input, 306 NULL, /* speaker_ctl */ 307 auich_getdev, 308 NULL, /* getfd */ 309 auich_set_port, 310 auich_get_port, 311 auich_query_devinfo, 312 auich_allocm, 313 auich_freem, 314 auich_round_buffersize, 315 auich_mappage, 316 auich_get_props, 317 auich_trigger_output, 318 auich_trigger_input, 319 NULL, /* dev_ioctl */ 320 }; 321 322 int auich_attach_codec(void *, struct ac97_codec_if *); 323 int auich_read_codec(void *, u_int8_t, u_int16_t *); 324 int auich_write_codec(void *, u_int8_t, u_int16_t); 325 void auich_reset_codec(void *); 326 327 static const struct auich_devtype { 328 int vendor; 329 int product; 330 const char *name; 331 const char *shortname; /* must be less than 11 characters */ 332 } auich_devices[] = { 333 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 334 "i82801AA (ICH) AC-97 Audio", "ICH" }, 335 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 336 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 337 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 338 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 339 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 340 "i82440MX AC-97 Audio", "440MX" }, 341 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 342 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 343 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 344 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 345 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 346 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 347 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 348 "SiS 7012 AC-97 Audio", "SiS7012" }, 349 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 350 "nForce MCP AC-97 Audio", "nForce" }, 351 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 352 "nForce2 MCP-T AC-97 Audio", "nForce2" }, 353 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 354 "nForce3 MCP-T AC-97 Audio", "nForce3" }, 355 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 356 "AMD768 AC-97 Audio", "AMD768" }, 357 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 358 "AMD8111 AC-97 Audio", "AMD8111" }, 359 { 0, 0, 360 NULL, NULL }, 361 }; 362 363 static const struct auich_devtype * 364 auich_lookup(struct pci_attach_args *pa) 365 { 366 const struct auich_devtype *d; 367 368 for (d = auich_devices; d->name != NULL; d++) { 369 if (PCI_VENDOR(pa->pa_id) == d->vendor 370 && PCI_PRODUCT(pa->pa_id) == d->product) 371 return (d); 372 } 373 374 return (NULL); 375 } 376 377 int 378 auich_match(struct device *parent, struct cfdata *match, void *aux) 379 { 380 struct pci_attach_args *pa = aux; 381 382 if (auich_lookup(pa) != NULL) 383 return (1); 384 385 return (0); 386 } 387 388 void 389 auich_attach(struct device *parent, struct device *self, void *aux) 390 { 391 struct auich_softc *sc = (struct auich_softc *)self; 392 struct pci_attach_args *pa = aux; 393 pci_intr_handle_t ih; 394 bus_size_t mix_size, aud_size; 395 pcireg_t v; 396 const char *intrstr; 397 const struct auich_devtype *d; 398 399 aprint_naive(": Audio controller\n"); 400 401 d = auich_lookup(pa); 402 if (d == NULL) 403 panic("auich_attach: impossible"); 404 405 #ifdef DIAGNOSTIC 406 sc->sc_pc = pa->pa_pc; 407 sc->sc_pt = pa->pa_tag; 408 #endif 409 410 aprint_normal(": %s\n", d->name); 411 412 if ((d->vendor == PCI_VENDOR_INTEL 413 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) 414 || (d->vendor == PCI_VENDOR_INTEL 415 && d->product == PCI_PRODUCT_INTEL_82801EB_AC)) { 416 /* 417 * Use native mode for ICH4/ICH5 418 */ 419 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 420 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 421 aprint_error("%s: can't map native codec i/o space\n", 422 sc->sc_dev.dv_xname); 423 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 424 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 425 v | ICH_CFG_IOSE); 426 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 427 0, &sc->iot, &sc->mix_ioh, NULL, 428 &mix_size)) { 429 aprint_error("%s: can't map compatible codec " 430 "i/o space\n", 431 sc->sc_dev.dv_xname); 432 return; 433 } 434 } 435 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 436 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 437 aprint_error("%s: can't map native device i/o space\n", 438 sc->sc_dev.dv_xname); 439 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 440 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 441 v | ICH_CFG_IOSE); 442 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 443 0, &sc->iot, &sc->aud_ioh, NULL, 444 &aud_size)) { 445 aprint_error("%s: can't map compatible device " 446 "i/o space\n", 447 sc->sc_dev.dv_xname); 448 return; 449 } 450 } 451 } else { 452 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 453 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 454 aprint_error("%s: can't map codec i/o space\n", 455 sc->sc_dev.dv_xname); 456 return; 457 } 458 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 459 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 460 aprint_error("%s: can't map device i/o space\n", 461 sc->sc_dev.dv_xname); 462 return; 463 } 464 } 465 sc->dmat = pa->pa_dmat; 466 467 /* enable bus mastering */ 468 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 469 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 470 v | PCI_COMMAND_MASTER_ENABLE); 471 472 /* Map and establish the interrupt. */ 473 if (pci_intr_map(pa, &ih)) { 474 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 475 return; 476 } 477 intrstr = pci_intr_string(pa->pa_pc, ih); 478 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 479 auich_intr, sc); 480 if (sc->sc_ih == NULL) { 481 aprint_error("%s: can't establish interrupt", 482 sc->sc_dev.dv_xname); 483 if (intrstr != NULL) 484 aprint_normal(" at %s", intrstr); 485 aprint_normal("\n"); 486 return; 487 } 488 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 489 490 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 491 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 492 "0x%02x", PCI_REVISION(pa->pa_class)); 493 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 494 495 /* SiS 7012 needs special handling */ 496 if (d->vendor == PCI_VENDOR_SIS 497 && d->product == PCI_PRODUCT_SIS_7012_AC) { 498 sc->sc_sts_reg = ICH_PICB; 499 sc->sc_sample_size = 1; 500 } else { 501 sc->sc_sts_reg = ICH_STS; 502 sc->sc_sample_size = 2; 503 } 504 505 /* Workaround for a 440MX B-stepping erratum */ 506 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 507 if (d->vendor == PCI_VENDOR_INTEL 508 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 509 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 510 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 511 } 512 513 /* Set up DMA lists. */ 514 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 515 auich_alloc_cdata(sc); 516 517 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 518 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 519 520 sc->host_if.arg = sc; 521 sc->host_if.attach = auich_attach_codec; 522 sc->host_if.read = auich_read_codec; 523 sc->host_if.write = auich_write_codec; 524 sc->host_if.reset = auich_reset_codec; 525 526 if (ac97_attach(&sc->host_if) != 0) 527 return; 528 529 /* Watch for power change */ 530 sc->sc_suspend = PWR_RESUME; 531 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 532 533 config_interrupts(self, auich_finish_attach); 534 } 535 536 void 537 auich_finish_attach(struct device *self) 538 { 539 struct auich_softc *sc = (void *)self; 540 541 if (!IS_FIXED_RATE(sc->codec_if)) 542 auich_calibrate(sc); 543 544 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 545 } 546 547 #define ICH_CODECIO_INTERVAL 10 548 int 549 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 550 { 551 struct auich_softc *sc = v; 552 int i; 553 uint32_t status; 554 555 /* wait for an access semaphore */ 556 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 557 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 558 DELAY(ICH_CODECIO_INTERVAL)); 559 560 if (i > 0) { 561 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 562 DPRINTF(ICH_DEBUG_CODECIO, 563 ("auich_read_codec(%x, %x)\n", reg, *val)); 564 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 565 if (status & ICH_RCS) { 566 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 567 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 568 *val = 0xffff; 569 } 570 return 0; 571 } else { 572 DPRINTF(ICH_DEBUG_CODECIO, 573 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 574 return -1; 575 } 576 } 577 578 int 579 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 580 { 581 struct auich_softc *sc = v; 582 int i; 583 584 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 585 /* wait for an access semaphore */ 586 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 587 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 588 DELAY(ICH_CODECIO_INTERVAL)); 589 590 if (i > 0) { 591 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 592 return 0; 593 } else { 594 DPRINTF(ICH_DEBUG_CODECIO, 595 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 596 return -1; 597 } 598 } 599 600 int 601 auich_attach_codec(void *v, struct ac97_codec_if *cif) 602 { 603 struct auich_softc *sc = v; 604 605 sc->codec_if = cif; 606 return 0; 607 } 608 609 void 610 auich_reset_codec(void *v) 611 { 612 struct auich_softc *sc = v; 613 int i; 614 uint32_t control, status; 615 616 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 617 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 618 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 619 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 620 621 for (i = 500000; i >= 0; i--) { 622 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 623 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 624 break; 625 DELAY(1); 626 } 627 if (i <= 0) { 628 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 629 /* XXX: should not attach the audio device */ 630 } else { 631 if (status & ICH_SCR) 632 printf("%s: The 2nd codec is ready.\n", 633 sc->sc_dev.dv_xname); 634 if (status & ICH_S2CR) 635 printf("%s: The 3rd codec is ready.\n", 636 sc->sc_dev.dv_xname); 637 } 638 } 639 640 int 641 auich_open(void *v, int flags) 642 { 643 return 0; 644 } 645 646 void 647 auich_close(void *v) 648 { 649 struct auich_softc *sc = v; 650 651 auich_halt_output(sc); 652 auich_halt_input(sc); 653 654 sc->sc_pintr = NULL; 655 sc->sc_rintr = NULL; 656 } 657 658 int 659 auich_query_encoding(void *v, struct audio_encoding *aep) 660 { 661 662 switch (aep->index) { 663 case 0: 664 strcpy(aep->name, AudioEulinear); 665 aep->encoding = AUDIO_ENCODING_ULINEAR; 666 aep->precision = 8; 667 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 668 return (0); 669 case 1: 670 strcpy(aep->name, AudioEmulaw); 671 aep->encoding = AUDIO_ENCODING_ULAW; 672 aep->precision = 8; 673 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 674 return (0); 675 case 2: 676 strcpy(aep->name, AudioEalaw); 677 aep->encoding = AUDIO_ENCODING_ALAW; 678 aep->precision = 8; 679 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 680 return (0); 681 case 3: 682 strcpy(aep->name, AudioEslinear); 683 aep->encoding = AUDIO_ENCODING_SLINEAR; 684 aep->precision = 8; 685 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 686 return (0); 687 case 4: 688 strcpy(aep->name, AudioEslinear_le); 689 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 690 aep->precision = 16; 691 aep->flags = 0; 692 return (0); 693 case 5: 694 strcpy(aep->name, AudioEulinear_le); 695 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 696 aep->precision = 16; 697 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 698 return (0); 699 case 6: 700 strcpy(aep->name, AudioEslinear_be); 701 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 702 aep->precision = 16; 703 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 704 return (0); 705 case 7: 706 strcpy(aep->name, AudioEulinear_be); 707 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 708 aep->precision = 16; 709 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 710 return (0); 711 default: 712 return (EINVAL); 713 } 714 } 715 716 int 717 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 718 { 719 int ret; 720 u_long ratetmp; 721 722 ratetmp = srate; 723 if (mode == AUMODE_RECORD) 724 return sc->codec_if->vtbl->set_rate(sc->codec_if, 725 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 726 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 727 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 728 if (ret) 729 return ret; 730 ratetmp = srate; 731 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 732 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 733 if (ret) 734 return ret; 735 ratetmp = srate; 736 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 737 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 738 return ret; 739 } 740 741 int 742 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 743 struct audio_params *rec) 744 { 745 struct auich_softc *sc = v; 746 struct audio_params *p; 747 int mode; 748 u_int32_t control; 749 750 for (mode = AUMODE_RECORD; mode != -1; 751 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 752 if ((setmode & mode) == 0) 753 continue; 754 755 p = mode == AUMODE_PLAY ? play : rec; 756 if (p == NULL) 757 continue; 758 759 if ((p->sample_rate != 8000) && 760 (p->sample_rate != 11025) && 761 (p->sample_rate != 12000) && 762 (p->sample_rate != 16000) && 763 (p->sample_rate != 22050) && 764 (p->sample_rate != 24000) && 765 (p->sample_rate != 32000) && 766 (p->sample_rate != 44100) && 767 (p->sample_rate != 48000)) 768 return (EINVAL); 769 770 p->factor = 1; 771 if (p->precision == 8) 772 p->factor *= 2; 773 774 p->sw_code = NULL; 775 /* setup hardware formats */ 776 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 777 p->hw_precision = 16; 778 779 if (mode == AUMODE_RECORD) { 780 if (p->channels < 1 || p->channels > 2) 781 return EINVAL; 782 } else { 783 switch (p->channels) { 784 case 1: 785 break; 786 case 2: 787 break; 788 case 4: 789 if (!SUPPORTS_4CH(sc->codec_if)) 790 return EINVAL; 791 break; 792 case 6: 793 if (!SUPPORTS_6CH(sc->codec_if)) 794 return EINVAL; 795 break; 796 default: 797 return EINVAL; 798 } 799 } 800 /* If monaural is requested, aurateconv expands a monaural 801 * stream to stereo. */ 802 if (p->channels == 1) 803 p->hw_channels = 2; 804 805 switch (p->encoding) { 806 case AUDIO_ENCODING_SLINEAR_BE: 807 if (p->precision == 16) { 808 p->sw_code = swap_bytes; 809 } else { 810 if (mode == AUMODE_PLAY) 811 p->sw_code = linear8_to_linear16_le; 812 else 813 p->sw_code = linear16_to_linear8_le; 814 } 815 break; 816 817 case AUDIO_ENCODING_SLINEAR_LE: 818 if (p->precision != 16) { 819 if (mode == AUMODE_PLAY) 820 p->sw_code = linear8_to_linear16_le; 821 else 822 p->sw_code = linear16_to_linear8_le; 823 } 824 break; 825 826 case AUDIO_ENCODING_ULINEAR_BE: 827 if (p->precision == 16) { 828 if (mode == AUMODE_PLAY) 829 p->sw_code = 830 swap_bytes_change_sign16_le; 831 else 832 p->sw_code = 833 change_sign16_swap_bytes_le; 834 } else { 835 if (mode == AUMODE_PLAY) 836 p->sw_code = 837 ulinear8_to_slinear16_le; 838 else 839 p->sw_code = 840 slinear16_to_ulinear8_le; 841 } 842 break; 843 844 case AUDIO_ENCODING_ULINEAR_LE: 845 if (p->precision == 16) { 846 p->sw_code = change_sign16_le; 847 } else { 848 if (mode == AUMODE_PLAY) 849 p->sw_code = 850 ulinear8_to_slinear16_le; 851 else 852 p->sw_code = 853 slinear16_to_ulinear8_le; 854 } 855 break; 856 857 case AUDIO_ENCODING_ULAW: 858 if (mode == AUMODE_PLAY) { 859 p->sw_code = mulaw_to_slinear16_le; 860 } else { 861 p->sw_code = slinear16_to_mulaw_le; 862 } 863 break; 864 865 case AUDIO_ENCODING_ALAW: 866 if (mode == AUMODE_PLAY) { 867 p->sw_code = alaw_to_slinear16_le; 868 } else { 869 p->sw_code = slinear16_to_alaw_le; 870 } 871 break; 872 873 default: 874 return (EINVAL); 875 } 876 877 if (IS_FIXED_RATE(sc->codec_if)) { 878 p->hw_sample_rate = AC97_SINGLE_RATE; 879 /* If hw_sample_rate is changed, aurateconv works. */ 880 } else { 881 if (auich_set_rate(sc, mode, p->sample_rate)) 882 return EINVAL; 883 } 884 if (mode == AUMODE_PLAY) { 885 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 886 control &= ~ICH_PCM246_MASK; 887 if (p->channels == 4) { 888 control |= ICH_PCM4; 889 } else if (p->channels == 6) { 890 control |= ICH_PCM6; 891 } 892 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 893 } 894 } 895 896 return (0); 897 } 898 899 int 900 auich_round_blocksize(void *v, int blk) 901 { 902 903 return (blk & ~0x3f); /* keep good alignment */ 904 } 905 906 int 907 auich_halt_output(void *v) 908 { 909 struct auich_softc *sc = v; 910 911 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 912 913 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 914 915 return (0); 916 } 917 918 int 919 auich_halt_input(void *v) 920 { 921 struct auich_softc *sc = v; 922 923 DPRINTF(ICH_DEBUG_DMA, 924 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 925 926 /* XXX halt both unless known otherwise */ 927 928 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 929 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 930 931 return (0); 932 } 933 934 int 935 auich_getdev(void *v, struct audio_device *adp) 936 { 937 struct auich_softc *sc = v; 938 939 *adp = sc->sc_audev; 940 return (0); 941 } 942 943 int 944 auich_set_port(void *v, mixer_ctrl_t *cp) 945 { 946 struct auich_softc *sc = v; 947 948 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 949 } 950 951 int 952 auich_get_port(void *v, mixer_ctrl_t *cp) 953 { 954 struct auich_softc *sc = v; 955 956 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 957 } 958 959 int 960 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 961 { 962 struct auich_softc *sc = v; 963 964 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 965 } 966 967 void * 968 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 969 int flags) 970 { 971 struct auich_softc *sc = v; 972 struct auich_dma *p; 973 int error; 974 975 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 976 return (NULL); 977 978 p = malloc(sizeof(*p), pool, flags|M_ZERO); 979 if (p == NULL) 980 return (NULL); 981 982 error = auich_allocmem(sc, size, 0, p); 983 if (error) { 984 free(p, pool); 985 return (NULL); 986 } 987 988 p->next = sc->sc_dmas; 989 sc->sc_dmas = p; 990 991 return (KERNADDR(p)); 992 } 993 994 void 995 auich_freem(void *v, void *ptr, struct malloc_type *pool) 996 { 997 struct auich_softc *sc = v; 998 struct auich_dma *p, **pp; 999 1000 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1001 if (KERNADDR(p) == ptr) { 1002 auich_freemem(sc, p); 1003 *pp = p->next; 1004 free(p, pool); 1005 return; 1006 } 1007 } 1008 } 1009 1010 size_t 1011 auich_round_buffersize(void *v, int direction, size_t size) 1012 { 1013 1014 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1015 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1016 1017 return size; 1018 } 1019 1020 paddr_t 1021 auich_mappage(void *v, void *mem, off_t off, int prot) 1022 { 1023 struct auich_softc *sc = v; 1024 struct auich_dma *p; 1025 1026 if (off < 0) 1027 return (-1); 1028 1029 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1030 ; 1031 if (!p) 1032 return (-1); 1033 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1034 off, prot, BUS_DMA_WAITOK)); 1035 } 1036 1037 int 1038 auich_get_props(void *v) 1039 { 1040 struct auich_softc *sc = v; 1041 int props; 1042 1043 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1044 /* 1045 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1046 * rate because of aurateconv. Applications can't know what rate the 1047 * device can process in the case of mmap(). 1048 */ 1049 if (!IS_FIXED_RATE(sc->codec_if)) 1050 props |= AUDIO_PROP_MMAP; 1051 return props; 1052 } 1053 1054 int 1055 auich_intr(void *v) 1056 { 1057 struct auich_softc *sc = v; 1058 int ret = 0, sts, gsts, i, qptr; 1059 1060 #ifdef DIAGNOSTIC 1061 int csts; 1062 #endif 1063 1064 #ifdef DIAGNOSTIC 1065 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1066 if (csts & PCI_STATUS_MASTER_ABORT) { 1067 printf("auich_intr: PCI master abort\n"); 1068 } 1069 #endif 1070 1071 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 1072 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 1073 1074 if (gsts & ICH_POINT) { 1075 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 1076 DPRINTF(ICH_DEBUG_DMA, 1077 ("auich_intr: osts=0x%x\n", sts)); 1078 1079 if (sts & ICH_FIFOE) { 1080 printf("%s: fifo underrun # %u\n", 1081 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1082 } 1083 1084 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1085 if (sts & (ICH_LVBCI | ICH_CELV)) { 1086 struct auich_dmalist *q; 1087 1088 qptr = sc->ptr_pcmo; 1089 1090 while (qptr != i) { 1091 q = &sc->dmalist_pcmo[qptr]; 1092 1093 q->base = sc->pcmo_p; 1094 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1095 DPRINTF(ICH_DEBUG_DMA, 1096 ("auich_intr: %p, %p = %x @ 0x%x\n", 1097 &sc->dmalist_pcmo[i], q, 1098 sc->pcmo_blksize / 2, sc->pcmo_p)); 1099 1100 sc->pcmo_p += sc->pcmo_blksize; 1101 if (sc->pcmo_p >= sc->pcmo_end) 1102 sc->pcmo_p = sc->pcmo_start; 1103 1104 if (++qptr == ICH_DMALIST_MAX) 1105 qptr = 0; 1106 } 1107 1108 sc->ptr_pcmo = qptr; 1109 bus_space_write_1(sc->iot, sc->aud_ioh, 1110 ICH_PCMO + ICH_LVI, 1111 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1112 } 1113 1114 if (sts & ICH_BCIS && sc->sc_pintr) 1115 sc->sc_pintr(sc->sc_parg); 1116 1117 /* int ack */ 1118 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1119 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1120 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1121 ret++; 1122 } 1123 1124 if (gsts & ICH_PIINT) { 1125 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1126 DPRINTF(ICH_DEBUG_DMA, 1127 ("auich_intr: ists=0x%x\n", sts)); 1128 1129 if (sts & ICH_FIFOE) { 1130 printf("%s: fifo overrun # %u\n", 1131 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1132 } 1133 1134 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1135 if (sts & (ICH_LVBCI | ICH_CELV)) { 1136 struct auich_dmalist *q; 1137 1138 qptr = sc->ptr_pcmi; 1139 1140 while (qptr != i) { 1141 q = &sc->dmalist_pcmi[qptr]; 1142 1143 q->base = sc->pcmi_p; 1144 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1145 DPRINTF(ICH_DEBUG_DMA, 1146 ("auich_intr: %p, %p = %x @ 0x%x\n", 1147 &sc->dmalist_pcmi[i], q, 1148 sc->pcmi_blksize / 2, sc->pcmi_p)); 1149 1150 sc->pcmi_p += sc->pcmi_blksize; 1151 if (sc->pcmi_p >= sc->pcmi_end) 1152 sc->pcmi_p = sc->pcmi_start; 1153 1154 if (++qptr == ICH_DMALIST_MAX) 1155 qptr = 0; 1156 } 1157 1158 sc->ptr_pcmi = qptr; 1159 bus_space_write_1(sc->iot, sc->aud_ioh, 1160 ICH_PCMI + ICH_LVI, 1161 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1162 } 1163 1164 if (sts & ICH_BCIS && sc->sc_rintr) 1165 sc->sc_rintr(sc->sc_rarg); 1166 1167 /* int ack */ 1168 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1169 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1170 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1171 ret++; 1172 } 1173 1174 if (gsts & ICH_MIINT) { 1175 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1176 DPRINTF(ICH_DEBUG_DMA, 1177 ("auich_intr: ists=0x%x\n", sts)); 1178 if (sts & ICH_FIFOE) 1179 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1180 1181 /* TODO mic input DMA */ 1182 1183 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1184 } 1185 1186 return ret; 1187 } 1188 1189 int 1190 auich_trigger_output(void *v, void *start, void *end, int blksize, 1191 void (*intr)(void *), void *arg, struct audio_params *param) 1192 { 1193 struct auich_softc *sc = v; 1194 struct auich_dmalist *q; 1195 struct auich_dma *p; 1196 size_t size; 1197 #ifdef DIAGNOSTIC 1198 int csts; 1199 #endif 1200 1201 DPRINTF(ICH_DEBUG_DMA, 1202 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1203 start, end, blksize, intr, arg, param)); 1204 1205 sc->sc_pintr = intr; 1206 sc->sc_parg = arg; 1207 #ifdef DIAGNOSTIC 1208 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1209 if (csts & PCI_STATUS_MASTER_ABORT) { 1210 printf("auich_trigger_output: PCI master abort\n"); 1211 } 1212 #endif 1213 1214 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1215 ; 1216 if (!p) { 1217 printf("auich_trigger_output: bad addr %p\n", start); 1218 return (EINVAL); 1219 } 1220 1221 size = (size_t)((caddr_t)end - (caddr_t)start); 1222 1223 /* 1224 * The logic behind this is: 1225 * setup one buffer to play, then LVI dump out the rest 1226 * to the scatter-gather chain. 1227 */ 1228 sc->pcmo_start = DMAADDR(p); 1229 sc->pcmo_p = sc->pcmo_start + blksize; 1230 sc->pcmo_end = sc->pcmo_start + size; 1231 sc->pcmo_blksize = blksize; 1232 1233 sc->ptr_pcmo = 0; 1234 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1235 q->base = sc->pcmo_start; 1236 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1237 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1238 sc->ptr_pcmo = 0; 1239 1240 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1241 sc->sc_cddma + ICH_PCMO_OFF(0)); 1242 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1243 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1244 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1245 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1246 1247 return (0); 1248 } 1249 1250 int 1251 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1252 void *v; 1253 void *start, *end; 1254 int blksize; 1255 void (*intr)(void *); 1256 void *arg; 1257 struct audio_params *param; 1258 { 1259 struct auich_softc *sc = v; 1260 struct auich_dmalist *q; 1261 struct auich_dma *p; 1262 size_t size; 1263 #ifdef DIAGNOSTIC 1264 int csts; 1265 #endif 1266 1267 DPRINTF(ICH_DEBUG_DMA, 1268 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1269 start, end, blksize, intr, arg, param)); 1270 1271 sc->sc_rintr = intr; 1272 sc->sc_rarg = arg; 1273 1274 #ifdef DIAGNOSTIC 1275 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1276 if (csts & PCI_STATUS_MASTER_ABORT) { 1277 printf("auich_trigger_input: PCI master abort\n"); 1278 } 1279 #endif 1280 1281 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1282 ; 1283 if (!p) { 1284 printf("auich_trigger_input: bad addr %p\n", start); 1285 return (EINVAL); 1286 } 1287 1288 size = (size_t)((caddr_t)end - (caddr_t)start); 1289 1290 /* 1291 * The logic behind this is: 1292 * setup one buffer to play, then LVI dump out the rest 1293 * to the scatter-gather chain. 1294 */ 1295 sc->pcmi_start = DMAADDR(p); 1296 sc->pcmi_p = sc->pcmi_start + blksize; 1297 sc->pcmi_end = sc->pcmi_start + size; 1298 sc->pcmi_blksize = blksize; 1299 1300 sc->ptr_pcmi = 0; 1301 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1302 q->base = sc->pcmi_start; 1303 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1304 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1305 sc->ptr_pcmi = 0; 1306 1307 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1308 sc->sc_cddma + ICH_PCMI_OFF(0)); 1309 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1310 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1311 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1312 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1313 1314 return (0); 1315 } 1316 1317 int 1318 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1319 struct auich_dma *p) 1320 { 1321 int error; 1322 1323 p->size = size; 1324 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1325 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1326 &p->nsegs, BUS_DMA_NOWAIT); 1327 if (error) 1328 return (error); 1329 1330 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1331 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1332 if (error) 1333 goto free; 1334 1335 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1336 0, BUS_DMA_NOWAIT, &p->map); 1337 if (error) 1338 goto unmap; 1339 1340 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1341 BUS_DMA_NOWAIT); 1342 if (error) 1343 goto destroy; 1344 return (0); 1345 1346 destroy: 1347 bus_dmamap_destroy(sc->dmat, p->map); 1348 unmap: 1349 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1350 free: 1351 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1352 return (error); 1353 } 1354 1355 int 1356 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1357 { 1358 1359 bus_dmamap_unload(sc->dmat, p->map); 1360 bus_dmamap_destroy(sc->dmat, p->map); 1361 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1362 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1363 return (0); 1364 } 1365 1366 int 1367 auich_alloc_cdata(struct auich_softc *sc) 1368 { 1369 bus_dma_segment_t seg; 1370 int error, rseg; 1371 1372 /* 1373 * Allocate the control data structure, and create and load the 1374 * DMA map for it. 1375 */ 1376 if ((error = bus_dmamem_alloc(sc->dmat, 1377 sizeof(struct auich_cdata), 1378 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1379 printf("%s: unable to allocate control data, error = %d\n", 1380 sc->sc_dev.dv_xname, error); 1381 goto fail_0; 1382 } 1383 1384 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1385 sizeof(struct auich_cdata), 1386 (caddr_t *) &sc->sc_cdata, 1387 sc->sc_dmamap_flags)) != 0) { 1388 printf("%s: unable to map control data, error = %d\n", 1389 sc->sc_dev.dv_xname, error); 1390 goto fail_1; 1391 } 1392 1393 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1394 sizeof(struct auich_cdata), 0, 0, 1395 &sc->sc_cddmamap)) != 0) { 1396 printf("%s: unable to create control data DMA map, " 1397 "error = %d\n", sc->sc_dev.dv_xname, error); 1398 goto fail_2; 1399 } 1400 1401 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1402 sc->sc_cdata, sizeof(struct auich_cdata), 1403 NULL, 0)) != 0) { 1404 printf("%s: unable tp load control data DMA map, " 1405 "error = %d\n", sc->sc_dev.dv_xname, error); 1406 goto fail_3; 1407 } 1408 1409 return (0); 1410 1411 fail_3: 1412 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1413 fail_2: 1414 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1415 sizeof(struct auich_cdata)); 1416 fail_1: 1417 bus_dmamem_free(sc->dmat, &seg, rseg); 1418 fail_0: 1419 return (error); 1420 } 1421 1422 void 1423 auich_powerhook(int why, void *addr) 1424 { 1425 struct auich_softc *sc = (struct auich_softc *)addr; 1426 1427 switch (why) { 1428 case PWR_SUSPEND: 1429 case PWR_STANDBY: 1430 /* Power down */ 1431 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1432 sc->sc_suspend = why; 1433 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1434 break; 1435 1436 case PWR_RESUME: 1437 /* Wake up */ 1438 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1439 if (sc->sc_suspend == PWR_RESUME) { 1440 printf("%s: resume without suspend.\n", 1441 sc->sc_dev.dv_xname); 1442 sc->sc_suspend = why; 1443 return; 1444 } 1445 sc->sc_suspend = why; 1446 auich_reset_codec(sc); 1447 DELAY(1000); 1448 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1449 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1450 break; 1451 1452 case PWR_SOFTSUSPEND: 1453 case PWR_SOFTSTANDBY: 1454 case PWR_SOFTRESUME: 1455 break; 1456 } 1457 } 1458 1459 1460 /* -------------------------------------------------------------------- */ 1461 /* Calibrate card (some boards are overclocked and need scaling) */ 1462 1463 void 1464 auich_calibrate(struct auich_softc *sc) 1465 { 1466 struct timeval t1, t2; 1467 uint8_t ociv, nciv; 1468 uint64_t wait_us; 1469 uint32_t actual_48k_rate, bytes, ac97rate; 1470 void *temp_buffer; 1471 struct auich_dma *p; 1472 u_long rate; 1473 1474 /* 1475 * Grab audio from input for fixed interval and compare how 1476 * much we actually get with what we expect. Interval needs 1477 * to be sufficiently short that no interrupts are 1478 * generated. 1479 */ 1480 1481 /* Force the codec to a known state first. */ 1482 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1483 rate = 48000; 1484 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1485 &rate); 1486 1487 /* Setup a buffer */ 1488 bytes = 64000; 1489 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1490 1491 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1492 ; 1493 if (p == NULL) { 1494 printf("auich_calibrate: bad address %p\n", temp_buffer); 1495 return; 1496 } 1497 sc->dmalist_pcmi[0].base = DMAADDR(p); 1498 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size); 1499 1500 /* 1501 * our data format is stereo, 16 bit so each sample is 4 bytes. 1502 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1503 * we're going to start recording with interrupts disabled and measure 1504 * the time taken for one block to complete. we know the block size, 1505 * we know the time in microseconds, we calculate the sample rate: 1506 * 1507 * actual_rate [bps] = bytes / (time [s] * 4) 1508 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1509 * actual_rate [Hz] = (bytes * 250000) / time [us] 1510 */ 1511 1512 /* prepare */ 1513 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1514 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1515 sc->sc_cddma + ICH_PCMI_OFF(0)); 1516 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1517 (0 - 1) & ICH_LVI_MASK); 1518 1519 /* start */ 1520 microtime(&t1); 1521 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1522 1523 /* wait */ 1524 nciv = ociv; 1525 do { 1526 microtime(&t2); 1527 if (t2.tv_sec - t1.tv_sec > 1) 1528 break; 1529 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1530 ICH_PCMI + ICH_CIV); 1531 } while (nciv == ociv); 1532 microtime(&t2); 1533 1534 /* stop */ 1535 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1536 1537 /* reset */ 1538 DELAY(100); 1539 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1540 1541 /* turn time delta into us */ 1542 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1543 1544 auich_freem(sc, temp_buffer, M_DEVBUF); 1545 1546 if (nciv == ociv) { 1547 printf("%s: ac97 link rate calibration timed out after %" 1548 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1549 return; 1550 } 1551 1552 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1553 1554 if (actual_48k_rate < 50000) 1555 ac97rate = 48000; 1556 else 1557 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1558 1559 printf("%s: measured ac97 link rate at %d Hz", 1560 sc->sc_dev.dv_xname, actual_48k_rate); 1561 if (ac97rate != actual_48k_rate) 1562 printf(", will use %d Hz", ac97rate); 1563 printf("\n"); 1564 1565 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1566 } 1567
Indexes created Thu Oct 23 22:10:10 GMT 2025