auich.c revision 1.57
1 /* $NetBSD: auich.c,v 1.57 2004/01/03 14:11:36 soren Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define ICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.57 2004/01/03 14:11:36 soren Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 131 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 132 133 #include <dev/pci/pcidevs.h> 134 #include <dev/pci/pcivar.h> 135 #include <dev/pci/auichreg.h> 136 137 #include <sys/audioio.h> 138 #include <dev/audio_if.h> 139 #include <dev/mulaw.h> 140 #include <dev/auconv.h> 141 142 #include <machine/bus.h> 143 144 #include <dev/ic/ac97reg.h> 145 #include <dev/ic/ac97var.h> 146 147 struct auich_dma { 148 bus_dmamap_t map; 149 caddr_t addr; 150 bus_dma_segment_t segs[1]; 151 int nsegs; 152 size_t size; 153 struct auich_dma *next; 154 }; 155 156 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 157 #define KERNADDR(p) ((void *)((p)->addr)) 158 159 struct auich_cdata { 160 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 161 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 163 }; 164 165 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 166 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 167 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 168 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 169 170 struct auich_softc { 171 struct device sc_dev; 172 void *sc_ih; 173 174 audio_device_t sc_audev; 175 176 bus_space_tag_t iot; 177 bus_space_handle_t mix_ioh; 178 bus_space_handle_t aud_ioh; 179 bus_dma_tag_t dmat; 180 181 struct ac97_codec_if *codec_if; 182 struct ac97_host_if host_if; 183 184 /* DMA scatter-gather lists. */ 185 bus_dmamap_t sc_cddmamap; 186 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 187 188 struct auich_cdata *sc_cdata; 189 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 190 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 191 #define dmalist_mici sc_cdata->ic_dmalist_mici 192 193 int ptr_pcmo, 194 ptr_pcmi, 195 ptr_mici; 196 197 /* i/o buffer pointers */ 198 u_int32_t pcmo_start, pcmo_p, pcmo_end; 199 int pcmo_blksize, pcmo_fifoe; 200 201 u_int32_t pcmi_start, pcmi_p, pcmi_end; 202 int pcmi_blksize, pcmi_fifoe; 203 204 u_int32_t mici_start, mici_p, mici_end; 205 int mici_blksize, mici_fifoe; 206 207 struct auich_dma *sc_dmas; 208 209 #ifdef DIAGNOSTIC 210 pci_chipset_tag_t sc_pc; 211 pcitag_t sc_pt; 212 #endif 213 /* SiS 7012 hack */ 214 int sc_sample_size; 215 int sc_sts_reg; 216 /* 440MX workaround */ 217 int sc_dmamap_flags; 218 219 void (*sc_pintr)(void *); 220 void *sc_parg; 221 222 void (*sc_rintr)(void *); 223 void *sc_rarg; 224 225 /* Power Management */ 226 void *sc_powerhook; 227 int sc_suspend; 228 u_int16_t ext_status; 229 }; 230 231 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 232 & AC97_EXT_AUDIO_VRA) 233 #define SUPPORTS_4CH(codec) ((codec)->vtbl->get_extcaps(codec) \ 234 & AC97_EXT_AUDIO_SDAC) 235 #define AC97_6CH_DACS (AC97_EXT_AUDIO_SDAC | AC97_EXT_AUDIO_CDAC \ 236 | AC97_EXT_AUDIO_LDAC) 237 #define SUPPORTS_6CH(codec) (((codec)->vtbl->get_extcaps(codec) \ 238 & AC97_6CH_DACS) == AC97_6CH_DACS) 239 240 /* Debug */ 241 #ifdef AUDIO_DEBUG 242 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 243 int auich_debug = 0xfffe; 244 #define ICH_DEBUG_CODECIO 0x0001 245 #define ICH_DEBUG_DMA 0x0002 246 #define ICH_DEBUG_PARAM 0x0004 247 #else 248 #define DPRINTF(x,y) /* nothing */ 249 #endif 250 251 int auich_match(struct device *, struct cfdata *, void *); 252 void auich_attach(struct device *, struct device *, void *); 253 int auich_intr(void *); 254 255 CFATTACH_DECL(auich, sizeof(struct auich_softc), 256 auich_match, auich_attach, NULL, NULL); 257 258 int auich_open(void *, int); 259 void auich_close(void *); 260 int auich_query_encoding(void *, struct audio_encoding *); 261 int auich_set_params(void *, int, int, struct audio_params *, 262 struct audio_params *); 263 int auich_round_blocksize(void *, int); 264 int auich_halt_output(void *); 265 int auich_halt_input(void *); 266 int auich_getdev(void *, struct audio_device *); 267 int auich_set_port(void *, mixer_ctrl_t *); 268 int auich_get_port(void *, mixer_ctrl_t *); 269 int auich_query_devinfo(void *, mixer_devinfo_t *); 270 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 271 void auich_freem(void *, void *, struct malloc_type *); 272 size_t auich_round_buffersize(void *, int, size_t); 273 paddr_t auich_mappage(void *, void *, off_t, int); 274 int auich_get_props(void *); 275 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 276 void *, struct audio_params *); 277 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 278 void *, struct audio_params *); 279 280 int auich_alloc_cdata(struct auich_softc *); 281 282 int auich_allocmem(struct auich_softc *, size_t, size_t, 283 struct auich_dma *); 284 int auich_freemem(struct auich_softc *, struct auich_dma *); 285 286 void auich_powerhook(int, void *); 287 int auich_set_rate(struct auich_softc *, int, u_long); 288 void auich_finish_attach(struct device *); 289 void auich_calibrate(struct auich_softc *); 290 291 292 struct audio_hw_if auich_hw_if = { 293 auich_open, 294 auich_close, 295 NULL, /* drain */ 296 auich_query_encoding, 297 auich_set_params, 298 auich_round_blocksize, 299 NULL, /* commit_setting */ 300 NULL, /* init_output */ 301 NULL, /* init_input */ 302 NULL, /* start_output */ 303 NULL, /* start_input */ 304 auich_halt_output, 305 auich_halt_input, 306 NULL, /* speaker_ctl */ 307 auich_getdev, 308 NULL, /* getfd */ 309 auich_set_port, 310 auich_get_port, 311 auich_query_devinfo, 312 auich_allocm, 313 auich_freem, 314 auich_round_buffersize, 315 auich_mappage, 316 auich_get_props, 317 auich_trigger_output, 318 auich_trigger_input, 319 NULL, /* dev_ioctl */ 320 }; 321 322 int auich_attach_codec(void *, struct ac97_codec_if *); 323 int auich_read_codec(void *, u_int8_t, u_int16_t *); 324 int auich_write_codec(void *, u_int8_t, u_int16_t); 325 void auich_reset_codec(void *); 326 327 static const struct auich_devtype { 328 int vendor; 329 int product; 330 const char *name; 331 const char *shortname; /* must be less than 11 characters */ 332 } auich_devices[] = { 333 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 334 "i82801AA (ICH) AC-97 Audio", "ICH" }, 335 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 336 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 337 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 338 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 339 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 340 "i82440MX AC-97 Audio", "440MX" }, 341 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 342 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 343 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 344 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 345 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 346 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 347 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 348 "SiS 7012 AC-97 Audio", "SiS7012" }, 349 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 350 "nForce MCP AC-97 Audio", "nForce" }, 351 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 352 "nForce2 MCP-T AC-97 Audio", "nForce2" }, 353 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 354 "nForce3 MCP-T AC-97 Audio", "nForce3" }, 355 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 356 "AMD768 AC-97 Audio", "AMD768" }, 357 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 358 "AMD8111 AC-97 Audio", "AMD8111" }, 359 { 0, 0, 360 NULL, NULL }, 361 }; 362 363 static const struct auich_devtype * 364 auich_lookup(struct pci_attach_args *pa) 365 { 366 const struct auich_devtype *d; 367 368 for (d = auich_devices; d->name != NULL; d++) { 369 if (PCI_VENDOR(pa->pa_id) == d->vendor 370 && PCI_PRODUCT(pa->pa_id) == d->product) 371 return (d); 372 } 373 374 return (NULL); 375 } 376 377 int 378 auich_match(struct device *parent, struct cfdata *match, void *aux) 379 { 380 struct pci_attach_args *pa = aux; 381 382 if (auich_lookup(pa) != NULL) 383 return (1); 384 385 return (0); 386 } 387 388 void 389 auich_attach(struct device *parent, struct device *self, void *aux) 390 { 391 struct auich_softc *sc = (struct auich_softc *)self; 392 struct pci_attach_args *pa = aux; 393 pci_intr_handle_t ih; 394 bus_size_t mix_size, aud_size; 395 pcireg_t v; 396 const char *intrstr; 397 const struct auich_devtype *d; 398 399 aprint_naive(": Audio controller\n"); 400 401 d = auich_lookup(pa); 402 if (d == NULL) 403 panic("auich_attach: impossible"); 404 405 #ifdef DIAGNOSTIC 406 sc->sc_pc = pa->pa_pc; 407 sc->sc_pt = pa->pa_tag; 408 #endif 409 410 aprint_normal(": %s\n", d->name); 411 412 if ((d->vendor == PCI_VENDOR_INTEL 413 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) 414 || (d->vendor == PCI_VENDOR_INTEL 415 && d->product == PCI_PRODUCT_INTEL_82801EB_AC)) { 416 /* 417 * Use native mode for ICH4/ICH5 418 */ 419 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 420 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 421 aprint_error("%s: can't map native codec i/o space\n", 422 sc->sc_dev.dv_xname); 423 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 424 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 425 v | ICH_CFG_IOSE); 426 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 427 0, &sc->iot, &sc->mix_ioh, NULL, 428 &mix_size)) { 429 aprint_error("%s: can't map compatible codec " 430 "i/o space\n", 431 sc->sc_dev.dv_xname); 432 return; 433 } 434 } 435 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 436 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 437 aprint_error("%s: can't map native device i/o space\n", 438 sc->sc_dev.dv_xname); 439 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 440 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 441 v | ICH_CFG_IOSE); 442 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 443 0, &sc->iot, &sc->aud_ioh, NULL, 444 &aud_size)) { 445 aprint_error("%s: can't map compatible device " 446 "i/o space\n", 447 sc->sc_dev.dv_xname); 448 return; 449 } 450 } 451 } else { 452 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 453 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 454 aprint_error("%s: can't map codec i/o space\n", 455 sc->sc_dev.dv_xname); 456 return; 457 } 458 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 459 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 460 aprint_error("%s: can't map device i/o space\n", 461 sc->sc_dev.dv_xname); 462 return; 463 } 464 } 465 sc->dmat = pa->pa_dmat; 466 467 /* enable bus mastering */ 468 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 469 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 470 v | PCI_COMMAND_MASTER_ENABLE); 471 472 /* Map and establish the interrupt. */ 473 if (pci_intr_map(pa, &ih)) { 474 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 475 return; 476 } 477 intrstr = pci_intr_string(pa->pa_pc, ih); 478 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 479 auich_intr, sc); 480 if (sc->sc_ih == NULL) { 481 aprint_error("%s: can't establish interrupt", 482 sc->sc_dev.dv_xname); 483 if (intrstr != NULL) 484 aprint_normal(" at %s", intrstr); 485 aprint_normal("\n"); 486 return; 487 } 488 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 489 490 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 491 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 492 "0x%02x", PCI_REVISION(pa->pa_class)); 493 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 494 495 /* SiS 7012 needs special handling */ 496 if (d->vendor == PCI_VENDOR_SIS 497 && d->product == PCI_PRODUCT_SIS_7012_AC) { 498 sc->sc_sts_reg = ICH_PICB; 499 sc->sc_sample_size = 1; 500 } else { 501 sc->sc_sts_reg = ICH_STS; 502 sc->sc_sample_size = 2; 503 } 504 505 /* Workaround for a 440MX B-stepping erratum */ 506 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 507 if (d->vendor == PCI_VENDOR_INTEL 508 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 509 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 510 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 511 } 512 513 /* Set up DMA lists. */ 514 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 515 auich_alloc_cdata(sc); 516 517 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 518 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 519 520 sc->host_if.arg = sc; 521 sc->host_if.attach = auich_attach_codec; 522 sc->host_if.read = auich_read_codec; 523 sc->host_if.write = auich_write_codec; 524 sc->host_if.reset = auich_reset_codec; 525 526 if (ac97_attach(&sc->host_if) != 0) 527 return; 528 529 /* Watch for power change */ 530 sc->sc_suspend = PWR_RESUME; 531 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 532 533 config_interrupts(self, auich_finish_attach); 534 } 535 536 void 537 auich_finish_attach(struct device *self) 538 { 539 struct auich_softc *sc = (void *)self; 540 541 if (!IS_FIXED_RATE(sc->codec_if)) 542 auich_calibrate(sc); 543 544 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 545 } 546 547 #define ICH_CODECIO_INTERVAL 10 548 int 549 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 550 { 551 struct auich_softc *sc = v; 552 int i; 553 uint32_t status; 554 555 /* wait for an access semaphore */ 556 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 557 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 558 DELAY(ICH_CODECIO_INTERVAL)); 559 560 if (i > 0) { 561 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 562 DPRINTF(ICH_DEBUG_CODECIO, 563 ("auich_read_codec(%x, %x)\n", reg, *val)); 564 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 565 if (status & ICH_RCS) { 566 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 567 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 568 *val = 0xffff; 569 } 570 return 0; 571 } else { 572 DPRINTF(ICH_DEBUG_CODECIO, 573 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 574 return -1; 575 } 576 } 577 578 int 579 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 580 { 581 struct auich_softc *sc = v; 582 int i; 583 584 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 585 /* wait for an access semaphore */ 586 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 587 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 588 DELAY(ICH_CODECIO_INTERVAL)); 589 590 if (i > 0) { 591 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 592 return 0; 593 } else { 594 DPRINTF(ICH_DEBUG_CODECIO, 595 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 596 return -1; 597 } 598 } 599 600 int 601 auich_attach_codec(void *v, struct ac97_codec_if *cif) 602 { 603 struct auich_softc *sc = v; 604 605 sc->codec_if = cif; 606 return 0; 607 } 608 609 void 610 auich_reset_codec(void *v) 611 { 612 struct auich_softc *sc = v; 613 int i; 614 uint32_t control, status; 615 616 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 617 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 618 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 619 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 620 621 for (i = 500000; i >= 0; i--) { 622 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 623 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 624 break; 625 DELAY(1); 626 } 627 if (i <= 0) { 628 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 629 /* XXX: should not attach the audio device */ 630 } else { 631 #ifdef DEBUG 632 if (status & ICH_SCR) 633 printf("%s: The 2nd codec is ready.\n", 634 sc->sc_dev.dv_xname); 635 if (status & ICH_S2CR) 636 printf("%s: The 3rd codec is ready.\n", 637 sc->sc_dev.dv_xname); 638 #endif 639 } 640 } 641 642 int 643 auich_open(void *v, int flags) 644 { 645 return 0; 646 } 647 648 void 649 auich_close(void *v) 650 { 651 struct auich_softc *sc = v; 652 653 auich_halt_output(sc); 654 auich_halt_input(sc); 655 656 sc->sc_pintr = NULL; 657 sc->sc_rintr = NULL; 658 } 659 660 int 661 auich_query_encoding(void *v, struct audio_encoding *aep) 662 { 663 664 switch (aep->index) { 665 case 0: 666 strcpy(aep->name, AudioEulinear); 667 aep->encoding = AUDIO_ENCODING_ULINEAR; 668 aep->precision = 8; 669 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 670 return (0); 671 case 1: 672 strcpy(aep->name, AudioEmulaw); 673 aep->encoding = AUDIO_ENCODING_ULAW; 674 aep->precision = 8; 675 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 676 return (0); 677 case 2: 678 strcpy(aep->name, AudioEalaw); 679 aep->encoding = AUDIO_ENCODING_ALAW; 680 aep->precision = 8; 681 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 682 return (0); 683 case 3: 684 strcpy(aep->name, AudioEslinear); 685 aep->encoding = AUDIO_ENCODING_SLINEAR; 686 aep->precision = 8; 687 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 688 return (0); 689 case 4: 690 strcpy(aep->name, AudioEslinear_le); 691 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 692 aep->precision = 16; 693 aep->flags = 0; 694 return (0); 695 case 5: 696 strcpy(aep->name, AudioEulinear_le); 697 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 698 aep->precision = 16; 699 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 700 return (0); 701 case 6: 702 strcpy(aep->name, AudioEslinear_be); 703 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 704 aep->precision = 16; 705 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 706 return (0); 707 case 7: 708 strcpy(aep->name, AudioEulinear_be); 709 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 710 aep->precision = 16; 711 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 712 return (0); 713 default: 714 return (EINVAL); 715 } 716 } 717 718 int 719 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 720 { 721 int ret; 722 u_long ratetmp; 723 724 ratetmp = srate; 725 if (mode == AUMODE_RECORD) 726 return sc->codec_if->vtbl->set_rate(sc->codec_if, 727 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 728 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 729 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 730 if (ret) 731 return ret; 732 ratetmp = srate; 733 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 734 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 735 if (ret) 736 return ret; 737 ratetmp = srate; 738 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 739 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 740 return ret; 741 } 742 743 int 744 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 745 struct audio_params *rec) 746 { 747 struct auich_softc *sc = v; 748 struct audio_params *p; 749 int mode; 750 u_int32_t control; 751 752 for (mode = AUMODE_RECORD; mode != -1; 753 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 754 if ((setmode & mode) == 0) 755 continue; 756 757 p = mode == AUMODE_PLAY ? play : rec; 758 if (p == NULL) 759 continue; 760 761 if ((p->sample_rate != 8000) && 762 (p->sample_rate != 11025) && 763 (p->sample_rate != 12000) && 764 (p->sample_rate != 16000) && 765 (p->sample_rate != 22050) && 766 (p->sample_rate != 24000) && 767 (p->sample_rate != 32000) && 768 (p->sample_rate != 44100) && 769 (p->sample_rate != 48000)) 770 return (EINVAL); 771 772 p->factor = 1; 773 if (p->precision == 8) 774 p->factor *= 2; 775 776 p->sw_code = NULL; 777 /* setup hardware formats */ 778 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 779 p->hw_precision = 16; 780 781 if (mode == AUMODE_RECORD) { 782 if (p->channels < 1 || p->channels > 2) 783 return EINVAL; 784 } else { 785 switch (p->channels) { 786 case 1: 787 break; 788 case 2: 789 break; 790 case 4: 791 if (!SUPPORTS_4CH(sc->codec_if)) 792 return EINVAL; 793 break; 794 case 6: 795 if (!SUPPORTS_6CH(sc->codec_if)) 796 return EINVAL; 797 break; 798 default: 799 return EINVAL; 800 } 801 } 802 /* If monaural is requested, aurateconv expands a monaural 803 * stream to stereo. */ 804 if (p->channels == 1) 805 p->hw_channels = 2; 806 807 switch (p->encoding) { 808 case AUDIO_ENCODING_SLINEAR_BE: 809 if (p->precision == 16) { 810 p->sw_code = swap_bytes; 811 } else { 812 if (mode == AUMODE_PLAY) 813 p->sw_code = linear8_to_linear16_le; 814 else 815 p->sw_code = linear16_to_linear8_le; 816 } 817 break; 818 819 case AUDIO_ENCODING_SLINEAR_LE: 820 if (p->precision != 16) { 821 if (mode == AUMODE_PLAY) 822 p->sw_code = linear8_to_linear16_le; 823 else 824 p->sw_code = linear16_to_linear8_le; 825 } 826 break; 827 828 case AUDIO_ENCODING_ULINEAR_BE: 829 if (p->precision == 16) { 830 if (mode == AUMODE_PLAY) 831 p->sw_code = 832 swap_bytes_change_sign16_le; 833 else 834 p->sw_code = 835 change_sign16_swap_bytes_le; 836 } else { 837 if (mode == AUMODE_PLAY) 838 p->sw_code = 839 ulinear8_to_slinear16_le; 840 else 841 p->sw_code = 842 slinear16_to_ulinear8_le; 843 } 844 break; 845 846 case AUDIO_ENCODING_ULINEAR_LE: 847 if (p->precision == 16) { 848 p->sw_code = change_sign16_le; 849 } else { 850 if (mode == AUMODE_PLAY) 851 p->sw_code = 852 ulinear8_to_slinear16_le; 853 else 854 p->sw_code = 855 slinear16_to_ulinear8_le; 856 } 857 break; 858 859 case AUDIO_ENCODING_ULAW: 860 if (mode == AUMODE_PLAY) { 861 p->sw_code = mulaw_to_slinear16_le; 862 } else { 863 p->sw_code = slinear16_to_mulaw_le; 864 } 865 break; 866 867 case AUDIO_ENCODING_ALAW: 868 if (mode == AUMODE_PLAY) { 869 p->sw_code = alaw_to_slinear16_le; 870 } else { 871 p->sw_code = slinear16_to_alaw_le; 872 } 873 break; 874 875 default: 876 return (EINVAL); 877 } 878 879 if (IS_FIXED_RATE(sc->codec_if)) { 880 p->hw_sample_rate = AC97_SINGLE_RATE; 881 /* If hw_sample_rate is changed, aurateconv works. */ 882 } else { 883 if (auich_set_rate(sc, mode, p->sample_rate)) 884 return EINVAL; 885 } 886 if (mode == AUMODE_PLAY) { 887 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 888 control &= ~ICH_PCM246_MASK; 889 if (p->channels == 4) { 890 control |= ICH_PCM4; 891 } else if (p->channels == 6) { 892 control |= ICH_PCM6; 893 } 894 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 895 } 896 } 897 898 return (0); 899 } 900 901 int 902 auich_round_blocksize(void *v, int blk) 903 { 904 905 return (blk & ~0x3f); /* keep good alignment */ 906 } 907 908 int 909 auich_halt_output(void *v) 910 { 911 struct auich_softc *sc = v; 912 913 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 914 915 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 916 917 return (0); 918 } 919 920 int 921 auich_halt_input(void *v) 922 { 923 struct auich_softc *sc = v; 924 925 DPRINTF(ICH_DEBUG_DMA, 926 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 927 928 /* XXX halt both unless known otherwise */ 929 930 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 931 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 932 933 return (0); 934 } 935 936 int 937 auich_getdev(void *v, struct audio_device *adp) 938 { 939 struct auich_softc *sc = v; 940 941 *adp = sc->sc_audev; 942 return (0); 943 } 944 945 int 946 auich_set_port(void *v, mixer_ctrl_t *cp) 947 { 948 struct auich_softc *sc = v; 949 950 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 951 } 952 953 int 954 auich_get_port(void *v, mixer_ctrl_t *cp) 955 { 956 struct auich_softc *sc = v; 957 958 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 959 } 960 961 int 962 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 963 { 964 struct auich_softc *sc = v; 965 966 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 967 } 968 969 void * 970 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 971 int flags) 972 { 973 struct auich_softc *sc = v; 974 struct auich_dma *p; 975 int error; 976 977 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 978 return (NULL); 979 980 p = malloc(sizeof(*p), pool, flags|M_ZERO); 981 if (p == NULL) 982 return (NULL); 983 984 error = auich_allocmem(sc, size, 0, p); 985 if (error) { 986 free(p, pool); 987 return (NULL); 988 } 989 990 p->next = sc->sc_dmas; 991 sc->sc_dmas = p; 992 993 return (KERNADDR(p)); 994 } 995 996 void 997 auich_freem(void *v, void *ptr, struct malloc_type *pool) 998 { 999 struct auich_softc *sc = v; 1000 struct auich_dma *p, **pp; 1001 1002 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1003 if (KERNADDR(p) == ptr) { 1004 auich_freemem(sc, p); 1005 *pp = p->next; 1006 free(p, pool); 1007 return; 1008 } 1009 } 1010 } 1011 1012 size_t 1013 auich_round_buffersize(void *v, int direction, size_t size) 1014 { 1015 1016 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1017 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1018 1019 return size; 1020 } 1021 1022 paddr_t 1023 auich_mappage(void *v, void *mem, off_t off, int prot) 1024 { 1025 struct auich_softc *sc = v; 1026 struct auich_dma *p; 1027 1028 if (off < 0) 1029 return (-1); 1030 1031 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1032 ; 1033 if (!p) 1034 return (-1); 1035 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1036 off, prot, BUS_DMA_WAITOK)); 1037 } 1038 1039 int 1040 auich_get_props(void *v) 1041 { 1042 struct auich_softc *sc = v; 1043 int props; 1044 1045 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1046 /* 1047 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1048 * rate because of aurateconv. Applications can't know what rate the 1049 * device can process in the case of mmap(). 1050 */ 1051 if (!IS_FIXED_RATE(sc->codec_if)) 1052 props |= AUDIO_PROP_MMAP; 1053 return props; 1054 } 1055 1056 int 1057 auich_intr(void *v) 1058 { 1059 struct auich_softc *sc = v; 1060 int ret = 0, sts, gsts, i, qptr; 1061 1062 #ifdef DIAGNOSTIC 1063 int csts; 1064 #endif 1065 1066 #ifdef DIAGNOSTIC 1067 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1068 if (csts & PCI_STATUS_MASTER_ABORT) { 1069 printf("auich_intr: PCI master abort\n"); 1070 } 1071 #endif 1072 1073 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 1074 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 1075 1076 if (gsts & ICH_POINT) { 1077 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+sc->sc_sts_reg); 1078 DPRINTF(ICH_DEBUG_DMA, 1079 ("auich_intr: osts=0x%x\n", sts)); 1080 1081 if (sts & ICH_FIFOE) { 1082 printf("%s: fifo underrun # %u\n", 1083 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1084 } 1085 1086 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1087 if (sts & (ICH_LVBCI | ICH_CELV)) { 1088 struct auich_dmalist *q; 1089 1090 qptr = sc->ptr_pcmo; 1091 1092 while (qptr != i) { 1093 q = &sc->dmalist_pcmo[qptr]; 1094 1095 q->base = sc->pcmo_p; 1096 q->len = (sc->pcmo_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1097 DPRINTF(ICH_DEBUG_DMA, 1098 ("auich_intr: %p, %p = %x @ 0x%x\n", 1099 &sc->dmalist_pcmo[i], q, 1100 sc->pcmo_blksize / 2, sc->pcmo_p)); 1101 1102 sc->pcmo_p += sc->pcmo_blksize; 1103 if (sc->pcmo_p >= sc->pcmo_end) 1104 sc->pcmo_p = sc->pcmo_start; 1105 1106 if (++qptr == ICH_DMALIST_MAX) 1107 qptr = 0; 1108 } 1109 1110 sc->ptr_pcmo = qptr; 1111 bus_space_write_1(sc->iot, sc->aud_ioh, 1112 ICH_PCMO + ICH_LVI, 1113 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1114 } 1115 1116 if (sts & ICH_BCIS && sc->sc_pintr) 1117 sc->sc_pintr(sc->sc_parg); 1118 1119 /* int ack */ 1120 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + sc->sc_sts_reg, 1121 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1122 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1123 ret++; 1124 } 1125 1126 if (gsts & ICH_PIINT) { 1127 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+sc->sc_sts_reg); 1128 DPRINTF(ICH_DEBUG_DMA, 1129 ("auich_intr: ists=0x%x\n", sts)); 1130 1131 if (sts & ICH_FIFOE) { 1132 printf("%s: fifo overrun # %u\n", 1133 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1134 } 1135 1136 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1137 if (sts & (ICH_LVBCI | ICH_CELV)) { 1138 struct auich_dmalist *q; 1139 1140 qptr = sc->ptr_pcmi; 1141 1142 while (qptr != i) { 1143 q = &sc->dmalist_pcmi[qptr]; 1144 1145 q->base = sc->pcmi_p; 1146 q->len = (sc->pcmi_blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1147 DPRINTF(ICH_DEBUG_DMA, 1148 ("auich_intr: %p, %p = %x @ 0x%x\n", 1149 &sc->dmalist_pcmi[i], q, 1150 sc->pcmi_blksize / 2, sc->pcmi_p)); 1151 1152 sc->pcmi_p += sc->pcmi_blksize; 1153 if (sc->pcmi_p >= sc->pcmi_end) 1154 sc->pcmi_p = sc->pcmi_start; 1155 1156 if (++qptr == ICH_DMALIST_MAX) 1157 qptr = 0; 1158 } 1159 1160 sc->ptr_pcmi = qptr; 1161 bus_space_write_1(sc->iot, sc->aud_ioh, 1162 ICH_PCMI + ICH_LVI, 1163 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1164 } 1165 1166 if (sts & ICH_BCIS && sc->sc_rintr) 1167 sc->sc_rintr(sc->sc_rarg); 1168 1169 /* int ack */ 1170 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + sc->sc_sts_reg, 1171 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 1172 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1173 ret++; 1174 } 1175 1176 if (gsts & ICH_MIINT) { 1177 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+sc->sc_sts_reg); 1178 DPRINTF(ICH_DEBUG_DMA, 1179 ("auich_intr: ists=0x%x\n", sts)); 1180 if (sts & ICH_FIFOE) 1181 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1182 1183 /* TODO mic input DMA */ 1184 1185 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1186 } 1187 1188 return ret; 1189 } 1190 1191 int 1192 auich_trigger_output(void *v, void *start, void *end, int blksize, 1193 void (*intr)(void *), void *arg, struct audio_params *param) 1194 { 1195 struct auich_softc *sc = v; 1196 struct auich_dmalist *q; 1197 struct auich_dma *p; 1198 size_t size; 1199 #ifdef DIAGNOSTIC 1200 int csts; 1201 #endif 1202 1203 DPRINTF(ICH_DEBUG_DMA, 1204 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1205 start, end, blksize, intr, arg, param)); 1206 1207 sc->sc_pintr = intr; 1208 sc->sc_parg = arg; 1209 #ifdef DIAGNOSTIC 1210 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1211 if (csts & PCI_STATUS_MASTER_ABORT) { 1212 printf("auich_trigger_output: PCI master abort\n"); 1213 } 1214 #endif 1215 1216 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1217 ; 1218 if (!p) { 1219 printf("auich_trigger_output: bad addr %p\n", start); 1220 return (EINVAL); 1221 } 1222 1223 size = (size_t)((caddr_t)end - (caddr_t)start); 1224 1225 /* 1226 * The logic behind this is: 1227 * setup one buffer to play, then LVI dump out the rest 1228 * to the scatter-gather chain. 1229 */ 1230 sc->pcmo_start = DMAADDR(p); 1231 sc->pcmo_p = sc->pcmo_start + blksize; 1232 sc->pcmo_end = sc->pcmo_start + size; 1233 sc->pcmo_blksize = blksize; 1234 1235 sc->ptr_pcmo = 0; 1236 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1237 q->base = sc->pcmo_start; 1238 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1239 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1240 sc->ptr_pcmo = 0; 1241 1242 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1243 sc->sc_cddma + ICH_PCMO_OFF(0)); 1244 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1245 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1246 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1247 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1248 1249 return (0); 1250 } 1251 1252 int 1253 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1254 void *v; 1255 void *start, *end; 1256 int blksize; 1257 void (*intr)(void *); 1258 void *arg; 1259 struct audio_params *param; 1260 { 1261 struct auich_softc *sc = v; 1262 struct auich_dmalist *q; 1263 struct auich_dma *p; 1264 size_t size; 1265 #ifdef DIAGNOSTIC 1266 int csts; 1267 #endif 1268 1269 DPRINTF(ICH_DEBUG_DMA, 1270 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1271 start, end, blksize, intr, arg, param)); 1272 1273 sc->sc_rintr = intr; 1274 sc->sc_rarg = arg; 1275 1276 #ifdef DIAGNOSTIC 1277 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1278 if (csts & PCI_STATUS_MASTER_ABORT) { 1279 printf("auich_trigger_input: PCI master abort\n"); 1280 } 1281 #endif 1282 1283 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1284 ; 1285 if (!p) { 1286 printf("auich_trigger_input: bad addr %p\n", start); 1287 return (EINVAL); 1288 } 1289 1290 size = (size_t)((caddr_t)end - (caddr_t)start); 1291 1292 /* 1293 * The logic behind this is: 1294 * setup one buffer to play, then LVI dump out the rest 1295 * to the scatter-gather chain. 1296 */ 1297 sc->pcmi_start = DMAADDR(p); 1298 sc->pcmi_p = sc->pcmi_start + blksize; 1299 sc->pcmi_end = sc->pcmi_start + size; 1300 sc->pcmi_blksize = blksize; 1301 1302 sc->ptr_pcmi = 0; 1303 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1304 q->base = sc->pcmi_start; 1305 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1306 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1307 sc->ptr_pcmi = 0; 1308 1309 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1310 sc->sc_cddma + ICH_PCMI_OFF(0)); 1311 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1312 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1313 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1314 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1315 1316 return (0); 1317 } 1318 1319 int 1320 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1321 struct auich_dma *p) 1322 { 1323 int error; 1324 1325 p->size = size; 1326 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1327 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1328 &p->nsegs, BUS_DMA_NOWAIT); 1329 if (error) 1330 return (error); 1331 1332 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1333 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1334 if (error) 1335 goto free; 1336 1337 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1338 0, BUS_DMA_NOWAIT, &p->map); 1339 if (error) 1340 goto unmap; 1341 1342 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1343 BUS_DMA_NOWAIT); 1344 if (error) 1345 goto destroy; 1346 return (0); 1347 1348 destroy: 1349 bus_dmamap_destroy(sc->dmat, p->map); 1350 unmap: 1351 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1352 free: 1353 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1354 return (error); 1355 } 1356 1357 int 1358 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1359 { 1360 1361 bus_dmamap_unload(sc->dmat, p->map); 1362 bus_dmamap_destroy(sc->dmat, p->map); 1363 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1364 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1365 return (0); 1366 } 1367 1368 int 1369 auich_alloc_cdata(struct auich_softc *sc) 1370 { 1371 bus_dma_segment_t seg; 1372 int error, rseg; 1373 1374 /* 1375 * Allocate the control data structure, and create and load the 1376 * DMA map for it. 1377 */ 1378 if ((error = bus_dmamem_alloc(sc->dmat, 1379 sizeof(struct auich_cdata), 1380 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1381 printf("%s: unable to allocate control data, error = %d\n", 1382 sc->sc_dev.dv_xname, error); 1383 goto fail_0; 1384 } 1385 1386 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1387 sizeof(struct auich_cdata), 1388 (caddr_t *) &sc->sc_cdata, 1389 sc->sc_dmamap_flags)) != 0) { 1390 printf("%s: unable to map control data, error = %d\n", 1391 sc->sc_dev.dv_xname, error); 1392 goto fail_1; 1393 } 1394 1395 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1396 sizeof(struct auich_cdata), 0, 0, 1397 &sc->sc_cddmamap)) != 0) { 1398 printf("%s: unable to create control data DMA map, " 1399 "error = %d\n", sc->sc_dev.dv_xname, error); 1400 goto fail_2; 1401 } 1402 1403 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1404 sc->sc_cdata, sizeof(struct auich_cdata), 1405 NULL, 0)) != 0) { 1406 printf("%s: unable tp load control data DMA map, " 1407 "error = %d\n", sc->sc_dev.dv_xname, error); 1408 goto fail_3; 1409 } 1410 1411 return (0); 1412 1413 fail_3: 1414 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1415 fail_2: 1416 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1417 sizeof(struct auich_cdata)); 1418 fail_1: 1419 bus_dmamem_free(sc->dmat, &seg, rseg); 1420 fail_0: 1421 return (error); 1422 } 1423 1424 void 1425 auich_powerhook(int why, void *addr) 1426 { 1427 struct auich_softc *sc = (struct auich_softc *)addr; 1428 1429 switch (why) { 1430 case PWR_SUSPEND: 1431 case PWR_STANDBY: 1432 /* Power down */ 1433 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1434 sc->sc_suspend = why; 1435 auich_read_codec(sc, AC97_REG_EXT_AUDIO_CTRL, &sc->ext_status); 1436 break; 1437 1438 case PWR_RESUME: 1439 /* Wake up */ 1440 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1441 if (sc->sc_suspend == PWR_RESUME) { 1442 printf("%s: resume without suspend.\n", 1443 sc->sc_dev.dv_xname); 1444 sc->sc_suspend = why; 1445 return; 1446 } 1447 sc->sc_suspend = why; 1448 auich_reset_codec(sc); 1449 DELAY(1000); 1450 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1451 auich_write_codec(sc, AC97_REG_EXT_AUDIO_CTRL, sc->ext_status); 1452 break; 1453 1454 case PWR_SOFTSUSPEND: 1455 case PWR_SOFTSTANDBY: 1456 case PWR_SOFTRESUME: 1457 break; 1458 } 1459 } 1460 1461 1462 /* -------------------------------------------------------------------- */ 1463 /* Calibrate card (some boards are overclocked and need scaling) */ 1464 1465 void 1466 auich_calibrate(struct auich_softc *sc) 1467 { 1468 struct timeval t1, t2; 1469 uint8_t ociv, nciv; 1470 uint64_t wait_us; 1471 uint32_t actual_48k_rate, bytes, ac97rate; 1472 void *temp_buffer; 1473 struct auich_dma *p; 1474 u_long rate; 1475 1476 /* 1477 * Grab audio from input for fixed interval and compare how 1478 * much we actually get with what we expect. Interval needs 1479 * to be sufficiently short that no interrupts are 1480 * generated. 1481 */ 1482 1483 /* Force the codec to a known state first. */ 1484 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1485 rate = 48000; 1486 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1487 &rate); 1488 1489 /* Setup a buffer */ 1490 bytes = 64000; 1491 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1492 1493 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1494 ; 1495 if (p == NULL) { 1496 printf("auich_calibrate: bad address %p\n", temp_buffer); 1497 return; 1498 } 1499 sc->dmalist_pcmi[0].base = DMAADDR(p); 1500 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size); 1501 1502 /* 1503 * our data format is stereo, 16 bit so each sample is 4 bytes. 1504 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1505 * we're going to start recording with interrupts disabled and measure 1506 * the time taken for one block to complete. we know the block size, 1507 * we know the time in microseconds, we calculate the sample rate: 1508 * 1509 * actual_rate [bps] = bytes / (time [s] * 4) 1510 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1511 * actual_rate [Hz] = (bytes * 250000) / time [us] 1512 */ 1513 1514 /* prepare */ 1515 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1516 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1517 sc->sc_cddma + ICH_PCMI_OFF(0)); 1518 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1519 (0 - 1) & ICH_LVI_MASK); 1520 1521 /* start */ 1522 microtime(&t1); 1523 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1524 1525 /* wait */ 1526 nciv = ociv; 1527 do { 1528 microtime(&t2); 1529 if (t2.tv_sec - t1.tv_sec > 1) 1530 break; 1531 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1532 ICH_PCMI + ICH_CIV); 1533 } while (nciv == ociv); 1534 microtime(&t2); 1535 1536 /* stop */ 1537 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1538 1539 /* reset */ 1540 DELAY(100); 1541 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1542 1543 /* turn time delta into us */ 1544 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1545 1546 auich_freem(sc, temp_buffer, M_DEVBUF); 1547 1548 if (nciv == ociv) { 1549 printf("%s: ac97 link rate calibration timed out after %" 1550 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1551 return; 1552 } 1553 1554 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1555 1556 if (actual_48k_rate < 50000) 1557 ac97rate = 48000; 1558 else 1559 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1560 1561 printf("%s: measured ac97 link rate at %d Hz", 1562 sc->sc_dev.dv_xname, actual_48k_rate); 1563 if (ac97rate != actual_48k_rate) 1564 printf(", will use %d Hz", ac97rate); 1565 printf("\n"); 1566 1567 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1568 } 1569
Indexes created Wed Oct 22 13:09:56 GMT 2025