auich.c revision 1.63
1 /* $NetBSD: auich.c,v 1.63 2004/10/17 09:10:28 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.63 2004/10/17 09:10:28 kent Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 131 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 132 133 #include <dev/pci/pcidevs.h> 134 #include <dev/pci/pcivar.h> 135 #include <dev/pci/auichreg.h> 136 137 #include <sys/audioio.h> 138 #include <dev/audio_if.h> 139 #include <dev/mulaw.h> 140 #include <dev/auconv.h> 141 142 #include <machine/bus.h> 143 144 #include <dev/ic/ac97reg.h> 145 #include <dev/ic/ac97var.h> 146 147 struct auich_dma { 148 bus_dmamap_t map; 149 caddr_t addr; 150 bus_dma_segment_t segs[1]; 151 int nsegs; 152 size_t size; 153 struct auich_dma *next; 154 }; 155 156 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 157 #define KERNADDR(p) ((void *)((p)->addr)) 158 159 struct auich_cdata { 160 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 161 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 163 }; 164 165 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 166 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 167 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 168 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 169 170 struct auich_softc { 171 struct device sc_dev; 172 void *sc_ih; 173 174 audio_device_t sc_audev; 175 176 bus_space_tag_t iot; 177 bus_space_handle_t mix_ioh; 178 bus_space_handle_t aud_ioh; 179 bus_dma_tag_t dmat; 180 181 struct ac97_codec_if *codec_if; 182 struct ac97_host_if host_if; 183 184 /* DMA scatter-gather lists. */ 185 bus_dmamap_t sc_cddmamap; 186 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 187 188 struct auich_cdata *sc_cdata; 189 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 190 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 191 #define dmalist_mici sc_cdata->ic_dmalist_mici 192 193 int ptr_pcmo, 194 ptr_pcmi, 195 ptr_mici; 196 197 /* i/o buffer pointers */ 198 u_int32_t pcmo_start, pcmo_p, pcmo_end; 199 int pcmo_blksize, pcmo_fifoe; 200 201 u_int32_t pcmi_start, pcmi_p, pcmi_end; 202 int pcmi_blksize, pcmi_fifoe; 203 204 u_int32_t mici_start, mici_p, mici_end; 205 int mici_blksize, mici_fifoe; 206 207 struct auich_dma *sc_dmas; 208 209 #ifdef DIAGNOSTIC 210 pci_chipset_tag_t sc_pc; 211 pcitag_t sc_pt; 212 #endif 213 /* SiS 7012 hack */ 214 int sc_sample_size; 215 int sc_sts_reg; 216 /* 440MX workaround */ 217 int sc_dmamap_flags; 218 219 void (*sc_pintr)(void *); 220 void *sc_parg; 221 222 void (*sc_rintr)(void *); 223 void *sc_rarg; 224 225 /* Power Management */ 226 void *sc_powerhook; 227 int sc_suspend; 228 }; 229 230 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 231 & AC97_EXT_AUDIO_VRA) 232 #define SUPPORTS_4CH(codec) ((codec)->vtbl->get_extcaps(codec) \ 233 & AC97_EXT_AUDIO_SDAC) 234 #define AC97_6CH_DACS (AC97_EXT_AUDIO_SDAC | AC97_EXT_AUDIO_CDAC \ 235 | AC97_EXT_AUDIO_LDAC) 236 #define SUPPORTS_6CH(codec) (((codec)->vtbl->get_extcaps(codec) \ 237 & AC97_6CH_DACS) == AC97_6CH_DACS) 238 239 /* Debug */ 240 #ifdef AUICH_DEBUG 241 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 242 int auich_debug = 0xfffe; 243 #define ICH_DEBUG_CODECIO 0x0001 244 #define ICH_DEBUG_DMA 0x0002 245 #define ICH_DEBUG_INTR 0x0004 246 #else 247 #define DPRINTF(x,y) /* nothing */ 248 #endif 249 250 int auich_match(struct device *, struct cfdata *, void *); 251 void auich_attach(struct device *, struct device *, void *); 252 int auich_intr(void *); 253 254 CFATTACH_DECL(auich, sizeof(struct auich_softc), 255 auich_match, auich_attach, NULL, NULL); 256 257 int auich_open(void *, int); 258 void auich_close(void *); 259 int auich_query_encoding(void *, struct audio_encoding *); 260 int auich_set_params(void *, int, int, struct audio_params *, 261 struct audio_params *); 262 int auich_round_blocksize(void *, int); 263 int auich_halt_output(void *); 264 int auich_halt_input(void *); 265 int auich_getdev(void *, struct audio_device *); 266 int auich_set_port(void *, mixer_ctrl_t *); 267 int auich_get_port(void *, mixer_ctrl_t *); 268 int auich_query_devinfo(void *, mixer_devinfo_t *); 269 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 270 void auich_freem(void *, void *, struct malloc_type *); 271 size_t auich_round_buffersize(void *, int, size_t); 272 paddr_t auich_mappage(void *, void *, off_t, int); 273 int auich_get_props(void *); 274 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 275 void *, struct audio_params *); 276 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 277 void *, struct audio_params *); 278 279 int auich_alloc_cdata(struct auich_softc *); 280 281 int auich_allocmem(struct auich_softc *, size_t, size_t, 282 struct auich_dma *); 283 int auich_freemem(struct auich_softc *, struct auich_dma *); 284 285 void auich_powerhook(int, void *); 286 int auich_set_rate(struct auich_softc *, int, u_long); 287 void auich_finish_attach(struct device *); 288 void auich_calibrate(struct auich_softc *); 289 290 291 struct audio_hw_if auich_hw_if = { 292 auich_open, 293 auich_close, 294 NULL, /* drain */ 295 auich_query_encoding, 296 auich_set_params, 297 auich_round_blocksize, 298 NULL, /* commit_setting */ 299 NULL, /* init_output */ 300 NULL, /* init_input */ 301 NULL, /* start_output */ 302 NULL, /* start_input */ 303 auich_halt_output, 304 auich_halt_input, 305 NULL, /* speaker_ctl */ 306 auich_getdev, 307 NULL, /* getfd */ 308 auich_set_port, 309 auich_get_port, 310 auich_query_devinfo, 311 auich_allocm, 312 auich_freem, 313 auich_round_buffersize, 314 auich_mappage, 315 auich_get_props, 316 auich_trigger_output, 317 auich_trigger_input, 318 NULL, /* dev_ioctl */ 319 }; 320 321 int auich_attach_codec(void *, struct ac97_codec_if *); 322 int auich_read_codec(void *, u_int8_t, u_int16_t *); 323 int auich_write_codec(void *, u_int8_t, u_int16_t); 324 int auich_reset_codec(void *); 325 326 static const struct auich_devtype { 327 int vendor; 328 int product; 329 const char *name; 330 const char *shortname; /* must be less than 11 characters */ 331 } auich_devices[] = { 332 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 333 "i82801AA (ICH) AC-97 Audio", "ICH" }, 334 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 335 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 336 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 337 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 338 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 339 "i82440MX AC-97 Audio", "440MX" }, 340 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 341 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 342 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 343 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 344 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 345 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 346 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 347 "SiS 7012 AC-97 Audio", "SiS7012" }, 348 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 349 "nForce MCP AC-97 Audio", "nForce" }, 350 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 351 "nForce2 MCP-T AC-97 Audio", "nForce2" }, 352 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 353 "nForce3 MCP-T AC-97 Audio", "nForce3" }, 354 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 355 "AMD768 AC-97 Audio", "AMD768" }, 356 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 357 "AMD8111 AC-97 Audio", "AMD8111" }, 358 { 0, 0, 359 NULL, NULL }, 360 }; 361 362 static const struct auich_devtype * 363 auich_lookup(struct pci_attach_args *pa) 364 { 365 const struct auich_devtype *d; 366 367 for (d = auich_devices; d->name != NULL; d++) { 368 if (PCI_VENDOR(pa->pa_id) == d->vendor 369 && PCI_PRODUCT(pa->pa_id) == d->product) 370 return (d); 371 } 372 373 return (NULL); 374 } 375 376 int 377 auich_match(struct device *parent, struct cfdata *match, void *aux) 378 { 379 struct pci_attach_args *pa = aux; 380 381 if (auich_lookup(pa) != NULL) 382 return (1); 383 384 return (0); 385 } 386 387 void 388 auich_attach(struct device *parent, struct device *self, void *aux) 389 { 390 struct auich_softc *sc = (struct auich_softc *)self; 391 struct pci_attach_args *pa = aux; 392 pci_intr_handle_t ih; 393 bus_size_t mix_size, aud_size; 394 pcireg_t v; 395 const char *intrstr; 396 const struct auich_devtype *d; 397 398 aprint_naive(": Audio controller\n"); 399 400 d = auich_lookup(pa); 401 if (d == NULL) 402 panic("auich_attach: impossible"); 403 404 #ifdef DIAGNOSTIC 405 sc->sc_pc = pa->pa_pc; 406 sc->sc_pt = pa->pa_tag; 407 #endif 408 409 aprint_normal(": %s\n", d->name); 410 411 if ((d->vendor == PCI_VENDOR_INTEL 412 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) 413 || (d->vendor == PCI_VENDOR_INTEL 414 && d->product == PCI_PRODUCT_INTEL_82801EB_AC)) { 415 /* 416 * Use native mode for ICH4/ICH5 417 */ 418 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 419 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 420 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 421 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 422 v | ICH_CFG_IOSE); 423 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 424 0, &sc->iot, &sc->mix_ioh, NULL, 425 &mix_size)) { 426 aprint_error("%s: can't map codec i/o space\n", 427 sc->sc_dev.dv_xname); 428 return; 429 } 430 } 431 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 432 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 433 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 434 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 435 v | ICH_CFG_IOSE); 436 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 437 0, &sc->iot, &sc->aud_ioh, NULL, 438 &aud_size)) { 439 aprint_error("%s: can't map device i/o space\n", 440 sc->sc_dev.dv_xname); 441 return; 442 } 443 } 444 } else { 445 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 446 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 447 aprint_error("%s: can't map codec i/o space\n", 448 sc->sc_dev.dv_xname); 449 return; 450 } 451 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 452 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 453 aprint_error("%s: can't map device i/o space\n", 454 sc->sc_dev.dv_xname); 455 return; 456 } 457 } 458 sc->dmat = pa->pa_dmat; 459 460 /* enable bus mastering */ 461 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 462 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 463 v | PCI_COMMAND_MASTER_ENABLE); 464 465 /* Map and establish the interrupt. */ 466 if (pci_intr_map(pa, &ih)) { 467 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 468 return; 469 } 470 intrstr = pci_intr_string(pa->pa_pc, ih); 471 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 472 auich_intr, sc); 473 if (sc->sc_ih == NULL) { 474 aprint_error("%s: can't establish interrupt", 475 sc->sc_dev.dv_xname); 476 if (intrstr != NULL) 477 aprint_normal(" at %s", intrstr); 478 aprint_normal("\n"); 479 return; 480 } 481 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 482 483 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 484 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 485 "0x%02x", PCI_REVISION(pa->pa_class)); 486 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 487 488 /* SiS 7012 needs special handling */ 489 if (d->vendor == PCI_VENDOR_SIS 490 && d->product == PCI_PRODUCT_SIS_7012_AC) { 491 sc->sc_sts_reg = ICH_PICB; 492 sc->sc_sample_size = 1; 493 } else { 494 sc->sc_sts_reg = ICH_STS; 495 sc->sc_sample_size = 2; 496 } 497 498 /* Workaround for a 440MX B-stepping erratum */ 499 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 500 if (d->vendor == PCI_VENDOR_INTEL 501 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 502 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 503 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 504 } 505 506 /* Set up DMA lists. */ 507 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 508 auich_alloc_cdata(sc); 509 510 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 511 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 512 513 sc->host_if.arg = sc; 514 sc->host_if.attach = auich_attach_codec; 515 sc->host_if.read = auich_read_codec; 516 sc->host_if.write = auich_write_codec; 517 sc->host_if.reset = auich_reset_codec; 518 519 if (ac97_attach(&sc->host_if) != 0) 520 return; 521 522 /* Watch for power change */ 523 sc->sc_suspend = PWR_RESUME; 524 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 525 526 config_interrupts(self, auich_finish_attach); 527 } 528 529 void 530 auich_finish_attach(struct device *self) 531 { 532 struct auich_softc *sc = (void *)self; 533 534 if (!IS_FIXED_RATE(sc->codec_if)) 535 auich_calibrate(sc); 536 537 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 538 } 539 540 #define ICH_CODECIO_INTERVAL 10 541 int 542 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 543 { 544 struct auich_softc *sc = v; 545 int i; 546 uint32_t status; 547 548 /* wait for an access semaphore */ 549 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 550 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 551 DELAY(ICH_CODECIO_INTERVAL)); 552 553 if (i > 0) { 554 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 555 DPRINTF(ICH_DEBUG_CODECIO, 556 ("auich_read_codec(%x, %x)\n", reg, *val)); 557 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 558 if (status & ICH_RCS) { 559 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 560 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 561 *val = 0xffff; 562 } 563 return 0; 564 } else { 565 DPRINTF(ICH_DEBUG_CODECIO, 566 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 567 return -1; 568 } 569 } 570 571 int 572 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 573 { 574 struct auich_softc *sc = v; 575 int i; 576 577 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 578 /* wait for an access semaphore */ 579 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 580 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 581 DELAY(ICH_CODECIO_INTERVAL)); 582 583 if (i > 0) { 584 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 585 return 0; 586 } else { 587 DPRINTF(ICH_DEBUG_CODECIO, 588 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 589 return -1; 590 } 591 } 592 593 int 594 auich_attach_codec(void *v, struct ac97_codec_if *cif) 595 { 596 struct auich_softc *sc = v; 597 598 sc->codec_if = cif; 599 return 0; 600 } 601 602 int 603 auich_reset_codec(void *v) 604 { 605 struct auich_softc *sc = v; 606 int i; 607 uint32_t control, status; 608 609 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 610 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 611 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 612 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 613 614 for (i = 500000; i >= 0; i--) { 615 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 616 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 617 break; 618 DELAY(1); 619 } 620 if (i <= 0) { 621 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 622 return ETIMEDOUT; 623 } 624 #ifdef DEBUG 625 if (status & ICH_SCR) 626 printf("%s: The 2nd codec is ready.\n", 627 sc->sc_dev.dv_xname); 628 if (status & ICH_S2CR) 629 printf("%s: The 3rd codec is ready.\n", 630 sc->sc_dev.dv_xname); 631 #endif 632 return 0; 633 } 634 635 int 636 auich_open(void *v, int flags) 637 { 638 return 0; 639 } 640 641 void 642 auich_close(void *v) 643 { 644 } 645 646 int 647 auich_query_encoding(void *v, struct audio_encoding *aep) 648 { 649 650 switch (aep->index) { 651 case 0: 652 strcpy(aep->name, AudioEulinear); 653 aep->encoding = AUDIO_ENCODING_ULINEAR; 654 aep->precision = 8; 655 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 656 return (0); 657 case 1: 658 strcpy(aep->name, AudioEmulaw); 659 aep->encoding = AUDIO_ENCODING_ULAW; 660 aep->precision = 8; 661 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 662 return (0); 663 case 2: 664 strcpy(aep->name, AudioEalaw); 665 aep->encoding = AUDIO_ENCODING_ALAW; 666 aep->precision = 8; 667 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 668 return (0); 669 case 3: 670 strcpy(aep->name, AudioEslinear); 671 aep->encoding = AUDIO_ENCODING_SLINEAR; 672 aep->precision = 8; 673 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 674 return (0); 675 case 4: 676 strcpy(aep->name, AudioEslinear_le); 677 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 678 aep->precision = 16; 679 aep->flags = 0; 680 return (0); 681 case 5: 682 strcpy(aep->name, AudioEulinear_le); 683 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 684 aep->precision = 16; 685 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 686 return (0); 687 case 6: 688 strcpy(aep->name, AudioEslinear_be); 689 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 690 aep->precision = 16; 691 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 692 return (0); 693 case 7: 694 strcpy(aep->name, AudioEulinear_be); 695 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 696 aep->precision = 16; 697 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 698 return (0); 699 default: 700 return (EINVAL); 701 } 702 } 703 704 int 705 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 706 { 707 int ret; 708 u_long ratetmp; 709 710 ratetmp = srate; 711 if (mode == AUMODE_RECORD) 712 return sc->codec_if->vtbl->set_rate(sc->codec_if, 713 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 714 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 715 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 716 if (ret) 717 return ret; 718 ratetmp = srate; 719 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 720 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 721 if (ret) 722 return ret; 723 ratetmp = srate; 724 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 725 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 726 return ret; 727 } 728 729 int 730 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 731 struct audio_params *rec) 732 { 733 struct auich_softc *sc = v; 734 struct audio_params *p; 735 int mode; 736 u_int32_t control; 737 738 for (mode = AUMODE_RECORD; mode != -1; 739 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 740 if ((setmode & mode) == 0) 741 continue; 742 743 p = mode == AUMODE_PLAY ? play : rec; 744 if (p == NULL) 745 continue; 746 747 if ((p->sample_rate != 8000) && 748 (p->sample_rate != 11025) && 749 (p->sample_rate != 12000) && 750 (p->sample_rate != 16000) && 751 (p->sample_rate != 22050) && 752 (p->sample_rate != 24000) && 753 (p->sample_rate != 32000) && 754 (p->sample_rate != 44100) && 755 (p->sample_rate != 48000)) 756 return (EINVAL); 757 758 p->factor = 1; 759 if (p->precision == 8) 760 p->factor *= 2; 761 762 p->sw_code = NULL; 763 /* setup hardware formats */ 764 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 765 p->hw_precision = 16; 766 767 if (mode == AUMODE_RECORD) { 768 if (p->channels < 1 || p->channels > 2) 769 return EINVAL; 770 } else { 771 switch (p->channels) { 772 case 1: 773 break; 774 case 2: 775 break; 776 case 4: 777 if (!SUPPORTS_4CH(sc->codec_if)) 778 return EINVAL; 779 break; 780 case 6: 781 if (!SUPPORTS_6CH(sc->codec_if)) 782 return EINVAL; 783 break; 784 default: 785 return EINVAL; 786 } 787 } 788 /* If monaural is requested, aurateconv expands a monaural 789 * stream to stereo. */ 790 if (p->channels == 1) 791 p->hw_channels = 2; 792 793 switch (p->encoding) { 794 case AUDIO_ENCODING_SLINEAR_BE: 795 if (p->precision == 16) { 796 p->sw_code = swap_bytes; 797 } else { 798 if (mode == AUMODE_PLAY) 799 p->sw_code = linear8_to_linear16_le; 800 else 801 p->sw_code = linear16_to_linear8_le; 802 } 803 break; 804 805 case AUDIO_ENCODING_SLINEAR_LE: 806 if (p->precision != 16) { 807 if (mode == AUMODE_PLAY) 808 p->sw_code = linear8_to_linear16_le; 809 else 810 p->sw_code = linear16_to_linear8_le; 811 } 812 break; 813 814 case AUDIO_ENCODING_ULINEAR_BE: 815 if (p->precision == 16) { 816 if (mode == AUMODE_PLAY) 817 p->sw_code = 818 swap_bytes_change_sign16_le; 819 else 820 p->sw_code = 821 change_sign16_swap_bytes_le; 822 } else { 823 if (mode == AUMODE_PLAY) 824 p->sw_code = 825 ulinear8_to_slinear16_le; 826 else 827 p->sw_code = 828 slinear16_to_ulinear8_le; 829 } 830 break; 831 832 case AUDIO_ENCODING_ULINEAR_LE: 833 if (p->precision == 16) { 834 p->sw_code = change_sign16_le; 835 } else { 836 if (mode == AUMODE_PLAY) 837 p->sw_code = 838 ulinear8_to_slinear16_le; 839 else 840 p->sw_code = 841 slinear16_to_ulinear8_le; 842 } 843 break; 844 845 case AUDIO_ENCODING_ULAW: 846 if (mode == AUMODE_PLAY) { 847 p->sw_code = mulaw_to_slinear16_le; 848 } else { 849 p->sw_code = slinear16_to_mulaw_le; 850 } 851 break; 852 853 case AUDIO_ENCODING_ALAW: 854 if (mode == AUMODE_PLAY) { 855 p->sw_code = alaw_to_slinear16_le; 856 } else { 857 p->sw_code = slinear16_to_alaw_le; 858 } 859 break; 860 861 default: 862 return (EINVAL); 863 } 864 865 if (IS_FIXED_RATE(sc->codec_if)) { 866 p->hw_sample_rate = AC97_SINGLE_RATE; 867 /* If hw_sample_rate is changed, aurateconv works. */ 868 } else { 869 if (auich_set_rate(sc, mode, p->sample_rate)) 870 return EINVAL; 871 } 872 if (mode == AUMODE_PLAY) { 873 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 874 control &= ~ICH_PCM246_MASK; 875 if (p->channels == 4) { 876 control |= ICH_PCM4; 877 } else if (p->channels == 6) { 878 control |= ICH_PCM6; 879 } 880 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 881 } 882 } 883 884 return (0); 885 } 886 887 int 888 auich_round_blocksize(void *v, int blk) 889 { 890 891 return (blk & ~0x3f); /* keep good alignment */ 892 } 893 894 int 895 auich_halt_output(void *v) 896 { 897 struct auich_softc *sc = v; 898 899 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 900 901 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 902 sc->sc_pintr = NULL; 903 904 return (0); 905 } 906 907 int 908 auich_halt_input(void *v) 909 { 910 struct auich_softc *sc = v; 911 912 DPRINTF(ICH_DEBUG_DMA, 913 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 914 915 /* XXX halt both unless known otherwise */ 916 917 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 918 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 919 sc->sc_rintr = NULL; 920 921 return (0); 922 } 923 924 int 925 auich_getdev(void *v, struct audio_device *adp) 926 { 927 struct auich_softc *sc = v; 928 929 *adp = sc->sc_audev; 930 return (0); 931 } 932 933 int 934 auich_set_port(void *v, mixer_ctrl_t *cp) 935 { 936 struct auich_softc *sc = v; 937 938 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 939 } 940 941 int 942 auich_get_port(void *v, mixer_ctrl_t *cp) 943 { 944 struct auich_softc *sc = v; 945 946 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 947 } 948 949 int 950 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 951 { 952 struct auich_softc *sc = v; 953 954 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 955 } 956 957 void * 958 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 959 int flags) 960 { 961 struct auich_softc *sc = v; 962 struct auich_dma *p; 963 int error; 964 965 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 966 return (NULL); 967 968 p = malloc(sizeof(*p), pool, flags|M_ZERO); 969 if (p == NULL) 970 return (NULL); 971 972 error = auich_allocmem(sc, size, 0, p); 973 if (error) { 974 free(p, pool); 975 return (NULL); 976 } 977 978 p->next = sc->sc_dmas; 979 sc->sc_dmas = p; 980 981 return (KERNADDR(p)); 982 } 983 984 void 985 auich_freem(void *v, void *ptr, struct malloc_type *pool) 986 { 987 struct auich_softc *sc = v; 988 struct auich_dma *p, **pp; 989 990 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 991 if (KERNADDR(p) == ptr) { 992 auich_freemem(sc, p); 993 *pp = p->next; 994 free(p, pool); 995 return; 996 } 997 } 998 } 999 1000 size_t 1001 auich_round_buffersize(void *v, int direction, size_t size) 1002 { 1003 1004 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1005 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1006 1007 return size; 1008 } 1009 1010 paddr_t 1011 auich_mappage(void *v, void *mem, off_t off, int prot) 1012 { 1013 struct auich_softc *sc = v; 1014 struct auich_dma *p; 1015 1016 if (off < 0) 1017 return (-1); 1018 1019 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1020 ; 1021 if (!p) 1022 return (-1); 1023 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1024 off, prot, BUS_DMA_WAITOK)); 1025 } 1026 1027 int 1028 auich_get_props(void *v) 1029 { 1030 struct auich_softc *sc = v; 1031 int props; 1032 1033 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1034 /* 1035 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1036 * rate because of aurateconv. Applications can't know what rate the 1037 * device can process in the case of mmap(). 1038 */ 1039 if (!IS_FIXED_RATE(sc->codec_if)) 1040 props |= AUDIO_PROP_MMAP; 1041 return props; 1042 } 1043 1044 int 1045 auich_intr(void *v) 1046 { 1047 struct auich_softc *sc = v; 1048 int ret = 0, sts, gsts, i, qptr; 1049 1050 #ifdef DIAGNOSTIC 1051 int csts; 1052 #endif 1053 1054 #ifdef DIAGNOSTIC 1055 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1056 if (csts & PCI_STATUS_MASTER_ABORT) { 1057 printf("auich_intr: PCI master abort\n"); 1058 } 1059 #endif 1060 1061 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 1062 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1063 1064 if (gsts & ICH_POINT) { 1065 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1066 ICH_PCMO + sc->sc_sts_reg); 1067 DPRINTF(ICH_DEBUG_INTR, 1068 ("auich_intr: osts=0x%x\n", sts)); 1069 1070 if (sts & ICH_FIFOE) { 1071 printf("%s: fifo underrun # %u\n", 1072 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1073 } 1074 1075 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1076 if (sts & (ICH_LVBCI | ICH_CELV)) { 1077 struct auich_dmalist *q; 1078 1079 qptr = sc->ptr_pcmo; 1080 1081 while (qptr != i) { 1082 q = &sc->dmalist_pcmo[qptr]; 1083 1084 q->base = sc->pcmo_p; 1085 q->len = (sc->pcmo_blksize / 1086 sc->sc_sample_size) | ICH_DMAF_IOC; 1087 DPRINTF(ICH_DEBUG_INTR, 1088 ("auich_intr: %p, %p = %x @ 0x%x\n", 1089 &sc->dmalist_pcmo[i], q, 1090 sc->pcmo_blksize / 2, sc->pcmo_p)); 1091 1092 sc->pcmo_p += sc->pcmo_blksize; 1093 if (sc->pcmo_p >= sc->pcmo_end) 1094 sc->pcmo_p = sc->pcmo_start; 1095 1096 if (++qptr == ICH_DMALIST_MAX) 1097 qptr = 0; 1098 } 1099 1100 sc->ptr_pcmo = qptr; 1101 bus_space_write_1(sc->iot, sc->aud_ioh, 1102 ICH_PCMO + ICH_LVI, 1103 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1104 } 1105 1106 if (sts & ICH_BCIS && sc->sc_pintr) 1107 sc->sc_pintr(sc->sc_parg); 1108 1109 /* int ack */ 1110 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1111 sc->sc_sts_reg, sts & (ICH_LVBCI | ICH_BCIS | ICH_FIFOE)); 1112 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1113 ret++; 1114 } 1115 1116 if (gsts & ICH_PIINT) { 1117 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1118 ICH_PCMI + sc->sc_sts_reg); 1119 DPRINTF(ICH_DEBUG_INTR, 1120 ("auich_intr: ists=0x%x\n", sts)); 1121 1122 if (sts & ICH_FIFOE) { 1123 printf("%s: fifo overrun # %u\n", 1124 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1125 } 1126 1127 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1128 if (sts & (ICH_LVBCI | ICH_CELV)) { 1129 struct auich_dmalist *q; 1130 1131 qptr = sc->ptr_pcmi; 1132 1133 while (qptr != i) { 1134 q = &sc->dmalist_pcmi[qptr]; 1135 1136 q->base = sc->pcmi_p; 1137 q->len = (sc->pcmi_blksize / 1138 sc->sc_sample_size) | ICH_DMAF_IOC; 1139 DPRINTF(ICH_DEBUG_INTR, 1140 ("auich_intr: %p, %p = %x @ 0x%x\n", 1141 &sc->dmalist_pcmi[i], q, 1142 sc->pcmi_blksize / 2, sc->pcmi_p)); 1143 1144 sc->pcmi_p += sc->pcmi_blksize; 1145 if (sc->pcmi_p >= sc->pcmi_end) 1146 sc->pcmi_p = sc->pcmi_start; 1147 1148 if (++qptr == ICH_DMALIST_MAX) 1149 qptr = 0; 1150 } 1151 1152 sc->ptr_pcmi = qptr; 1153 bus_space_write_1(sc->iot, sc->aud_ioh, 1154 ICH_PCMI + ICH_LVI, 1155 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1156 } 1157 1158 if (sts & ICH_BCIS && sc->sc_rintr) 1159 sc->sc_rintr(sc->sc_rarg); 1160 1161 /* int ack */ 1162 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1163 sc->sc_sts_reg, sts & (ICH_LVBCI | ICH_BCIS | ICH_FIFOE)); 1164 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1165 ret++; 1166 } 1167 1168 if (gsts & ICH_MIINT) { 1169 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1170 ICH_MICI + sc->sc_sts_reg); 1171 DPRINTF(ICH_DEBUG_INTR, 1172 ("auich_intr: ists=0x%x\n", sts)); 1173 if (sts & ICH_FIFOE) 1174 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1175 1176 /* TODO mic input DMA */ 1177 1178 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1179 } 1180 1181 return ret; 1182 } 1183 1184 int 1185 auich_trigger_output(void *v, void *start, void *end, int blksize, 1186 void (*intr)(void *), void *arg, struct audio_params *param) 1187 { 1188 struct auich_softc *sc = v; 1189 struct auich_dmalist *q; 1190 struct auich_dma *p; 1191 size_t size; 1192 #ifdef DIAGNOSTIC 1193 int csts; 1194 #endif 1195 1196 DPRINTF(ICH_DEBUG_DMA, 1197 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1198 start, end, blksize, intr, arg, param)); 1199 1200 sc->sc_pintr = intr; 1201 sc->sc_parg = arg; 1202 #ifdef DIAGNOSTIC 1203 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1204 if (csts & PCI_STATUS_MASTER_ABORT) { 1205 printf("auich_trigger_output: PCI master abort\n"); 1206 } 1207 #endif 1208 1209 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1210 ; 1211 if (!p) { 1212 printf("auich_trigger_output: bad addr %p\n", start); 1213 return (EINVAL); 1214 } 1215 1216 size = (size_t)((caddr_t)end - (caddr_t)start); 1217 1218 /* 1219 * The logic behind this is: 1220 * setup one buffer to play, then LVI dump out the rest 1221 * to the scatter-gather chain. 1222 */ 1223 sc->pcmo_start = DMAADDR(p); 1224 sc->pcmo_p = sc->pcmo_start + blksize; 1225 sc->pcmo_end = sc->pcmo_start + size; 1226 sc->pcmo_blksize = blksize; 1227 1228 sc->ptr_pcmo = 0; 1229 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1230 q->base = sc->pcmo_start; 1231 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1232 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1233 sc->ptr_pcmo = 0; 1234 1235 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1236 sc->sc_cddma + ICH_PCMO_OFF(0)); 1237 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1238 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1239 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1240 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1241 1242 return (0); 1243 } 1244 1245 int 1246 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1247 void *v; 1248 void *start, *end; 1249 int blksize; 1250 void (*intr)(void *); 1251 void *arg; 1252 struct audio_params *param; 1253 { 1254 struct auich_softc *sc = v; 1255 struct auich_dmalist *q; 1256 struct auich_dma *p; 1257 size_t size; 1258 #ifdef DIAGNOSTIC 1259 int csts; 1260 #endif 1261 1262 DPRINTF(ICH_DEBUG_DMA, 1263 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1264 start, end, blksize, intr, arg, param)); 1265 1266 sc->sc_rintr = intr; 1267 sc->sc_rarg = arg; 1268 1269 #ifdef DIAGNOSTIC 1270 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1271 if (csts & PCI_STATUS_MASTER_ABORT) { 1272 printf("auich_trigger_input: PCI master abort\n"); 1273 } 1274 #endif 1275 1276 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1277 ; 1278 if (!p) { 1279 printf("auich_trigger_input: bad addr %p\n", start); 1280 return (EINVAL); 1281 } 1282 1283 size = (size_t)((caddr_t)end - (caddr_t)start); 1284 1285 /* 1286 * The logic behind this is: 1287 * setup one buffer to play, then LVI dump out the rest 1288 * to the scatter-gather chain. 1289 */ 1290 sc->pcmi_start = DMAADDR(p); 1291 sc->pcmi_p = sc->pcmi_start + blksize; 1292 sc->pcmi_end = sc->pcmi_start + size; 1293 sc->pcmi_blksize = blksize; 1294 1295 sc->ptr_pcmi = 0; 1296 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1297 q->base = sc->pcmi_start; 1298 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1299 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1300 sc->ptr_pcmi = 0; 1301 1302 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1303 sc->sc_cddma + ICH_PCMI_OFF(0)); 1304 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1305 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1306 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1307 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1308 1309 return (0); 1310 } 1311 1312 int 1313 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1314 struct auich_dma *p) 1315 { 1316 int error; 1317 1318 p->size = size; 1319 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1320 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1321 &p->nsegs, BUS_DMA_NOWAIT); 1322 if (error) 1323 return (error); 1324 1325 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1326 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1327 if (error) 1328 goto free; 1329 1330 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1331 0, BUS_DMA_NOWAIT, &p->map); 1332 if (error) 1333 goto unmap; 1334 1335 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1336 BUS_DMA_NOWAIT); 1337 if (error) 1338 goto destroy; 1339 return (0); 1340 1341 destroy: 1342 bus_dmamap_destroy(sc->dmat, p->map); 1343 unmap: 1344 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1345 free: 1346 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1347 return (error); 1348 } 1349 1350 int 1351 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1352 { 1353 1354 bus_dmamap_unload(sc->dmat, p->map); 1355 bus_dmamap_destroy(sc->dmat, p->map); 1356 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1357 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1358 return (0); 1359 } 1360 1361 int 1362 auich_alloc_cdata(struct auich_softc *sc) 1363 { 1364 bus_dma_segment_t seg; 1365 int error, rseg; 1366 1367 /* 1368 * Allocate the control data structure, and create and load the 1369 * DMA map for it. 1370 */ 1371 if ((error = bus_dmamem_alloc(sc->dmat, 1372 sizeof(struct auich_cdata), 1373 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1374 printf("%s: unable to allocate control data, error = %d\n", 1375 sc->sc_dev.dv_xname, error); 1376 goto fail_0; 1377 } 1378 1379 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1380 sizeof(struct auich_cdata), 1381 (caddr_t *) &sc->sc_cdata, 1382 sc->sc_dmamap_flags)) != 0) { 1383 printf("%s: unable to map control data, error = %d\n", 1384 sc->sc_dev.dv_xname, error); 1385 goto fail_1; 1386 } 1387 1388 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1389 sizeof(struct auich_cdata), 0, 0, 1390 &sc->sc_cddmamap)) != 0) { 1391 printf("%s: unable to create control data DMA map, " 1392 "error = %d\n", sc->sc_dev.dv_xname, error); 1393 goto fail_2; 1394 } 1395 1396 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1397 sc->sc_cdata, sizeof(struct auich_cdata), 1398 NULL, 0)) != 0) { 1399 printf("%s: unable tp load control data DMA map, " 1400 "error = %d\n", sc->sc_dev.dv_xname, error); 1401 goto fail_3; 1402 } 1403 1404 return (0); 1405 1406 fail_3: 1407 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1408 fail_2: 1409 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1410 sizeof(struct auich_cdata)); 1411 fail_1: 1412 bus_dmamem_free(sc->dmat, &seg, rseg); 1413 fail_0: 1414 return (error); 1415 } 1416 1417 void 1418 auich_powerhook(int why, void *addr) 1419 { 1420 struct auich_softc *sc = (struct auich_softc *)addr; 1421 1422 switch (why) { 1423 case PWR_SUSPEND: 1424 case PWR_STANDBY: 1425 /* Power down */ 1426 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1427 sc->sc_suspend = why; 1428 break; 1429 1430 case PWR_RESUME: 1431 /* Wake up */ 1432 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1433 if (sc->sc_suspend == PWR_RESUME) { 1434 printf("%s: resume without suspend.\n", 1435 sc->sc_dev.dv_xname); 1436 sc->sc_suspend = why; 1437 return; 1438 } 1439 sc->sc_suspend = why; 1440 auich_reset_codec(sc); 1441 DELAY(1000); 1442 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1443 break; 1444 1445 case PWR_SOFTSUSPEND: 1446 case PWR_SOFTSTANDBY: 1447 case PWR_SOFTRESUME: 1448 break; 1449 } 1450 } 1451 1452 /* 1453 * Calibrate card (some boards are overclocked and need scaling) 1454 */ 1455 void 1456 auich_calibrate(struct auich_softc *sc) 1457 { 1458 struct timeval t1, t2; 1459 uint8_t ociv, nciv; 1460 uint64_t wait_us; 1461 uint32_t actual_48k_rate, bytes, ac97rate; 1462 void *temp_buffer; 1463 struct auich_dma *p; 1464 u_long rate; 1465 1466 /* 1467 * Grab audio from input for fixed interval and compare how 1468 * much we actually get with what we expect. Interval needs 1469 * to be sufficiently short that no interrupts are 1470 * generated. 1471 */ 1472 1473 /* Force the codec to a known state first. */ 1474 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1475 rate = 48000; 1476 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1477 &rate); 1478 1479 /* Setup a buffer */ 1480 bytes = 64000; 1481 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1482 1483 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1484 ; 1485 if (p == NULL) { 1486 printf("auich_calibrate: bad address %p\n", temp_buffer); 1487 return; 1488 } 1489 sc->dmalist_pcmi[0].base = DMAADDR(p); 1490 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size); 1491 1492 /* 1493 * our data format is stereo, 16 bit so each sample is 4 bytes. 1494 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1495 * we're going to start recording with interrupts disabled and measure 1496 * the time taken for one block to complete. we know the block size, 1497 * we know the time in microseconds, we calculate the sample rate: 1498 * 1499 * actual_rate [bps] = bytes / (time [s] * 4) 1500 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1501 * actual_rate [Hz] = (bytes * 250000) / time [us] 1502 */ 1503 1504 /* prepare */ 1505 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1506 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1507 sc->sc_cddma + ICH_PCMI_OFF(0)); 1508 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1509 (0 - 1) & ICH_LVI_MASK); 1510 1511 /* start */ 1512 microtime(&t1); 1513 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1514 1515 /* wait */ 1516 nciv = ociv; 1517 do { 1518 microtime(&t2); 1519 if (t2.tv_sec - t1.tv_sec > 1) 1520 break; 1521 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1522 ICH_PCMI + ICH_CIV); 1523 } while (nciv == ociv); 1524 microtime(&t2); 1525 1526 /* stop */ 1527 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1528 1529 /* reset */ 1530 DELAY(100); 1531 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1532 1533 /* turn time delta into us */ 1534 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1535 1536 auich_freem(sc, temp_buffer, M_DEVBUF); 1537 1538 if (nciv == ociv) { 1539 printf("%s: ac97 link rate calibration timed out after %" 1540 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1541 return; 1542 } 1543 1544 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1545 1546 if (actual_48k_rate < 50000) 1547 ac97rate = 48000; 1548 else 1549 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1550 1551 printf("%s: measured ac97 link rate at %d Hz", 1552 sc->sc_dev.dv_xname, actual_48k_rate); 1553 if (ac97rate != actual_48k_rate) 1554 printf(", will use %d Hz", ac97rate); 1555 printf("\n"); 1556 1557 sc->codec_if->vtbl->set_clock(sc->codec_if, ac97rate); 1558 } 1559
Indexes created Wed Oct 22 13:09:56 GMT 2025