auich.c revision 1.66
1 /* $NetBSD: auich.c,v 1.66 2004/10/31 05:50:58 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.66 2004/10/31 05:50:58 mycroft Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 bus_space_tag_t iot; 179 bus_space_handle_t mix_ioh; 180 bus_space_handle_t aud_ioh; 181 bus_dma_tag_t dmat; 182 183 struct ac97_codec_if *codec_if; 184 struct ac97_host_if host_if; 185 186 /* DMA scatter-gather lists. */ 187 bus_dmamap_t sc_cddmamap; 188 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 189 190 struct auich_cdata *sc_cdata; 191 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 192 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 193 #define dmalist_mici sc_cdata->ic_dmalist_mici 194 195 int ptr_pcmo, 196 ptr_pcmi, 197 ptr_mici; 198 199 /* i/o buffer pointers */ 200 u_int32_t pcmo_start, pcmo_p, pcmo_end; 201 int pcmo_blksize, pcmo_fifoe; 202 203 u_int32_t pcmi_start, pcmi_p, pcmi_end; 204 int pcmi_blksize, pcmi_fifoe; 205 206 u_int32_t mici_start, mici_p, mici_end; 207 int mici_blksize, mici_fifoe; 208 209 struct auich_dma *sc_dmas; 210 211 #ifdef DIAGNOSTIC 212 pci_chipset_tag_t sc_pc; 213 pcitag_t sc_pt; 214 #endif 215 /* SiS 7012 hack */ 216 int sc_sample_size; 217 int sc_sts_reg; 218 /* 440MX workaround */ 219 int sc_dmamap_flags; 220 221 void (*sc_pintr)(void *); 222 void *sc_parg; 223 224 void (*sc_rintr)(void *); 225 void *sc_rarg; 226 227 /* Power Management */ 228 void *sc_powerhook; 229 int sc_suspend; 230 231 /* sysctl */ 232 struct sysctllog *sc_log; 233 uint32_t sc_ac97_clock; 234 int sc_ac97_clock_mib; 235 }; 236 237 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 238 & AC97_EXT_AUDIO_VRA) 239 #define SUPPORTS_4CH(codec) ((codec)->vtbl->get_extcaps(codec) \ 240 & AC97_EXT_AUDIO_SDAC) 241 #define AC97_6CH_DACS (AC97_EXT_AUDIO_SDAC | AC97_EXT_AUDIO_CDAC \ 242 | AC97_EXT_AUDIO_LDAC) 243 #define SUPPORTS_6CH(codec) (((codec)->vtbl->get_extcaps(codec) \ 244 & AC97_6CH_DACS) == AC97_6CH_DACS) 245 246 /* Debug */ 247 #ifdef AUICH_DEBUG 248 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 249 int auich_debug = 0xfffe; 250 #define ICH_DEBUG_CODECIO 0x0001 251 #define ICH_DEBUG_DMA 0x0002 252 #define ICH_DEBUG_INTR 0x0004 253 #else 254 #define DPRINTF(x,y) /* nothing */ 255 #endif 256 257 int auich_match(struct device *, struct cfdata *, void *); 258 void auich_attach(struct device *, struct device *, void *); 259 int auich_intr(void *); 260 261 CFATTACH_DECL(auich, sizeof(struct auich_softc), 262 auich_match, auich_attach, NULL, NULL); 263 264 int auich_open(void *, int); 265 void auich_close(void *); 266 int auich_query_encoding(void *, struct audio_encoding *); 267 int auich_set_params(void *, int, int, struct audio_params *, 268 struct audio_params *); 269 int auich_round_blocksize(void *, int); 270 int auich_halt_output(void *); 271 int auich_halt_input(void *); 272 int auich_getdev(void *, struct audio_device *); 273 int auich_set_port(void *, mixer_ctrl_t *); 274 int auich_get_port(void *, mixer_ctrl_t *); 275 int auich_query_devinfo(void *, mixer_devinfo_t *); 276 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 277 void auich_freem(void *, void *, struct malloc_type *); 278 size_t auich_round_buffersize(void *, int, size_t); 279 paddr_t auich_mappage(void *, void *, off_t, int); 280 int auich_get_props(void *); 281 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 282 void *, struct audio_params *); 283 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 284 void *, struct audio_params *); 285 286 int auich_alloc_cdata(struct auich_softc *); 287 288 int auich_allocmem(struct auich_softc *, size_t, size_t, 289 struct auich_dma *); 290 int auich_freemem(struct auich_softc *, struct auich_dma *); 291 292 void auich_powerhook(int, void *); 293 int auich_set_rate(struct auich_softc *, int, u_long); 294 static int auich_sysctl_verify(SYSCTLFN_ARGS); 295 void auich_finish_attach(struct device *); 296 void auich_calibrate(struct auich_softc *); 297 298 299 const struct audio_hw_if auich_hw_if = { 300 auich_open, 301 auich_close, 302 NULL, /* drain */ 303 auich_query_encoding, 304 auich_set_params, 305 auich_round_blocksize, 306 NULL, /* commit_setting */ 307 NULL, /* init_output */ 308 NULL, /* init_input */ 309 NULL, /* start_output */ 310 NULL, /* start_input */ 311 auich_halt_output, 312 auich_halt_input, 313 NULL, /* speaker_ctl */ 314 auich_getdev, 315 NULL, /* getfd */ 316 auich_set_port, 317 auich_get_port, 318 auich_query_devinfo, 319 auich_allocm, 320 auich_freem, 321 auich_round_buffersize, 322 auich_mappage, 323 auich_get_props, 324 auich_trigger_output, 325 auich_trigger_input, 326 NULL, /* dev_ioctl */ 327 }; 328 329 int auich_attach_codec(void *, struct ac97_codec_if *); 330 int auich_read_codec(void *, u_int8_t, u_int16_t *); 331 int auich_write_codec(void *, u_int8_t, u_int16_t); 332 int auich_reset_codec(void *); 333 334 static const struct auich_devtype { 335 int vendor; 336 int product; 337 const char *name; 338 const char *shortname; /* must be less than 11 characters */ 339 } auich_devices[] = { 340 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 341 "i82801AA (ICH) AC-97 Audio", "ICH" }, 342 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 343 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 344 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 345 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 346 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 347 "i82440MX AC-97 Audio", "440MX" }, 348 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 349 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 350 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 351 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 352 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 353 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 354 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 355 "SiS 7012 AC-97 Audio", "SiS7012" }, 356 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 357 "nForce MCP AC-97 Audio", "nForce" }, 358 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 359 "nForce2 MCP-T AC-97 Audio", "nForce2" }, 360 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 361 "nForce3 MCP-T AC-97 Audio", "nForce3" }, 362 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 363 "AMD768 AC-97 Audio", "AMD768" }, 364 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 365 "AMD8111 AC-97 Audio", "AMD8111" }, 366 { 0, 0, 367 NULL, NULL }, 368 }; 369 370 static const struct auich_devtype * 371 auich_lookup(struct pci_attach_args *pa) 372 { 373 const struct auich_devtype *d; 374 375 for (d = auich_devices; d->name != NULL; d++) { 376 if (PCI_VENDOR(pa->pa_id) == d->vendor 377 && PCI_PRODUCT(pa->pa_id) == d->product) 378 return (d); 379 } 380 381 return (NULL); 382 } 383 384 int 385 auich_match(struct device *parent, struct cfdata *match, void *aux) 386 { 387 struct pci_attach_args *pa = aux; 388 389 if (auich_lookup(pa) != NULL) 390 return (1); 391 392 return (0); 393 } 394 395 void 396 auich_attach(struct device *parent, struct device *self, void *aux) 397 { 398 struct auich_softc *sc = (struct auich_softc *)self; 399 struct pci_attach_args *pa = aux; 400 pci_intr_handle_t ih; 401 bus_size_t mix_size, aud_size; 402 pcireg_t v; 403 const char *intrstr; 404 const struct auich_devtype *d; 405 struct sysctlnode *node; 406 int err, node_mib; 407 408 aprint_naive(": Audio controller\n"); 409 410 d = auich_lookup(pa); 411 if (d == NULL) 412 panic("auich_attach: impossible"); 413 414 #ifdef DIAGNOSTIC 415 sc->sc_pc = pa->pa_pc; 416 sc->sc_pt = pa->pa_tag; 417 #endif 418 419 aprint_normal(": %s\n", d->name); 420 421 if ((d->vendor == PCI_VENDOR_INTEL 422 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) 423 || (d->vendor == PCI_VENDOR_INTEL 424 && d->product == PCI_PRODUCT_INTEL_82801EB_AC)) { 425 /* 426 * Use native mode for ICH4/ICH5 427 */ 428 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 429 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 430 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 431 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 432 v | ICH_CFG_IOSE); 433 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 434 0, &sc->iot, &sc->mix_ioh, NULL, 435 &mix_size)) { 436 aprint_error("%s: can't map codec i/o space\n", 437 sc->sc_dev.dv_xname); 438 return; 439 } 440 } 441 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 442 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 443 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 444 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 445 v | ICH_CFG_IOSE); 446 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 447 0, &sc->iot, &sc->aud_ioh, NULL, 448 &aud_size)) { 449 aprint_error("%s: can't map device i/o space\n", 450 sc->sc_dev.dv_xname); 451 return; 452 } 453 } 454 } else { 455 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 456 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 457 aprint_error("%s: can't map codec i/o space\n", 458 sc->sc_dev.dv_xname); 459 return; 460 } 461 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 462 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 463 aprint_error("%s: can't map device i/o space\n", 464 sc->sc_dev.dv_xname); 465 return; 466 } 467 } 468 sc->dmat = pa->pa_dmat; 469 470 /* enable bus mastering */ 471 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 472 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 473 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 474 475 /* Map and establish the interrupt. */ 476 if (pci_intr_map(pa, &ih)) { 477 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 478 return; 479 } 480 intrstr = pci_intr_string(pa->pa_pc, ih); 481 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 482 auich_intr, sc); 483 if (sc->sc_ih == NULL) { 484 aprint_error("%s: can't establish interrupt", 485 sc->sc_dev.dv_xname); 486 if (intrstr != NULL) 487 aprint_normal(" at %s", intrstr); 488 aprint_normal("\n"); 489 return; 490 } 491 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 492 493 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 494 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 495 "0x%02x", PCI_REVISION(pa->pa_class)); 496 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 497 498 /* SiS 7012 needs special handling */ 499 if (d->vendor == PCI_VENDOR_SIS 500 && d->product == PCI_PRODUCT_SIS_7012_AC) { 501 sc->sc_sts_reg = ICH_PICB; 502 sc->sc_sample_size = 1; 503 } else { 504 sc->sc_sts_reg = ICH_STS; 505 sc->sc_sample_size = 2; 506 } 507 508 /* Workaround for a 440MX B-stepping erratum */ 509 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 510 if (d->vendor == PCI_VENDOR_INTEL 511 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 512 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 513 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 514 } 515 516 /* Set up DMA lists. */ 517 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 518 auich_alloc_cdata(sc); 519 520 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 521 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 522 523 sc->host_if.arg = sc; 524 sc->host_if.attach = auich_attach_codec; 525 sc->host_if.read = auich_read_codec; 526 sc->host_if.write = auich_write_codec; 527 sc->host_if.reset = auich_reset_codec; 528 529 if (ac97_attach(&sc->host_if) != 0) 530 return; 531 532 /* Watch for power change */ 533 sc->sc_suspend = PWR_RESUME; 534 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 535 536 config_interrupts(self, auich_finish_attach); 537 538 /* sysctl setup */ 539 if (IS_FIXED_RATE(sc->codec_if)) 540 return; 541 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 542 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 543 CTL_HW, CTL_EOL); 544 if (err != 0) 545 goto sysctl_err; 546 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 547 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 548 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 549 if (err != 0) 550 goto sysctl_err; 551 node_mib = node->sysctl_num; 552 /* passing the sc address instead of &sc->sc_ac97_clock */ 553 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 554 CTLTYPE_INT, "ac97rate", 555 SYSCTL_DESCR("AC'97 codec link rate"), 556 auich_sysctl_verify, 0, sc, 0, 557 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 558 if (err != 0) 559 goto sysctl_err; 560 sc->sc_ac97_clock_mib = node->sysctl_num; 561 562 return; 563 564 sysctl_err: 565 printf("%s: failed to add sysctl nodes. (%d)\n", 566 sc->sc_dev.dv_xname, err); 567 return; /* failure of sysctl is not fatal. */ 568 } 569 570 #if 0 571 int 572 auich_detach(struct device *self, int flags) 573 { 574 struct auich_softc *sc; 575 576 sc = (struct auich_softc *)self; 577 /* sysctl */ 578 sysctl_teardown(&sc->sc_log); 579 /* audio */ 580 if (sc->sc_audiodev != NULL) 581 config_detach(sc->sc_audiodev, flags); 582 /* XXX ac97 */ 583 /* XXX memory */ 584 return 0; 585 } 586 #endif 587 588 static int 589 auich_sysctl_verify(SYSCTLFN_ARGS) 590 { 591 int error, tmp; 592 struct sysctlnode node; 593 struct auich_softc *sc; 594 595 node = *rnode; 596 sc = rnode->sysctl_data; 597 tmp = sc->sc_ac97_clock; 598 node.sysctl_data = &tmp; 599 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 600 if (error || newp == NULL) 601 return error; 602 603 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 604 if (tmp < 48000 || tmp > 96000) 605 return EINVAL; 606 sc->sc_ac97_clock = tmp; 607 } 608 609 return 0; 610 } 611 612 void 613 auich_finish_attach(struct device *self) 614 { 615 struct auich_softc *sc = (void *)self; 616 617 if (!IS_FIXED_RATE(sc->codec_if)) 618 auich_calibrate(sc); 619 620 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 621 } 622 623 #define ICH_CODECIO_INTERVAL 10 624 int 625 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 626 { 627 struct auich_softc *sc = v; 628 int i; 629 uint32_t status; 630 631 /* wait for an access semaphore */ 632 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 633 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 634 DELAY(ICH_CODECIO_INTERVAL)); 635 636 if (i > 0) { 637 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 638 DPRINTF(ICH_DEBUG_CODECIO, 639 ("auich_read_codec(%x, %x)\n", reg, *val)); 640 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 641 if (status & ICH_RCS) { 642 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 643 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 644 *val = 0xffff; 645 } 646 return 0; 647 } else { 648 DPRINTF(ICH_DEBUG_CODECIO, 649 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 650 return -1; 651 } 652 } 653 654 int 655 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 656 { 657 struct auich_softc *sc = v; 658 int i; 659 660 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 661 /* wait for an access semaphore */ 662 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 663 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 664 DELAY(ICH_CODECIO_INTERVAL)); 665 666 if (i > 0) { 667 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 668 return 0; 669 } else { 670 DPRINTF(ICH_DEBUG_CODECIO, 671 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 672 return -1; 673 } 674 } 675 676 int 677 auich_attach_codec(void *v, struct ac97_codec_if *cif) 678 { 679 struct auich_softc *sc = v; 680 681 sc->codec_if = cif; 682 return 0; 683 } 684 685 int 686 auich_reset_codec(void *v) 687 { 688 struct auich_softc *sc = v; 689 int i; 690 uint32_t control, status; 691 692 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 693 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 694 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 695 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 696 697 for (i = 500000; i >= 0; i--) { 698 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 699 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 700 break; 701 DELAY(1); 702 } 703 if (i <= 0) { 704 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 705 return ETIMEDOUT; 706 } 707 #ifdef DEBUG 708 if (status & ICH_SCR) 709 printf("%s: The 2nd codec is ready.\n", 710 sc->sc_dev.dv_xname); 711 if (status & ICH_S2CR) 712 printf("%s: The 3rd codec is ready.\n", 713 sc->sc_dev.dv_xname); 714 #endif 715 return 0; 716 } 717 718 int 719 auich_open(void *v, int flags) 720 { 721 return 0; 722 } 723 724 void 725 auich_close(void *v) 726 { 727 } 728 729 int 730 auich_query_encoding(void *v, struct audio_encoding *aep) 731 { 732 733 switch (aep->index) { 734 case 0: 735 strcpy(aep->name, AudioEulinear); 736 aep->encoding = AUDIO_ENCODING_ULINEAR; 737 aep->precision = 8; 738 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 739 return (0); 740 case 1: 741 strcpy(aep->name, AudioEmulaw); 742 aep->encoding = AUDIO_ENCODING_ULAW; 743 aep->precision = 8; 744 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 745 return (0); 746 case 2: 747 strcpy(aep->name, AudioEalaw); 748 aep->encoding = AUDIO_ENCODING_ALAW; 749 aep->precision = 8; 750 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 751 return (0); 752 case 3: 753 strcpy(aep->name, AudioEslinear); 754 aep->encoding = AUDIO_ENCODING_SLINEAR; 755 aep->precision = 8; 756 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 757 return (0); 758 case 4: 759 strcpy(aep->name, AudioEslinear_le); 760 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 761 aep->precision = 16; 762 aep->flags = 0; 763 return (0); 764 case 5: 765 strcpy(aep->name, AudioEulinear_le); 766 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 767 aep->precision = 16; 768 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 769 return (0); 770 case 6: 771 strcpy(aep->name, AudioEslinear_be); 772 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 773 aep->precision = 16; 774 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 775 return (0); 776 case 7: 777 strcpy(aep->name, AudioEulinear_be); 778 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 779 aep->precision = 16; 780 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 781 return (0); 782 default: 783 return (EINVAL); 784 } 785 } 786 787 int 788 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 789 { 790 int ret; 791 u_long ratetmp; 792 793 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 794 ratetmp = srate; 795 if (mode == AUMODE_RECORD) 796 return sc->codec_if->vtbl->set_rate(sc->codec_if, 797 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 798 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 799 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 800 if (ret) 801 return ret; 802 ratetmp = srate; 803 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 804 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 805 if (ret) 806 return ret; 807 ratetmp = srate; 808 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 809 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 810 return ret; 811 } 812 813 int 814 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 815 struct audio_params *rec) 816 { 817 struct auich_softc *sc = v; 818 struct audio_params *p; 819 int mode; 820 u_int32_t control; 821 822 for (mode = AUMODE_RECORD; mode != -1; 823 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 824 if ((setmode & mode) == 0) 825 continue; 826 827 p = mode == AUMODE_PLAY ? play : rec; 828 if (p == NULL) 829 continue; 830 831 if ((p->sample_rate != 8000) && 832 (p->sample_rate != 11025) && 833 (p->sample_rate != 12000) && 834 (p->sample_rate != 16000) && 835 (p->sample_rate != 22050) && 836 (p->sample_rate != 24000) && 837 (p->sample_rate != 32000) && 838 (p->sample_rate != 44100) && 839 (p->sample_rate != 48000)) 840 return (EINVAL); 841 842 p->factor = 1; 843 if (p->precision == 8) 844 p->factor *= 2; 845 846 p->sw_code = NULL; 847 /* setup hardware formats */ 848 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 849 p->hw_precision = 16; 850 851 if (mode == AUMODE_RECORD) { 852 if (p->channels < 1 || p->channels > 2) 853 return EINVAL; 854 } else { 855 switch (p->channels) { 856 case 1: 857 break; 858 case 2: 859 break; 860 case 4: 861 if (!SUPPORTS_4CH(sc->codec_if)) 862 return EINVAL; 863 break; 864 case 6: 865 if (!SUPPORTS_6CH(sc->codec_if)) 866 return EINVAL; 867 break; 868 default: 869 return EINVAL; 870 } 871 } 872 /* If monaural is requested, aurateconv expands a monaural 873 * stream to stereo. */ 874 if (p->channels == 1) 875 p->hw_channels = 2; 876 877 switch (p->encoding) { 878 case AUDIO_ENCODING_SLINEAR_BE: 879 if (p->precision == 16) { 880 p->sw_code = swap_bytes; 881 } else { 882 if (mode == AUMODE_PLAY) 883 p->sw_code = linear8_to_linear16_le; 884 else 885 p->sw_code = linear16_to_linear8_le; 886 } 887 break; 888 889 case AUDIO_ENCODING_SLINEAR_LE: 890 if (p->precision != 16) { 891 if (mode == AUMODE_PLAY) 892 p->sw_code = linear8_to_linear16_le; 893 else 894 p->sw_code = linear16_to_linear8_le; 895 } 896 break; 897 898 case AUDIO_ENCODING_ULINEAR_BE: 899 if (p->precision == 16) { 900 if (mode == AUMODE_PLAY) 901 p->sw_code = 902 swap_bytes_change_sign16_le; 903 else 904 p->sw_code = 905 change_sign16_swap_bytes_le; 906 } else { 907 if (mode == AUMODE_PLAY) 908 p->sw_code = 909 ulinear8_to_slinear16_le; 910 else 911 p->sw_code = 912 slinear16_to_ulinear8_le; 913 } 914 break; 915 916 case AUDIO_ENCODING_ULINEAR_LE: 917 if (p->precision == 16) { 918 p->sw_code = change_sign16_le; 919 } else { 920 if (mode == AUMODE_PLAY) 921 p->sw_code = 922 ulinear8_to_slinear16_le; 923 else 924 p->sw_code = 925 slinear16_to_ulinear8_le; 926 } 927 break; 928 929 case AUDIO_ENCODING_ULAW: 930 if (mode == AUMODE_PLAY) { 931 p->sw_code = mulaw_to_slinear16_le; 932 } else { 933 p->sw_code = slinear16_to_mulaw_le; 934 } 935 break; 936 937 case AUDIO_ENCODING_ALAW: 938 if (mode == AUMODE_PLAY) { 939 p->sw_code = alaw_to_slinear16_le; 940 } else { 941 p->sw_code = slinear16_to_alaw_le; 942 } 943 break; 944 945 default: 946 return (EINVAL); 947 } 948 949 if (IS_FIXED_RATE(sc->codec_if)) { 950 p->hw_sample_rate = AC97_SINGLE_RATE; 951 /* If hw_sample_rate is changed, aurateconv works. */ 952 } else { 953 if (auich_set_rate(sc, mode, p->sample_rate)) 954 return EINVAL; 955 } 956 if (mode == AUMODE_PLAY) { 957 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 958 control &= ~ICH_PCM246_MASK; 959 if (p->channels == 4) { 960 control |= ICH_PCM4; 961 } else if (p->channels == 6) { 962 control |= ICH_PCM6; 963 } 964 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 965 } 966 } 967 968 return (0); 969 } 970 971 int 972 auich_round_blocksize(void *v, int blk) 973 { 974 975 return (blk & ~0x3f); /* keep good alignment */ 976 } 977 978 int 979 auich_halt_output(void *v) 980 { 981 struct auich_softc *sc = v; 982 983 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 984 985 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 986 sc->sc_pintr = NULL; 987 988 return (0); 989 } 990 991 int 992 auich_halt_input(void *v) 993 { 994 struct auich_softc *sc = v; 995 996 DPRINTF(ICH_DEBUG_DMA, 997 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 998 999 /* XXX halt both unless known otherwise */ 1000 1001 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1002 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 1003 sc->sc_rintr = NULL; 1004 1005 return (0); 1006 } 1007 1008 int 1009 auich_getdev(void *v, struct audio_device *adp) 1010 { 1011 struct auich_softc *sc = v; 1012 1013 *adp = sc->sc_audev; 1014 return (0); 1015 } 1016 1017 int 1018 auich_set_port(void *v, mixer_ctrl_t *cp) 1019 { 1020 struct auich_softc *sc = v; 1021 1022 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 1023 } 1024 1025 int 1026 auich_get_port(void *v, mixer_ctrl_t *cp) 1027 { 1028 struct auich_softc *sc = v; 1029 1030 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1031 } 1032 1033 int 1034 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1035 { 1036 struct auich_softc *sc = v; 1037 1038 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 1039 } 1040 1041 void * 1042 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 1043 int flags) 1044 { 1045 struct auich_softc *sc = v; 1046 struct auich_dma *p; 1047 int error; 1048 1049 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1050 return (NULL); 1051 1052 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1053 if (p == NULL) 1054 return (NULL); 1055 1056 error = auich_allocmem(sc, size, 0, p); 1057 if (error) { 1058 free(p, pool); 1059 return (NULL); 1060 } 1061 1062 p->next = sc->sc_dmas; 1063 sc->sc_dmas = p; 1064 1065 return (KERNADDR(p)); 1066 } 1067 1068 void 1069 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1070 { 1071 struct auich_softc *sc = v; 1072 struct auich_dma *p, **pp; 1073 1074 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1075 if (KERNADDR(p) == ptr) { 1076 auich_freemem(sc, p); 1077 *pp = p->next; 1078 free(p, pool); 1079 return; 1080 } 1081 } 1082 } 1083 1084 size_t 1085 auich_round_buffersize(void *v, int direction, size_t size) 1086 { 1087 1088 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1089 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1090 1091 return size; 1092 } 1093 1094 paddr_t 1095 auich_mappage(void *v, void *mem, off_t off, int prot) 1096 { 1097 struct auich_softc *sc = v; 1098 struct auich_dma *p; 1099 1100 if (off < 0) 1101 return (-1); 1102 1103 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1104 ; 1105 if (!p) 1106 return (-1); 1107 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1108 off, prot, BUS_DMA_WAITOK)); 1109 } 1110 1111 int 1112 auich_get_props(void *v) 1113 { 1114 struct auich_softc *sc = v; 1115 int props; 1116 1117 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1118 /* 1119 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1120 * rate because of aurateconv. Applications can't know what rate the 1121 * device can process in the case of mmap(). 1122 */ 1123 if (!IS_FIXED_RATE(sc->codec_if)) 1124 props |= AUDIO_PROP_MMAP; 1125 return props; 1126 } 1127 1128 int 1129 auich_intr(void *v) 1130 { 1131 struct auich_softc *sc = v; 1132 int ret = 0, sts, gsts, i, qptr; 1133 1134 #ifdef DIAGNOSTIC 1135 int csts; 1136 #endif 1137 1138 #ifdef DIAGNOSTIC 1139 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1140 if (csts & PCI_STATUS_MASTER_ABORT) { 1141 printf("auich_intr: PCI master abort\n"); 1142 } 1143 #endif 1144 1145 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 1146 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1147 1148 if (gsts & ICH_POINT) { 1149 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1150 ICH_PCMO + sc->sc_sts_reg); 1151 DPRINTF(ICH_DEBUG_INTR, 1152 ("auich_intr: osts=0x%x\n", sts)); 1153 1154 if (sts & ICH_FIFOE) { 1155 printf("%s: fifo underrun # %u\n", 1156 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1157 } 1158 1159 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1160 if (sts & (ICH_BCIS | ICH_LVBCI | ICH_CELV)) { 1161 struct auich_dmalist *q; 1162 1163 qptr = sc->ptr_pcmo; 1164 1165 while (qptr != i) { 1166 q = &sc->dmalist_pcmo[qptr]; 1167 1168 q->base = sc->pcmo_p; 1169 q->len = (sc->pcmo_blksize / 1170 sc->sc_sample_size) | ICH_DMAF_IOC; 1171 DPRINTF(ICH_DEBUG_INTR, 1172 ("auich_intr: %p, %p = %x @ 0x%x\n", 1173 &sc->dmalist_pcmo[i], q, 1174 sc->pcmo_blksize / 2, sc->pcmo_p)); 1175 1176 sc->pcmo_p += sc->pcmo_blksize; 1177 if (sc->pcmo_p >= sc->pcmo_end) 1178 sc->pcmo_p = sc->pcmo_start; 1179 1180 if (++qptr == ICH_DMALIST_MAX) 1181 qptr = 0; 1182 if (sc->sc_pintr) 1183 sc->sc_pintr(sc->sc_parg); 1184 1185 } 1186 1187 sc->ptr_pcmo = qptr; 1188 bus_space_write_1(sc->iot, sc->aud_ioh, 1189 ICH_PCMO + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1190 } 1191 1192 /* int ack */ 1193 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1194 sc->sc_sts_reg, sts & (ICH_CELV | ICH_LVBCI | ICH_BCIS | ICH_FIFOE)); 1195 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1196 ret++; 1197 } 1198 1199 if (gsts & ICH_PIINT) { 1200 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1201 ICH_PCMI + sc->sc_sts_reg); 1202 DPRINTF(ICH_DEBUG_INTR, 1203 ("auich_intr: ists=0x%x\n", sts)); 1204 1205 if (sts & ICH_FIFOE) { 1206 printf("%s: fifo overrun # %u\n", 1207 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1208 } 1209 1210 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1211 if (sts & (ICH_BCIS | ICH_LVBCI | ICH_CELV)) { 1212 struct auich_dmalist *q; 1213 1214 qptr = sc->ptr_pcmi; 1215 1216 while (qptr != i) { 1217 q = &sc->dmalist_pcmi[qptr]; 1218 1219 q->base = sc->pcmi_p; 1220 q->len = (sc->pcmi_blksize / 1221 sc->sc_sample_size) | ICH_DMAF_IOC; 1222 DPRINTF(ICH_DEBUG_INTR, 1223 ("auich_intr: %p, %p = %x @ 0x%x\n", 1224 &sc->dmalist_pcmi[i], q, 1225 sc->pcmi_blksize / 2, sc->pcmi_p)); 1226 1227 sc->pcmi_p += sc->pcmi_blksize; 1228 if (sc->pcmi_p >= sc->pcmi_end) 1229 sc->pcmi_p = sc->pcmi_start; 1230 1231 if (++qptr == ICH_DMALIST_MAX) 1232 qptr = 0; 1233 if (sc->sc_rintr) 1234 sc->sc_rintr(sc->sc_rarg); 1235 } 1236 1237 sc->ptr_pcmi = qptr; 1238 bus_space_write_1(sc->iot, sc->aud_ioh, 1239 ICH_PCMI + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1240 } 1241 1242 /* int ack */ 1243 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1244 sc->sc_sts_reg, sts & (ICH_CELV | ICH_LVBCI | ICH_BCIS | ICH_FIFOE)); 1245 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1246 ret++; 1247 } 1248 1249 if (gsts & ICH_MIINT) { 1250 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1251 ICH_MICI + sc->sc_sts_reg); 1252 DPRINTF(ICH_DEBUG_INTR, 1253 ("auich_intr: ists=0x%x\n", sts)); 1254 if (sts & ICH_FIFOE) 1255 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1256 1257 /* TODO mic input DMA */ 1258 1259 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1260 } 1261 1262 return ret; 1263 } 1264 1265 int 1266 auich_trigger_output(void *v, void *start, void *end, int blksize, 1267 void (*intr)(void *), void *arg, struct audio_params *param) 1268 { 1269 struct auich_softc *sc = v; 1270 struct auich_dmalist *q; 1271 struct auich_dma *p; 1272 size_t size; 1273 #ifdef DIAGNOSTIC 1274 int csts; 1275 #endif 1276 1277 DPRINTF(ICH_DEBUG_DMA, 1278 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1279 start, end, blksize, intr, arg, param)); 1280 1281 sc->sc_pintr = intr; 1282 sc->sc_parg = arg; 1283 #ifdef DIAGNOSTIC 1284 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1285 if (csts & PCI_STATUS_MASTER_ABORT) { 1286 printf("auich_trigger_output: PCI master abort\n"); 1287 } 1288 #endif 1289 1290 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1291 ; 1292 if (!p) { 1293 printf("auich_trigger_output: bad addr %p\n", start); 1294 return (EINVAL); 1295 } 1296 1297 size = (size_t)((caddr_t)end - (caddr_t)start); 1298 1299 /* 1300 * The logic behind this is: 1301 * setup one buffer to play, then LVI dump out the rest 1302 * to the scatter-gather chain. 1303 */ 1304 sc->pcmo_start = DMAADDR(p); 1305 sc->pcmo_p = sc->pcmo_start + blksize; 1306 sc->pcmo_end = sc->pcmo_start + size; 1307 sc->pcmo_blksize = blksize; 1308 1309 sc->ptr_pcmo = 0; 1310 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 1311 q->base = sc->pcmo_start; 1312 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1313 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 1314 sc->ptr_pcmo = 0; 1315 1316 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1317 sc->sc_cddma + ICH_PCMO_OFF(0)); 1318 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1319 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1320 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1321 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 1322 1323 return (0); 1324 } 1325 1326 int 1327 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1328 void *v; 1329 void *start, *end; 1330 int blksize; 1331 void (*intr)(void *); 1332 void *arg; 1333 struct audio_params *param; 1334 { 1335 struct auich_softc *sc = v; 1336 struct auich_dmalist *q; 1337 struct auich_dma *p; 1338 size_t size; 1339 #ifdef DIAGNOSTIC 1340 int csts; 1341 #endif 1342 1343 DPRINTF(ICH_DEBUG_DMA, 1344 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1345 start, end, blksize, intr, arg, param)); 1346 1347 sc->sc_rintr = intr; 1348 sc->sc_rarg = arg; 1349 1350 #ifdef DIAGNOSTIC 1351 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1352 if (csts & PCI_STATUS_MASTER_ABORT) { 1353 printf("auich_trigger_input: PCI master abort\n"); 1354 } 1355 #endif 1356 1357 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1358 ; 1359 if (!p) { 1360 printf("auich_trigger_input: bad addr %p\n", start); 1361 return (EINVAL); 1362 } 1363 1364 size = (size_t)((caddr_t)end - (caddr_t)start); 1365 1366 /* 1367 * The logic behind this is: 1368 * setup one buffer to play, then LVI dump out the rest 1369 * to the scatter-gather chain. 1370 */ 1371 sc->pcmi_start = DMAADDR(p); 1372 sc->pcmi_p = sc->pcmi_start + blksize; 1373 sc->pcmi_end = sc->pcmi_start + size; 1374 sc->pcmi_blksize = blksize; 1375 1376 sc->ptr_pcmi = 0; 1377 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1378 q->base = sc->pcmi_start; 1379 q->len = (blksize / sc->sc_sample_size) | ICH_DMAF_IOC; 1380 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1381 sc->ptr_pcmi = 0; 1382 1383 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1384 sc->sc_cddma + ICH_PCMI_OFF(0)); 1385 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1386 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1387 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1388 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1389 1390 return (0); 1391 } 1392 1393 int 1394 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1395 struct auich_dma *p) 1396 { 1397 int error; 1398 1399 p->size = size; 1400 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1401 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1402 &p->nsegs, BUS_DMA_NOWAIT); 1403 if (error) 1404 return (error); 1405 1406 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1407 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1408 if (error) 1409 goto free; 1410 1411 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1412 0, BUS_DMA_NOWAIT, &p->map); 1413 if (error) 1414 goto unmap; 1415 1416 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1417 BUS_DMA_NOWAIT); 1418 if (error) 1419 goto destroy; 1420 return (0); 1421 1422 destroy: 1423 bus_dmamap_destroy(sc->dmat, p->map); 1424 unmap: 1425 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1426 free: 1427 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1428 return (error); 1429 } 1430 1431 int 1432 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1433 { 1434 1435 bus_dmamap_unload(sc->dmat, p->map); 1436 bus_dmamap_destroy(sc->dmat, p->map); 1437 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1438 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1439 return (0); 1440 } 1441 1442 int 1443 auich_alloc_cdata(struct auich_softc *sc) 1444 { 1445 bus_dma_segment_t seg; 1446 int error, rseg; 1447 1448 /* 1449 * Allocate the control data structure, and create and load the 1450 * DMA map for it. 1451 */ 1452 if ((error = bus_dmamem_alloc(sc->dmat, 1453 sizeof(struct auich_cdata), 1454 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1455 printf("%s: unable to allocate control data, error = %d\n", 1456 sc->sc_dev.dv_xname, error); 1457 goto fail_0; 1458 } 1459 1460 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1461 sizeof(struct auich_cdata), 1462 (caddr_t *) &sc->sc_cdata, 1463 sc->sc_dmamap_flags)) != 0) { 1464 printf("%s: unable to map control data, error = %d\n", 1465 sc->sc_dev.dv_xname, error); 1466 goto fail_1; 1467 } 1468 1469 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1470 sizeof(struct auich_cdata), 0, 0, 1471 &sc->sc_cddmamap)) != 0) { 1472 printf("%s: unable to create control data DMA map, " 1473 "error = %d\n", sc->sc_dev.dv_xname, error); 1474 goto fail_2; 1475 } 1476 1477 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1478 sc->sc_cdata, sizeof(struct auich_cdata), 1479 NULL, 0)) != 0) { 1480 printf("%s: unable tp load control data DMA map, " 1481 "error = %d\n", sc->sc_dev.dv_xname, error); 1482 goto fail_3; 1483 } 1484 1485 return (0); 1486 1487 fail_3: 1488 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1489 fail_2: 1490 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1491 sizeof(struct auich_cdata)); 1492 fail_1: 1493 bus_dmamem_free(sc->dmat, &seg, rseg); 1494 fail_0: 1495 return (error); 1496 } 1497 1498 void 1499 auich_powerhook(int why, void *addr) 1500 { 1501 struct auich_softc *sc = (struct auich_softc *)addr; 1502 1503 switch (why) { 1504 case PWR_SUSPEND: 1505 case PWR_STANDBY: 1506 /* Power down */ 1507 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1508 sc->sc_suspend = why; 1509 break; 1510 1511 case PWR_RESUME: 1512 /* Wake up */ 1513 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1514 if (sc->sc_suspend == PWR_RESUME) { 1515 printf("%s: resume without suspend.\n", 1516 sc->sc_dev.dv_xname); 1517 sc->sc_suspend = why; 1518 return; 1519 } 1520 sc->sc_suspend = why; 1521 auich_reset_codec(sc); 1522 DELAY(1000); 1523 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1524 break; 1525 1526 case PWR_SOFTSUSPEND: 1527 case PWR_SOFTSTANDBY: 1528 case PWR_SOFTRESUME: 1529 break; 1530 } 1531 } 1532 1533 /* 1534 * Calibrate card (some boards are overclocked and need scaling) 1535 */ 1536 void 1537 auich_calibrate(struct auich_softc *sc) 1538 { 1539 struct timeval t1, t2; 1540 uint8_t ociv, nciv; 1541 uint64_t wait_us; 1542 uint32_t actual_48k_rate, bytes, ac97rate; 1543 void *temp_buffer; 1544 struct auich_dma *p; 1545 u_long rate; 1546 1547 /* 1548 * Grab audio from input for fixed interval and compare how 1549 * much we actually get with what we expect. Interval needs 1550 * to be sufficiently short that no interrupts are 1551 * generated. 1552 */ 1553 1554 /* Force the codec to a known state first. */ 1555 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1556 rate = 48000; 1557 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1558 &rate); 1559 1560 /* Setup a buffer */ 1561 bytes = 64000; 1562 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1563 1564 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1565 ; 1566 if (p == NULL) { 1567 printf("auich_calibrate: bad address %p\n", temp_buffer); 1568 return; 1569 } 1570 sc->dmalist_pcmi[0].base = DMAADDR(p); 1571 sc->dmalist_pcmi[0].len = (bytes / sc->sc_sample_size); 1572 1573 /* 1574 * our data format is stereo, 16 bit so each sample is 4 bytes. 1575 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1576 * we're going to start recording with interrupts disabled and measure 1577 * the time taken for one block to complete. we know the block size, 1578 * we know the time in microseconds, we calculate the sample rate: 1579 * 1580 * actual_rate [bps] = bytes / (time [s] * 4) 1581 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1582 * actual_rate [Hz] = (bytes * 250000) / time [us] 1583 */ 1584 1585 /* prepare */ 1586 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1587 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1588 sc->sc_cddma + ICH_PCMI_OFF(0)); 1589 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1590 (0 - 1) & ICH_LVI_MASK); 1591 1592 /* start */ 1593 microtime(&t1); 1594 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1595 1596 /* wait */ 1597 nciv = ociv; 1598 do { 1599 microtime(&t2); 1600 if (t2.tv_sec - t1.tv_sec > 1) 1601 break; 1602 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1603 ICH_PCMI + ICH_CIV); 1604 } while (nciv == ociv); 1605 microtime(&t2); 1606 1607 /* stop */ 1608 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1609 1610 /* reset */ 1611 DELAY(100); 1612 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1613 1614 /* turn time delta into us */ 1615 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1616 1617 auich_freem(sc, temp_buffer, M_DEVBUF); 1618 1619 if (nciv == ociv) { 1620 printf("%s: ac97 link rate calibration timed out after %" 1621 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1622 return; 1623 } 1624 1625 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1626 1627 if (actual_48k_rate < 50000) 1628 ac97rate = 48000; 1629 else 1630 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1631 1632 printf("%s: measured ac97 link rate at %d Hz", 1633 sc->sc_dev.dv_xname, actual_48k_rate); 1634 if (ac97rate != actual_48k_rate) 1635 printf(", will use %d Hz", ac97rate); 1636 printf("\n"); 1637 1638 sc->sc_ac97_clock = ac97rate; 1639 } 1640
Indexes created Wed Oct 22 13:09:56 GMT 2025