auich.c revision 1.72
1 /* $NetBSD: auich.c,v 1.72 2004/10/31 20:15:16 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.72 2004/10/31 20:15:16 mycroft Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 bus_space_tag_t iot; 179 bus_space_handle_t mix_ioh; 180 bus_space_handle_t aud_ioh; 181 bus_dma_tag_t dmat; 182 183 struct ac97_codec_if *codec_if; 184 struct ac97_host_if host_if; 185 186 /* DMA scatter-gather lists. */ 187 bus_dmamap_t sc_cddmamap; 188 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 189 190 struct auich_cdata *sc_cdata; 191 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 192 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 193 #define dmalist_mici sc_cdata->ic_dmalist_mici 194 195 int ptr_pcmo, 196 ptr_pcmi, 197 ptr_mici; 198 199 /* i/o buffer pointers */ 200 u_int32_t pcmo_start, pcmo_p, pcmo_end; 201 int pcmo_blksize, pcmo_fifoe; 202 203 u_int32_t pcmi_start, pcmi_p, pcmi_end; 204 int pcmi_blksize, pcmi_fifoe; 205 206 u_int32_t mici_start, mici_p, mici_end; 207 int mici_blksize, mici_fifoe; 208 209 struct auich_dma *sc_dmas; 210 211 #ifdef DIAGNOSTIC 212 pci_chipset_tag_t sc_pc; 213 pcitag_t sc_pt; 214 #endif 215 /* SiS 7012 hack */ 216 int sc_sample_shift; 217 int sc_sts_reg; 218 /* 440MX workaround */ 219 int sc_dmamap_flags; 220 221 void (*sc_pintr)(void *); 222 void *sc_parg; 223 224 void (*sc_rintr)(void *); 225 void *sc_rarg; 226 227 /* Power Management */ 228 void *sc_powerhook; 229 int sc_suspend; 230 231 /* sysctl */ 232 struct sysctllog *sc_log; 233 uint32_t sc_ac97_clock; 234 int sc_ac97_clock_mib; 235 }; 236 237 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 238 & AC97_EXT_AUDIO_VRA) 239 #define SUPPORTS_4CH(codec) ((codec)->vtbl->get_extcaps(codec) \ 240 & AC97_EXT_AUDIO_SDAC) 241 #define AC97_6CH_DACS (AC97_EXT_AUDIO_SDAC | AC97_EXT_AUDIO_CDAC \ 242 | AC97_EXT_AUDIO_LDAC) 243 #define SUPPORTS_6CH(codec) (((codec)->vtbl->get_extcaps(codec) \ 244 & AC97_6CH_DACS) == AC97_6CH_DACS) 245 246 /* Debug */ 247 #ifdef AUICH_DEBUG 248 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 249 int auich_debug = 0xfffe; 250 #define ICH_DEBUG_CODECIO 0x0001 251 #define ICH_DEBUG_DMA 0x0002 252 #define ICH_DEBUG_INTR 0x0004 253 #else 254 #define DPRINTF(x,y) /* nothing */ 255 #endif 256 257 int auich_match(struct device *, struct cfdata *, void *); 258 void auich_attach(struct device *, struct device *, void *); 259 int auich_intr(void *); 260 261 CFATTACH_DECL(auich, sizeof(struct auich_softc), 262 auich_match, auich_attach, NULL, NULL); 263 264 int auich_open(void *, int); 265 void auich_close(void *); 266 int auich_query_encoding(void *, struct audio_encoding *); 267 int auich_set_params(void *, int, int, struct audio_params *, 268 struct audio_params *); 269 int auich_round_blocksize(void *, int); 270 int auich_halt_output(void *); 271 int auich_halt_input(void *); 272 int auich_getdev(void *, struct audio_device *); 273 int auich_set_port(void *, mixer_ctrl_t *); 274 int auich_get_port(void *, mixer_ctrl_t *); 275 int auich_query_devinfo(void *, mixer_devinfo_t *); 276 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 277 void auich_freem(void *, void *, struct malloc_type *); 278 size_t auich_round_buffersize(void *, int, size_t); 279 paddr_t auich_mappage(void *, void *, off_t, int); 280 int auich_get_props(void *); 281 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 282 void *, struct audio_params *); 283 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 284 void *, struct audio_params *); 285 286 int auich_alloc_cdata(struct auich_softc *); 287 288 int auich_allocmem(struct auich_softc *, size_t, size_t, 289 struct auich_dma *); 290 int auich_freemem(struct auich_softc *, struct auich_dma *); 291 292 void auich_powerhook(int, void *); 293 int auich_set_rate(struct auich_softc *, int, u_long); 294 static int auich_sysctl_verify(SYSCTLFN_ARGS); 295 void auich_finish_attach(struct device *); 296 void auich_calibrate(struct auich_softc *); 297 298 299 const struct audio_hw_if auich_hw_if = { 300 auich_open, 301 auich_close, 302 NULL, /* drain */ 303 auich_query_encoding, 304 auich_set_params, 305 auich_round_blocksize, 306 NULL, /* commit_setting */ 307 NULL, /* init_output */ 308 NULL, /* init_input */ 309 NULL, /* start_output */ 310 NULL, /* start_input */ 311 auich_halt_output, 312 auich_halt_input, 313 NULL, /* speaker_ctl */ 314 auich_getdev, 315 NULL, /* getfd */ 316 auich_set_port, 317 auich_get_port, 318 auich_query_devinfo, 319 auich_allocm, 320 auich_freem, 321 auich_round_buffersize, 322 auich_mappage, 323 auich_get_props, 324 auich_trigger_output, 325 auich_trigger_input, 326 NULL, /* dev_ioctl */ 327 }; 328 329 int auich_attach_codec(void *, struct ac97_codec_if *); 330 int auich_read_codec(void *, u_int8_t, u_int16_t *); 331 int auich_write_codec(void *, u_int8_t, u_int16_t); 332 int auich_reset_codec(void *); 333 334 static const struct auich_devtype { 335 int vendor; 336 int product; 337 const char *name; 338 const char *shortname; /* must be less than 11 characters */ 339 } auich_devices[] = { 340 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 341 "i82801AA (ICH) AC-97 Audio", "ICH" }, 342 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 343 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 344 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 345 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 346 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 347 "i82440MX AC-97 Audio", "440MX" }, 348 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 349 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 350 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 351 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 352 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 353 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 354 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 355 "SiS 7012 AC-97 Audio", "SiS7012" }, 356 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 357 "nForce MCP AC-97 Audio", "nForce" }, 358 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 359 "nForce2 MCP-T AC-97 Audio", "nForce2" }, 360 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 361 "nForce3 MCP-T AC-97 Audio", "nForce3" }, 362 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 363 "AMD768 AC-97 Audio", "AMD768" }, 364 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 365 "AMD8111 AC-97 Audio", "AMD8111" }, 366 { 0, 0, 367 NULL, NULL }, 368 }; 369 370 static const struct auich_devtype * 371 auich_lookup(struct pci_attach_args *pa) 372 { 373 const struct auich_devtype *d; 374 375 for (d = auich_devices; d->name != NULL; d++) { 376 if (PCI_VENDOR(pa->pa_id) == d->vendor 377 && PCI_PRODUCT(pa->pa_id) == d->product) 378 return (d); 379 } 380 381 return (NULL); 382 } 383 384 int 385 auich_match(struct device *parent, struct cfdata *match, void *aux) 386 { 387 struct pci_attach_args *pa = aux; 388 389 if (auich_lookup(pa) != NULL) 390 return (1); 391 392 return (0); 393 } 394 395 void 396 auich_attach(struct device *parent, struct device *self, void *aux) 397 { 398 struct auich_softc *sc = (struct auich_softc *)self; 399 struct pci_attach_args *pa = aux; 400 pci_intr_handle_t ih; 401 bus_size_t mix_size, aud_size; 402 pcireg_t v; 403 const char *intrstr; 404 const struct auich_devtype *d; 405 struct sysctlnode *node; 406 int err, node_mib; 407 408 aprint_naive(": Audio controller\n"); 409 410 d = auich_lookup(pa); 411 if (d == NULL) 412 panic("auich_attach: impossible"); 413 414 #ifdef DIAGNOSTIC 415 sc->sc_pc = pa->pa_pc; 416 sc->sc_pt = pa->pa_tag; 417 #endif 418 419 aprint_normal(": %s\n", d->name); 420 421 if ((d->vendor == PCI_VENDOR_INTEL 422 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) 423 || (d->vendor == PCI_VENDOR_INTEL 424 && d->product == PCI_PRODUCT_INTEL_82801EB_AC)) { 425 /* 426 * Use native mode for ICH4/ICH5 427 */ 428 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 429 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 430 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 431 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 432 v | ICH_CFG_IOSE); 433 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 434 0, &sc->iot, &sc->mix_ioh, NULL, 435 &mix_size)) { 436 aprint_error("%s: can't map codec i/o space\n", 437 sc->sc_dev.dv_xname); 438 return; 439 } 440 } 441 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 442 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 443 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 444 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 445 v | ICH_CFG_IOSE); 446 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 447 0, &sc->iot, &sc->aud_ioh, NULL, 448 &aud_size)) { 449 aprint_error("%s: can't map device i/o space\n", 450 sc->sc_dev.dv_xname); 451 return; 452 } 453 } 454 } else { 455 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 456 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 457 aprint_error("%s: can't map codec i/o space\n", 458 sc->sc_dev.dv_xname); 459 return; 460 } 461 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 462 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 463 aprint_error("%s: can't map device i/o space\n", 464 sc->sc_dev.dv_xname); 465 return; 466 } 467 } 468 sc->dmat = pa->pa_dmat; 469 470 /* enable bus mastering */ 471 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 472 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 473 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 474 475 /* Map and establish the interrupt. */ 476 if (pci_intr_map(pa, &ih)) { 477 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 478 return; 479 } 480 intrstr = pci_intr_string(pa->pa_pc, ih); 481 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 482 auich_intr, sc); 483 if (sc->sc_ih == NULL) { 484 aprint_error("%s: can't establish interrupt", 485 sc->sc_dev.dv_xname); 486 if (intrstr != NULL) 487 aprint_normal(" at %s", intrstr); 488 aprint_normal("\n"); 489 return; 490 } 491 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 492 493 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 494 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 495 "0x%02x", PCI_REVISION(pa->pa_class)); 496 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 497 498 /* SiS 7012 needs special handling */ 499 if (d->vendor == PCI_VENDOR_SIS 500 && d->product == PCI_PRODUCT_SIS_7012_AC) { 501 sc->sc_sts_reg = ICH_PICB; 502 sc->sc_sample_shift = 0; 503 } else { 504 sc->sc_sts_reg = ICH_STS; 505 sc->sc_sample_shift = 1; 506 } 507 508 /* Workaround for a 440MX B-stepping erratum */ 509 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 510 if (d->vendor == PCI_VENDOR_INTEL 511 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 512 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 513 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 514 } 515 516 /* Set up DMA lists. */ 517 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 518 auich_alloc_cdata(sc); 519 520 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 521 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 522 523 sc->host_if.arg = sc; 524 sc->host_if.attach = auich_attach_codec; 525 sc->host_if.read = auich_read_codec; 526 sc->host_if.write = auich_write_codec; 527 sc->host_if.reset = auich_reset_codec; 528 529 if (ac97_attach(&sc->host_if) != 0) 530 return; 531 532 /* Watch for power change */ 533 sc->sc_suspend = PWR_RESUME; 534 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 535 536 config_interrupts(self, auich_finish_attach); 537 538 /* sysctl setup */ 539 if (IS_FIXED_RATE(sc->codec_if)) 540 return; 541 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 542 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 543 CTL_HW, CTL_EOL); 544 if (err != 0) 545 goto sysctl_err; 546 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 547 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 548 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 549 if (err != 0) 550 goto sysctl_err; 551 node_mib = node->sysctl_num; 552 /* passing the sc address instead of &sc->sc_ac97_clock */ 553 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 554 CTLTYPE_INT, "ac97rate", 555 SYSCTL_DESCR("AC'97 codec link rate"), 556 auich_sysctl_verify, 0, sc, 0, 557 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 558 if (err != 0) 559 goto sysctl_err; 560 sc->sc_ac97_clock_mib = node->sysctl_num; 561 562 return; 563 564 sysctl_err: 565 printf("%s: failed to add sysctl nodes. (%d)\n", 566 sc->sc_dev.dv_xname, err); 567 return; /* failure of sysctl is not fatal. */ 568 } 569 570 #if 0 571 int 572 auich_detach(struct device *self, int flags) 573 { 574 struct auich_softc *sc; 575 576 sc = (struct auich_softc *)self; 577 /* sysctl */ 578 sysctl_teardown(&sc->sc_log); 579 /* audio */ 580 if (sc->sc_audiodev != NULL) 581 config_detach(sc->sc_audiodev, flags); 582 /* XXX ac97 */ 583 /* XXX memory */ 584 return 0; 585 } 586 #endif 587 588 static int 589 auich_sysctl_verify(SYSCTLFN_ARGS) 590 { 591 int error, tmp; 592 struct sysctlnode node; 593 struct auich_softc *sc; 594 595 node = *rnode; 596 sc = rnode->sysctl_data; 597 tmp = sc->sc_ac97_clock; 598 node.sysctl_data = &tmp; 599 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 600 if (error || newp == NULL) 601 return error; 602 603 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 604 if (tmp < 48000 || tmp > 96000) 605 return EINVAL; 606 sc->sc_ac97_clock = tmp; 607 } 608 609 return 0; 610 } 611 612 void 613 auich_finish_attach(struct device *self) 614 { 615 struct auich_softc *sc = (void *)self; 616 617 if (!IS_FIXED_RATE(sc->codec_if)) 618 auich_calibrate(sc); 619 620 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 621 } 622 623 #define ICH_CODECIO_INTERVAL 10 624 int 625 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 626 { 627 struct auich_softc *sc = v; 628 int i; 629 uint32_t status; 630 631 /* wait for an access semaphore */ 632 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 633 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 634 DELAY(ICH_CODECIO_INTERVAL)); 635 636 if (i > 0) { 637 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 638 DPRINTF(ICH_DEBUG_CODECIO, 639 ("auich_read_codec(%x, %x)\n", reg, *val)); 640 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 641 if (status & ICH_RCS) { 642 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 643 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 644 *val = 0xffff; 645 } 646 return 0; 647 } else { 648 DPRINTF(ICH_DEBUG_CODECIO, 649 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 650 return -1; 651 } 652 } 653 654 int 655 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 656 { 657 struct auich_softc *sc = v; 658 int i; 659 660 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 661 /* wait for an access semaphore */ 662 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 663 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 664 DELAY(ICH_CODECIO_INTERVAL)); 665 666 if (i > 0) { 667 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 668 return 0; 669 } else { 670 DPRINTF(ICH_DEBUG_CODECIO, 671 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 672 return -1; 673 } 674 } 675 676 int 677 auich_attach_codec(void *v, struct ac97_codec_if *cif) 678 { 679 struct auich_softc *sc = v; 680 681 sc->codec_if = cif; 682 return 0; 683 } 684 685 int 686 auich_reset_codec(void *v) 687 { 688 struct auich_softc *sc = v; 689 int i; 690 uint32_t control, status; 691 692 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 693 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 694 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 695 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 696 697 for (i = 500000; i >= 0; i--) { 698 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 699 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 700 break; 701 DELAY(1); 702 } 703 if (i <= 0) { 704 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 705 return ETIMEDOUT; 706 } 707 #ifdef DEBUG 708 if (status & ICH_SCR) 709 printf("%s: The 2nd codec is ready.\n", 710 sc->sc_dev.dv_xname); 711 if (status & ICH_S2CR) 712 printf("%s: The 3rd codec is ready.\n", 713 sc->sc_dev.dv_xname); 714 #endif 715 return 0; 716 } 717 718 int 719 auich_open(void *v, int flags) 720 { 721 return 0; 722 } 723 724 void 725 auich_close(void *v) 726 { 727 } 728 729 int 730 auich_query_encoding(void *v, struct audio_encoding *aep) 731 { 732 static const struct auich_encoding { 733 const char *name; 734 int encoding, precision, flags; 735 } *p, auich_encoding[] = { 736 {AudioEulinear, AUDIO_ENCODING_ULINEAR, 737 8, AUDIO_ENCODINGFLAG_EMULATED}, 738 {AudioEmulaw, AUDIO_ENCODING_ULAW, 739 8, AUDIO_ENCODINGFLAG_EMULATED}, 740 {AudioEalaw, AUDIO_ENCODING_ALAW, 741 8, AUDIO_ENCODINGFLAG_EMULATED}, 742 {AudioEslinear, AUDIO_ENCODING_SLINEAR, 743 8, AUDIO_ENCODINGFLAG_EMULATED}, 744 {AudioEslinear_le, AUDIO_ENCODING_SLINEAR_LE, 745 16, 0}, 746 {AudioEulinear_le, AUDIO_ENCODING_ULINEAR_LE, 747 16, AUDIO_ENCODINGFLAG_EMULATED}, 748 {AudioEslinear_be, AUDIO_ENCODING_SLINEAR_BE, 749 16, AUDIO_ENCODINGFLAG_EMULATED}, 750 {AudioEulinear_be, AUDIO_ENCODING_ULINEAR_BE, 751 16, AUDIO_ENCODINGFLAG_EMULATED}, 752 }; 753 754 if (aep->index >= 8) 755 return (EINVAL); 756 757 p = &auich_encoding[aep->index]; 758 strcpy(aep->name, p->name); 759 aep->encoding = p->encoding; 760 aep->precision = p->precision; 761 aep->flags = p->flags; 762 return (0); 763 } 764 765 int 766 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 767 { 768 int ret; 769 u_long ratetmp; 770 771 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 772 ratetmp = srate; 773 if (mode == AUMODE_RECORD) 774 return sc->codec_if->vtbl->set_rate(sc->codec_if, 775 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 776 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 777 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 778 if (ret) 779 return ret; 780 ratetmp = srate; 781 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 782 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 783 if (ret) 784 return ret; 785 ratetmp = srate; 786 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 787 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 788 return ret; 789 } 790 791 int 792 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 793 struct audio_params *rec) 794 { 795 struct auich_softc *sc = v; 796 struct audio_params *p; 797 int mode; 798 u_int32_t control; 799 800 for (mode = AUMODE_RECORD; mode != -1; 801 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 802 if ((setmode & mode) == 0) 803 continue; 804 805 p = mode == AUMODE_PLAY ? play : rec; 806 if (p == NULL) 807 continue; 808 809 if (p->sample_rate < 8000 || 810 p->sample_rate > 48000) 811 return (EINVAL); 812 813 if (p->precision == 8) 814 p->factor = 2; 815 else 816 p->factor = 1; 817 818 p->sw_code = NULL; 819 /* setup hardware formats */ 820 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 821 p->hw_precision = 16; 822 823 if (mode == AUMODE_RECORD) { 824 if (p->channels < 1 || p->channels > 2) 825 return EINVAL; 826 } else { 827 switch (p->channels) { 828 case 1: 829 break; 830 case 2: 831 break; 832 case 4: 833 if (!SUPPORTS_4CH(sc->codec_if)) 834 return EINVAL; 835 break; 836 case 6: 837 if (!SUPPORTS_6CH(sc->codec_if)) 838 return EINVAL; 839 break; 840 default: 841 return EINVAL; 842 } 843 } 844 /* If monaural is requested, aurateconv expands a monaural 845 * stream to stereo. */ 846 if (p->channels == 1) 847 p->hw_channels = 2; 848 849 switch (p->encoding) { 850 case AUDIO_ENCODING_SLINEAR_BE: 851 if (p->precision == 16) { 852 p->sw_code = swap_bytes; 853 } else { 854 if (mode == AUMODE_PLAY) 855 p->sw_code = linear8_to_linear16_le; 856 else 857 p->sw_code = linear16_to_linear8_le; 858 } 859 break; 860 861 case AUDIO_ENCODING_SLINEAR_LE: 862 if (p->precision != 16) { 863 if (mode == AUMODE_PLAY) 864 p->sw_code = linear8_to_linear16_le; 865 else 866 p->sw_code = linear16_to_linear8_le; 867 } 868 break; 869 870 case AUDIO_ENCODING_ULINEAR_BE: 871 if (p->precision == 16) { 872 if (mode == AUMODE_PLAY) 873 p->sw_code = 874 swap_bytes_change_sign16_le; 875 else 876 p->sw_code = 877 change_sign16_swap_bytes_le; 878 } else { 879 if (mode == AUMODE_PLAY) 880 p->sw_code = 881 ulinear8_to_slinear16_le; 882 else 883 p->sw_code = 884 slinear16_to_ulinear8_le; 885 } 886 break; 887 888 case AUDIO_ENCODING_ULINEAR_LE: 889 if (p->precision == 16) { 890 p->sw_code = change_sign16_le; 891 } else { 892 if (mode == AUMODE_PLAY) 893 p->sw_code = 894 ulinear8_to_slinear16_le; 895 else 896 p->sw_code = 897 slinear16_to_ulinear8_le; 898 } 899 break; 900 901 case AUDIO_ENCODING_ULAW: 902 if (mode == AUMODE_PLAY) { 903 p->sw_code = mulaw_to_slinear16_le; 904 } else { 905 p->sw_code = slinear16_to_mulaw_le; 906 } 907 break; 908 909 case AUDIO_ENCODING_ALAW: 910 if (mode == AUMODE_PLAY) { 911 p->sw_code = alaw_to_slinear16_le; 912 } else { 913 p->sw_code = slinear16_to_alaw_le; 914 } 915 break; 916 917 default: 918 return (EINVAL); 919 } 920 921 if (IS_FIXED_RATE(sc->codec_if)) { 922 p->hw_sample_rate = AC97_SINGLE_RATE; 923 /* If hw_sample_rate is changed, aurateconv works. */ 924 } else { 925 if (auich_set_rate(sc, mode, p->sample_rate)) 926 return EINVAL; 927 } 928 if (mode == AUMODE_PLAY) { 929 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 930 control &= ~ICH_PCM246_MASK; 931 if (p->channels == 4) { 932 control |= ICH_PCM4; 933 } else if (p->channels == 6) { 934 control |= ICH_PCM6; 935 } 936 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 937 } 938 } 939 940 return (0); 941 } 942 943 int 944 auich_round_blocksize(void *v, int blk) 945 { 946 947 return (blk & ~0x3f); /* keep good alignment */ 948 } 949 950 int 951 auich_halt_output(void *v) 952 { 953 struct auich_softc *sc = v; 954 955 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 956 957 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 958 sc->sc_pintr = NULL; 959 960 return (0); 961 } 962 963 int 964 auich_halt_input(void *v) 965 { 966 struct auich_softc *sc = v; 967 968 DPRINTF(ICH_DEBUG_DMA, 969 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 970 971 /* XXX halt both unless known otherwise */ 972 973 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 974 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 975 sc->sc_rintr = NULL; 976 977 return (0); 978 } 979 980 int 981 auich_getdev(void *v, struct audio_device *adp) 982 { 983 struct auich_softc *sc = v; 984 985 *adp = sc->sc_audev; 986 return (0); 987 } 988 989 int 990 auich_set_port(void *v, mixer_ctrl_t *cp) 991 { 992 struct auich_softc *sc = v; 993 994 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 995 } 996 997 int 998 auich_get_port(void *v, mixer_ctrl_t *cp) 999 { 1000 struct auich_softc *sc = v; 1001 1002 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1003 } 1004 1005 int 1006 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1007 { 1008 struct auich_softc *sc = v; 1009 1010 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 1011 } 1012 1013 void * 1014 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 1015 int flags) 1016 { 1017 struct auich_softc *sc = v; 1018 struct auich_dma *p; 1019 int error; 1020 1021 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1022 return (NULL); 1023 1024 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1025 if (p == NULL) 1026 return (NULL); 1027 1028 error = auich_allocmem(sc, size, 0, p); 1029 if (error) { 1030 free(p, pool); 1031 return (NULL); 1032 } 1033 1034 p->next = sc->sc_dmas; 1035 sc->sc_dmas = p; 1036 1037 return (KERNADDR(p)); 1038 } 1039 1040 void 1041 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1042 { 1043 struct auich_softc *sc = v; 1044 struct auich_dma *p, **pp; 1045 1046 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1047 if (KERNADDR(p) == ptr) { 1048 auich_freemem(sc, p); 1049 *pp = p->next; 1050 free(p, pool); 1051 return; 1052 } 1053 } 1054 } 1055 1056 size_t 1057 auich_round_buffersize(void *v, int direction, size_t size) 1058 { 1059 1060 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1061 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1062 1063 return size; 1064 } 1065 1066 paddr_t 1067 auich_mappage(void *v, void *mem, off_t off, int prot) 1068 { 1069 struct auich_softc *sc = v; 1070 struct auich_dma *p; 1071 1072 if (off < 0) 1073 return (-1); 1074 1075 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1076 ; 1077 if (!p) 1078 return (-1); 1079 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1080 off, prot, BUS_DMA_WAITOK)); 1081 } 1082 1083 int 1084 auich_get_props(void *v) 1085 { 1086 struct auich_softc *sc = v; 1087 int props; 1088 1089 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1090 /* 1091 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1092 * rate because of aurateconv. Applications can't know what rate the 1093 * device can process in the case of mmap(). 1094 */ 1095 if (!IS_FIXED_RATE(sc->codec_if)) 1096 props |= AUDIO_PROP_MMAP; 1097 return props; 1098 } 1099 1100 int 1101 auich_intr(void *v) 1102 { 1103 struct auich_softc *sc = v; 1104 int ret = 0, sts, gsts, i; 1105 1106 #ifdef DIAGNOSTIC 1107 int csts; 1108 #endif 1109 1110 #ifdef DIAGNOSTIC 1111 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1112 if (csts & PCI_STATUS_MASTER_ABORT) { 1113 printf("auich_intr: PCI master abort\n"); 1114 } 1115 #endif 1116 1117 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 1118 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1119 1120 if (gsts & ICH_POINT) { 1121 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1122 ICH_PCMO + sc->sc_sts_reg); 1123 DPRINTF(ICH_DEBUG_INTR, 1124 ("auich_intr: osts=0x%x\n", sts)); 1125 1126 if (sts & ICH_FIFOE) { 1127 printf("%s: fifo underrun # %u\n", 1128 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 1129 } 1130 1131 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 1132 if (sts & (ICH_BCIS | ICH_LVBCI | ICH_CELV)) { 1133 struct auich_dmalist *q; 1134 int blksize, qptr; 1135 1136 blksize = sc->pcmo_blksize; 1137 qptr = sc->ptr_pcmo; 1138 1139 while (qptr != i) { 1140 q = &sc->dmalist_pcmo[qptr]; 1141 1142 q->base = sc->pcmo_p; 1143 q->len = (blksize >> sc->sc_sample_shift) | 1144 ICH_DMAF_IOC; 1145 DPRINTF(ICH_DEBUG_INTR, 1146 ("auich_intr: %p, %p = %x @ 0x%x\n", 1147 &sc->dmalist_pcmo[i], q, q->len, q->base)); 1148 1149 sc->pcmo_p += blksize; 1150 if (sc->pcmo_p >= sc->pcmo_end) 1151 sc->pcmo_p = sc->pcmo_start; 1152 1153 if (++qptr == ICH_DMALIST_MAX) 1154 qptr = 0; 1155 if (sc->sc_pintr) 1156 sc->sc_pintr(sc->sc_parg); 1157 } 1158 1159 sc->ptr_pcmo = qptr; 1160 bus_space_write_1(sc->iot, sc->aud_ioh, 1161 ICH_PCMO + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1162 } 1163 1164 /* int ack */ 1165 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1166 sc->sc_sts_reg, sts & (ICH_CELV | ICH_LVBCI | ICH_BCIS | ICH_FIFOE)); 1167 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1168 ret++; 1169 } 1170 1171 if (gsts & ICH_PIINT) { 1172 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1173 ICH_PCMI + sc->sc_sts_reg); 1174 DPRINTF(ICH_DEBUG_INTR, 1175 ("auich_intr: ists=0x%x\n", sts)); 1176 1177 if (sts & ICH_FIFOE) { 1178 printf("%s: fifo overrun # %u\n", 1179 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 1180 } 1181 1182 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1183 if (sts & (ICH_BCIS | ICH_LVBCI | ICH_CELV)) { 1184 struct auich_dmalist *q; 1185 int blksize, qptr; 1186 1187 blksize = sc->pcmi_blksize; 1188 qptr = sc->ptr_pcmi; 1189 1190 while (qptr != i) { 1191 q = &sc->dmalist_pcmi[qptr]; 1192 1193 q->base = sc->pcmi_p; 1194 q->len = (blksize >> sc->sc_sample_shift) | 1195 ICH_DMAF_IOC; 1196 DPRINTF(ICH_DEBUG_INTR, 1197 ("auich_intr: %p, %p = %x @ 0x%x\n", 1198 &sc->dmalist_pcmi[i], q, q->len, q->base)); 1199 1200 sc->pcmi_p += blksize; 1201 if (sc->pcmi_p >= sc->pcmi_end) 1202 sc->pcmi_p = sc->pcmi_start; 1203 1204 if (++qptr == ICH_DMALIST_MAX) 1205 qptr = 0; 1206 if (sc->sc_rintr) 1207 sc->sc_rintr(sc->sc_rarg); 1208 } 1209 1210 sc->ptr_pcmi = qptr; 1211 bus_space_write_1(sc->iot, sc->aud_ioh, 1212 ICH_PCMI + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1213 } 1214 1215 /* int ack */ 1216 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1217 sc->sc_sts_reg, sts & (ICH_CELV | ICH_LVBCI | ICH_BCIS | ICH_FIFOE)); 1218 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1219 ret++; 1220 } 1221 1222 if (gsts & ICH_MIINT) { 1223 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1224 ICH_MICI + sc->sc_sts_reg); 1225 DPRINTF(ICH_DEBUG_INTR, 1226 ("auich_intr: ists=0x%x\n", sts)); 1227 if (sts & ICH_FIFOE) 1228 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1229 1230 /* TODO mic input DMA */ 1231 1232 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1233 } 1234 1235 return ret; 1236 } 1237 1238 int 1239 auich_trigger_output(void *v, void *start, void *end, int blksize, 1240 void (*intr)(void *), void *arg, struct audio_params *param) 1241 { 1242 struct auich_softc *sc = v; 1243 struct auich_dmalist *q; 1244 struct auich_dma *p; 1245 size_t size; 1246 int qptr; 1247 #ifdef DIAGNOSTIC 1248 int csts; 1249 #endif 1250 1251 DPRINTF(ICH_DEBUG_DMA, 1252 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1253 start, end, blksize, intr, arg, param)); 1254 1255 sc->sc_pintr = intr; 1256 sc->sc_parg = arg; 1257 #ifdef DIAGNOSTIC 1258 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1259 if (csts & PCI_STATUS_MASTER_ABORT) { 1260 printf("auich_trigger_output: PCI master abort\n"); 1261 } 1262 #endif 1263 1264 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1265 ; 1266 if (!p) { 1267 printf("auich_trigger_output: bad addr %p\n", start); 1268 return (EINVAL); 1269 } 1270 1271 size = (size_t)((caddr_t)end - (caddr_t)start); 1272 1273 /* 1274 * The logic behind this is: 1275 * setup one buffer to play, then LVI dump out the rest 1276 * to the scatter-gather chain. 1277 */ 1278 sc->pcmo_start = DMAADDR(p); 1279 sc->pcmo_p = sc->pcmo_start; 1280 sc->pcmo_end = sc->pcmo_start + size; 1281 sc->pcmo_blksize = blksize; 1282 1283 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1284 q = &sc->dmalist_pcmo[qptr]; 1285 1286 q->base = sc->pcmo_p; 1287 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1288 1289 sc->pcmo_p += blksize; 1290 if (sc->pcmo_p >= sc->pcmo_end) 1291 sc->pcmo_p = sc->pcmo_start; 1292 } 1293 1294 sc->ptr_pcmo = qptr = 0; 1295 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1296 (qptr - 1) & ICH_LVI_MASK); 1297 1298 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1299 sc->sc_cddma + ICH_PCMO_OFF(0)); 1300 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1301 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1302 1303 return (0); 1304 } 1305 1306 int 1307 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1308 void *v; 1309 void *start, *end; 1310 int blksize; 1311 void (*intr)(void *); 1312 void *arg; 1313 struct audio_params *param; 1314 { 1315 struct auich_softc *sc = v; 1316 struct auich_dmalist *q; 1317 struct auich_dma *p; 1318 size_t size; 1319 int qptr; 1320 #ifdef DIAGNOSTIC 1321 int csts; 1322 #endif 1323 1324 DPRINTF(ICH_DEBUG_DMA, 1325 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1326 start, end, blksize, intr, arg, param)); 1327 1328 sc->sc_rintr = intr; 1329 sc->sc_rarg = arg; 1330 1331 #ifdef DIAGNOSTIC 1332 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1333 if (csts & PCI_STATUS_MASTER_ABORT) { 1334 printf("auich_trigger_input: PCI master abort\n"); 1335 } 1336 #endif 1337 1338 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1339 ; 1340 if (!p) { 1341 printf("auich_trigger_input: bad addr %p\n", start); 1342 return (EINVAL); 1343 } 1344 1345 size = (size_t)((caddr_t)end - (caddr_t)start); 1346 1347 /* 1348 * The logic behind this is: 1349 * setup one buffer to play, then LVI dump out the rest 1350 * to the scatter-gather chain. 1351 */ 1352 sc->pcmi_start = DMAADDR(p); 1353 sc->pcmi_p = sc->pcmi_start; 1354 sc->pcmi_end = sc->pcmi_start + size; 1355 sc->pcmi_blksize = blksize; 1356 1357 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1358 q = &sc->dmalist_pcmi[qptr]; 1359 1360 q->base = sc->pcmi_p; 1361 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1362 1363 sc->pcmi_p += blksize; 1364 if (sc->pcmi_p >= sc->pcmi_end) 1365 sc->pcmi_p = sc->pcmi_start; 1366 } 1367 1368 sc->ptr_pcmi = qptr = 0; 1369 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1370 (qptr - 1) & ICH_LVI_MASK); 1371 1372 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1373 sc->sc_cddma + ICH_PCMI_OFF(0)); 1374 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1375 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1376 1377 return (0); 1378 } 1379 1380 int 1381 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1382 struct auich_dma *p) 1383 { 1384 int error; 1385 1386 p->size = size; 1387 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1388 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1389 &p->nsegs, BUS_DMA_NOWAIT); 1390 if (error) 1391 return (error); 1392 1393 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1394 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1395 if (error) 1396 goto free; 1397 1398 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1399 0, BUS_DMA_NOWAIT, &p->map); 1400 if (error) 1401 goto unmap; 1402 1403 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1404 BUS_DMA_NOWAIT); 1405 if (error) 1406 goto destroy; 1407 return (0); 1408 1409 destroy: 1410 bus_dmamap_destroy(sc->dmat, p->map); 1411 unmap: 1412 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1413 free: 1414 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1415 return (error); 1416 } 1417 1418 int 1419 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1420 { 1421 1422 bus_dmamap_unload(sc->dmat, p->map); 1423 bus_dmamap_destroy(sc->dmat, p->map); 1424 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1425 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1426 return (0); 1427 } 1428 1429 int 1430 auich_alloc_cdata(struct auich_softc *sc) 1431 { 1432 bus_dma_segment_t seg; 1433 int error, rseg; 1434 1435 /* 1436 * Allocate the control data structure, and create and load the 1437 * DMA map for it. 1438 */ 1439 if ((error = bus_dmamem_alloc(sc->dmat, 1440 sizeof(struct auich_cdata), 1441 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1442 printf("%s: unable to allocate control data, error = %d\n", 1443 sc->sc_dev.dv_xname, error); 1444 goto fail_0; 1445 } 1446 1447 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1448 sizeof(struct auich_cdata), 1449 (caddr_t *) &sc->sc_cdata, 1450 sc->sc_dmamap_flags)) != 0) { 1451 printf("%s: unable to map control data, error = %d\n", 1452 sc->sc_dev.dv_xname, error); 1453 goto fail_1; 1454 } 1455 1456 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1457 sizeof(struct auich_cdata), 0, 0, 1458 &sc->sc_cddmamap)) != 0) { 1459 printf("%s: unable to create control data DMA map, " 1460 "error = %d\n", sc->sc_dev.dv_xname, error); 1461 goto fail_2; 1462 } 1463 1464 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1465 sc->sc_cdata, sizeof(struct auich_cdata), 1466 NULL, 0)) != 0) { 1467 printf("%s: unable tp load control data DMA map, " 1468 "error = %d\n", sc->sc_dev.dv_xname, error); 1469 goto fail_3; 1470 } 1471 1472 return (0); 1473 1474 fail_3: 1475 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1476 fail_2: 1477 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1478 sizeof(struct auich_cdata)); 1479 fail_1: 1480 bus_dmamem_free(sc->dmat, &seg, rseg); 1481 fail_0: 1482 return (error); 1483 } 1484 1485 void 1486 auich_powerhook(int why, void *addr) 1487 { 1488 struct auich_softc *sc = (struct auich_softc *)addr; 1489 1490 switch (why) { 1491 case PWR_SUSPEND: 1492 case PWR_STANDBY: 1493 /* Power down */ 1494 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1495 sc->sc_suspend = why; 1496 break; 1497 1498 case PWR_RESUME: 1499 /* Wake up */ 1500 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1501 if (sc->sc_suspend == PWR_RESUME) { 1502 printf("%s: resume without suspend.\n", 1503 sc->sc_dev.dv_xname); 1504 sc->sc_suspend = why; 1505 return; 1506 } 1507 sc->sc_suspend = why; 1508 auich_reset_codec(sc); 1509 DELAY(1000); 1510 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1511 break; 1512 1513 case PWR_SOFTSUSPEND: 1514 case PWR_SOFTSTANDBY: 1515 case PWR_SOFTRESUME: 1516 break; 1517 } 1518 } 1519 1520 /* 1521 * Calibrate card (some boards are overclocked and need scaling) 1522 */ 1523 void 1524 auich_calibrate(struct auich_softc *sc) 1525 { 1526 struct timeval t1, t2; 1527 uint8_t ociv, nciv; 1528 uint64_t wait_us; 1529 uint32_t actual_48k_rate, bytes, ac97rate; 1530 void *temp_buffer; 1531 struct auich_dma *p; 1532 u_long rate; 1533 1534 /* 1535 * Grab audio from input for fixed interval and compare how 1536 * much we actually get with what we expect. Interval needs 1537 * to be sufficiently short that no interrupts are 1538 * generated. 1539 */ 1540 1541 /* Force the codec to a known state first. */ 1542 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1543 rate = 48000; 1544 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1545 &rate); 1546 1547 /* Setup a buffer */ 1548 bytes = 64000; 1549 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1550 1551 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1552 ; 1553 if (p == NULL) { 1554 printf("auich_calibrate: bad address %p\n", temp_buffer); 1555 return; 1556 } 1557 sc->dmalist_pcmi[0].base = DMAADDR(p); 1558 sc->dmalist_pcmi[0].len = (bytes >> sc->sc_sample_shift); 1559 1560 /* 1561 * our data format is stereo, 16 bit so each sample is 4 bytes. 1562 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1563 * we're going to start recording with interrupts disabled and measure 1564 * the time taken for one block to complete. we know the block size, 1565 * we know the time in microseconds, we calculate the sample rate: 1566 * 1567 * actual_rate [bps] = bytes / (time [s] * 4) 1568 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1569 * actual_rate [Hz] = (bytes * 250000) / time [us] 1570 */ 1571 1572 /* prepare */ 1573 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1574 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1575 sc->sc_cddma + ICH_PCMI_OFF(0)); 1576 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1577 (0 - 1) & ICH_LVI_MASK); 1578 1579 /* start */ 1580 microtime(&t1); 1581 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1582 1583 /* wait */ 1584 nciv = ociv; 1585 do { 1586 microtime(&t2); 1587 if (t2.tv_sec - t1.tv_sec > 1) 1588 break; 1589 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1590 ICH_PCMI + ICH_CIV); 1591 } while (nciv == ociv); 1592 microtime(&t2); 1593 1594 /* stop */ 1595 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1596 1597 /* reset */ 1598 DELAY(100); 1599 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1600 1601 /* turn time delta into us */ 1602 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1603 1604 auich_freem(sc, temp_buffer, M_DEVBUF); 1605 1606 if (nciv == ociv) { 1607 printf("%s: ac97 link rate calibration timed out after %" 1608 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1609 return; 1610 } 1611 1612 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1613 1614 if (actual_48k_rate < 50000) 1615 ac97rate = 48000; 1616 else 1617 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1618 1619 printf("%s: measured ac97 link rate at %d Hz", 1620 sc->sc_dev.dv_xname, actual_48k_rate); 1621 if (ac97rate != actual_48k_rate) 1622 printf(", will use %d Hz", ac97rate); 1623 printf("\n"); 1624 1625 sc->sc_ac97_clock = ac97rate; 1626 } 1627
Indexes created Sun Oct 26 13:09:57 GMT 2025