auich.c revision 1.74
1 /* $NetBSD: auich.c,v 1.74 2004/11/06 08:41:14 xtraeme Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.74 2004/11/06 08:41:14 xtraeme Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 bus_space_tag_t iot; 179 bus_space_handle_t mix_ioh; 180 bus_space_handle_t aud_ioh; 181 bus_dma_tag_t dmat; 182 183 struct ac97_codec_if *codec_if; 184 struct ac97_host_if host_if; 185 186 /* DMA scatter-gather lists. */ 187 bus_dmamap_t sc_cddmamap; 188 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 189 190 struct auich_cdata *sc_cdata; 191 192 struct auich_ring { 193 int qptr; 194 struct auich_dmalist *dmalist; 195 196 u_int32_t start, p, end; 197 int blksize; 198 199 void (*intr)(void *); 200 void *arg; 201 } pcmo, pcmi, mici; 202 203 struct auich_dma *sc_dmas; 204 205 #ifdef DIAGNOSTIC 206 pci_chipset_tag_t sc_pc; 207 pcitag_t sc_pt; 208 #endif 209 /* SiS 7012 hack */ 210 int sc_sample_shift; 211 int sc_sts_reg; 212 /* 440MX workaround */ 213 int sc_dmamap_flags; 214 215 216 /* Power Management */ 217 void *sc_powerhook; 218 int sc_suspend; 219 220 /* sysctl */ 221 struct sysctllog *sc_log; 222 uint32_t sc_ac97_clock; 223 int sc_ac97_clock_mib; 224 }; 225 226 #define IS_FIXED_RATE(codec) !((codec)->vtbl->get_extcaps(codec) \ 227 & AC97_EXT_AUDIO_VRA) 228 #define SUPPORTS_4CH(codec) ((codec)->vtbl->get_extcaps(codec) \ 229 & AC97_EXT_AUDIO_SDAC) 230 #define AC97_6CH_DACS (AC97_EXT_AUDIO_SDAC | AC97_EXT_AUDIO_CDAC \ 231 | AC97_EXT_AUDIO_LDAC) 232 #define SUPPORTS_6CH(codec) (((codec)->vtbl->get_extcaps(codec) \ 233 & AC97_6CH_DACS) == AC97_6CH_DACS) 234 235 /* Debug */ 236 #ifdef AUICH_DEBUG 237 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 238 int auich_debug = 0xfffe; 239 #define ICH_DEBUG_CODECIO 0x0001 240 #define ICH_DEBUG_DMA 0x0002 241 #define ICH_DEBUG_INTR 0x0004 242 #else 243 #define DPRINTF(x,y) /* nothing */ 244 #endif 245 246 int auich_match(struct device *, struct cfdata *, void *); 247 void auich_attach(struct device *, struct device *, void *); 248 int auich_intr(void *); 249 250 CFATTACH_DECL(auich, sizeof(struct auich_softc), 251 auich_match, auich_attach, NULL, NULL); 252 253 int auich_open(void *, int); 254 void auich_close(void *); 255 int auich_query_encoding(void *, struct audio_encoding *); 256 int auich_set_params(void *, int, int, struct audio_params *, 257 struct audio_params *); 258 int auich_round_blocksize(void *, int); 259 int auich_halt_output(void *); 260 int auich_halt_input(void *); 261 int auich_getdev(void *, struct audio_device *); 262 int auich_set_port(void *, mixer_ctrl_t *); 263 int auich_get_port(void *, mixer_ctrl_t *); 264 int auich_query_devinfo(void *, mixer_devinfo_t *); 265 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 266 void auich_freem(void *, void *, struct malloc_type *); 267 size_t auich_round_buffersize(void *, int, size_t); 268 paddr_t auich_mappage(void *, void *, off_t, int); 269 int auich_get_props(void *); 270 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 271 void *, struct audio_params *); 272 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 273 void *, struct audio_params *); 274 275 int auich_alloc_cdata(struct auich_softc *); 276 277 int auich_allocmem(struct auich_softc *, size_t, size_t, 278 struct auich_dma *); 279 int auich_freemem(struct auich_softc *, struct auich_dma *); 280 281 void auich_powerhook(int, void *); 282 int auich_set_rate(struct auich_softc *, int, u_long); 283 static int auich_sysctl_verify(SYSCTLFN_ARGS); 284 void auich_finish_attach(struct device *); 285 void auich_calibrate(struct auich_softc *); 286 287 288 const struct audio_hw_if auich_hw_if = { 289 auich_open, 290 auich_close, 291 NULL, /* drain */ 292 auich_query_encoding, 293 auich_set_params, 294 auich_round_blocksize, 295 NULL, /* commit_setting */ 296 NULL, /* init_output */ 297 NULL, /* init_input */ 298 NULL, /* start_output */ 299 NULL, /* start_input */ 300 auich_halt_output, 301 auich_halt_input, 302 NULL, /* speaker_ctl */ 303 auich_getdev, 304 NULL, /* getfd */ 305 auich_set_port, 306 auich_get_port, 307 auich_query_devinfo, 308 auich_allocm, 309 auich_freem, 310 auich_round_buffersize, 311 auich_mappage, 312 auich_get_props, 313 auich_trigger_output, 314 auich_trigger_input, 315 NULL, /* dev_ioctl */ 316 }; 317 318 int auich_attach_codec(void *, struct ac97_codec_if *); 319 int auich_read_codec(void *, u_int8_t, u_int16_t *); 320 int auich_write_codec(void *, u_int8_t, u_int16_t); 321 int auich_reset_codec(void *); 322 323 static const struct auich_devtype { 324 int vendor; 325 int product; 326 const char *name; 327 const char *shortname; /* must be less than 11 characters */ 328 } auich_devices[] = { 329 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 330 "i82801AA (ICH) AC-97 Audio", "ICH" }, 331 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 332 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 333 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 334 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 335 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 336 "i82440MX AC-97 Audio", "440MX" }, 337 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 338 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 339 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 340 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 341 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 342 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 343 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 344 "SiS 7012 AC-97 Audio", "SiS7012" }, 345 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 346 "nForce MCP AC-97 Audio", "nForce" }, 347 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 348 "nForce2 MCP-T AC-97 Audio", "nForce2" }, 349 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 350 "nForce3 MCP-T AC-97 Audio", "nForce3" }, 351 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_MCPT_AC, 352 "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 353 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 354 "AMD768 AC-97 Audio", "AMD768" }, 355 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 356 "AMD8111 AC-97 Audio", "AMD8111" }, 357 { 0, 0, 358 NULL, NULL }, 359 }; 360 361 static const struct auich_devtype * 362 auich_lookup(struct pci_attach_args *pa) 363 { 364 const struct auich_devtype *d; 365 366 for (d = auich_devices; d->name != NULL; d++) { 367 if (PCI_VENDOR(pa->pa_id) == d->vendor 368 && PCI_PRODUCT(pa->pa_id) == d->product) 369 return (d); 370 } 371 372 return (NULL); 373 } 374 375 int 376 auich_match(struct device *parent, struct cfdata *match, void *aux) 377 { 378 struct pci_attach_args *pa = aux; 379 380 if (auich_lookup(pa) != NULL) 381 return (1); 382 383 return (0); 384 } 385 386 void 387 auich_attach(struct device *parent, struct device *self, void *aux) 388 { 389 struct auich_softc *sc = (struct auich_softc *)self; 390 struct pci_attach_args *pa = aux; 391 pci_intr_handle_t ih; 392 bus_size_t mix_size, aud_size; 393 pcireg_t v; 394 const char *intrstr; 395 const struct auich_devtype *d; 396 struct sysctlnode *node; 397 int err, node_mib; 398 399 aprint_naive(": Audio controller\n"); 400 401 d = auich_lookup(pa); 402 if (d == NULL) 403 panic("auich_attach: impossible"); 404 405 #ifdef DIAGNOSTIC 406 sc->sc_pc = pa->pa_pc; 407 sc->sc_pt = pa->pa_tag; 408 #endif 409 410 aprint_normal(": %s\n", d->name); 411 412 if ((d->vendor == PCI_VENDOR_INTEL 413 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) 414 || (d->vendor == PCI_VENDOR_INTEL 415 && d->product == PCI_PRODUCT_INTEL_82801EB_AC)) { 416 /* 417 * Use native mode for ICH4/ICH5 418 */ 419 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 420 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 421 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 422 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 423 v | ICH_CFG_IOSE); 424 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 425 0, &sc->iot, &sc->mix_ioh, NULL, 426 &mix_size)) { 427 aprint_error("%s: can't map codec i/o space\n", 428 sc->sc_dev.dv_xname); 429 return; 430 } 431 } 432 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 433 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 434 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 435 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 436 v | ICH_CFG_IOSE); 437 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 438 0, &sc->iot, &sc->aud_ioh, NULL, 439 &aud_size)) { 440 aprint_error("%s: can't map device i/o space\n", 441 sc->sc_dev.dv_xname); 442 return; 443 } 444 } 445 } else { 446 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 447 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 448 aprint_error("%s: can't map codec i/o space\n", 449 sc->sc_dev.dv_xname); 450 return; 451 } 452 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 453 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 454 aprint_error("%s: can't map device i/o space\n", 455 sc->sc_dev.dv_xname); 456 return; 457 } 458 } 459 sc->dmat = pa->pa_dmat; 460 461 /* enable bus mastering */ 462 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 463 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 464 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 465 466 /* Map and establish the interrupt. */ 467 if (pci_intr_map(pa, &ih)) { 468 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 469 return; 470 } 471 intrstr = pci_intr_string(pa->pa_pc, ih); 472 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 473 auich_intr, sc); 474 if (sc->sc_ih == NULL) { 475 aprint_error("%s: can't establish interrupt", 476 sc->sc_dev.dv_xname); 477 if (intrstr != NULL) 478 aprint_normal(" at %s", intrstr); 479 aprint_normal("\n"); 480 return; 481 } 482 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 483 484 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 485 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 486 "0x%02x", PCI_REVISION(pa->pa_class)); 487 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 488 489 /* SiS 7012 needs special handling */ 490 if (d->vendor == PCI_VENDOR_SIS 491 && d->product == PCI_PRODUCT_SIS_7012_AC) { 492 sc->sc_sts_reg = ICH_PICB; 493 sc->sc_sample_shift = 0; 494 } else { 495 sc->sc_sts_reg = ICH_STS; 496 sc->sc_sample_shift = 1; 497 } 498 499 /* Workaround for a 440MX B-stepping erratum */ 500 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 501 if (d->vendor == PCI_VENDOR_INTEL 502 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 503 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 504 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 505 } 506 507 /* Set up DMA lists. */ 508 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 509 auich_alloc_cdata(sc); 510 511 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 512 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 513 514 sc->host_if.arg = sc; 515 sc->host_if.attach = auich_attach_codec; 516 sc->host_if.read = auich_read_codec; 517 sc->host_if.write = auich_write_codec; 518 sc->host_if.reset = auich_reset_codec; 519 520 if (ac97_attach(&sc->host_if) != 0) 521 return; 522 523 /* Watch for power change */ 524 sc->sc_suspend = PWR_RESUME; 525 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 526 527 config_interrupts(self, auich_finish_attach); 528 529 /* sysctl setup */ 530 if (IS_FIXED_RATE(sc->codec_if)) 531 return; 532 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 533 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 534 CTL_HW, CTL_EOL); 535 if (err != 0) 536 goto sysctl_err; 537 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 538 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 539 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 540 if (err != 0) 541 goto sysctl_err; 542 node_mib = node->sysctl_num; 543 /* passing the sc address instead of &sc->sc_ac97_clock */ 544 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 545 CTLTYPE_INT, "ac97rate", 546 SYSCTL_DESCR("AC'97 codec link rate"), 547 auich_sysctl_verify, 0, sc, 0, 548 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 549 if (err != 0) 550 goto sysctl_err; 551 sc->sc_ac97_clock_mib = node->sysctl_num; 552 553 return; 554 555 sysctl_err: 556 printf("%s: failed to add sysctl nodes. (%d)\n", 557 sc->sc_dev.dv_xname, err); 558 return; /* failure of sysctl is not fatal. */ 559 } 560 561 #if 0 562 int 563 auich_detach(struct device *self, int flags) 564 { 565 struct auich_softc *sc; 566 567 sc = (struct auich_softc *)self; 568 /* sysctl */ 569 sysctl_teardown(&sc->sc_log); 570 /* audio */ 571 if (sc->sc_audiodev != NULL) 572 config_detach(sc->sc_audiodev, flags); 573 /* XXX ac97 */ 574 /* XXX memory */ 575 return 0; 576 } 577 #endif 578 579 static int 580 auich_sysctl_verify(SYSCTLFN_ARGS) 581 { 582 int error, tmp; 583 struct sysctlnode node; 584 struct auich_softc *sc; 585 586 node = *rnode; 587 sc = rnode->sysctl_data; 588 tmp = sc->sc_ac97_clock; 589 node.sysctl_data = &tmp; 590 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 591 if (error || newp == NULL) 592 return error; 593 594 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 595 if (tmp < 48000 || tmp > 96000) 596 return EINVAL; 597 sc->sc_ac97_clock = tmp; 598 } 599 600 return 0; 601 } 602 603 void 604 auich_finish_attach(struct device *self) 605 { 606 struct auich_softc *sc = (void *)self; 607 608 if (!IS_FIXED_RATE(sc->codec_if)) 609 auich_calibrate(sc); 610 611 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 612 } 613 614 #define ICH_CODECIO_INTERVAL 10 615 int 616 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 617 { 618 struct auich_softc *sc = v; 619 int i; 620 uint32_t status; 621 622 /* wait for an access semaphore */ 623 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 624 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 625 DELAY(ICH_CODECIO_INTERVAL)); 626 627 if (i > 0) { 628 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 629 DPRINTF(ICH_DEBUG_CODECIO, 630 ("auich_read_codec(%x, %x)\n", reg, *val)); 631 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 632 if (status & ICH_RCS) { 633 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 634 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 635 *val = 0xffff; 636 } 637 return 0; 638 } else { 639 DPRINTF(ICH_DEBUG_CODECIO, 640 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 641 return -1; 642 } 643 } 644 645 int 646 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 647 { 648 struct auich_softc *sc = v; 649 int i; 650 651 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 652 /* wait for an access semaphore */ 653 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 654 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 655 DELAY(ICH_CODECIO_INTERVAL)); 656 657 if (i > 0) { 658 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 659 return 0; 660 } else { 661 DPRINTF(ICH_DEBUG_CODECIO, 662 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 663 return -1; 664 } 665 } 666 667 int 668 auich_attach_codec(void *v, struct ac97_codec_if *cif) 669 { 670 struct auich_softc *sc = v; 671 672 sc->codec_if = cif; 673 return 0; 674 } 675 676 int 677 auich_reset_codec(void *v) 678 { 679 struct auich_softc *sc = v; 680 int i; 681 uint32_t control, status; 682 683 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 684 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 685 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 686 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 687 688 for (i = 500000; i >= 0; i--) { 689 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 690 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 691 break; 692 DELAY(1); 693 } 694 if (i <= 0) { 695 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 696 return ETIMEDOUT; 697 } 698 #ifdef DEBUG 699 if (status & ICH_SCR) 700 printf("%s: The 2nd codec is ready.\n", 701 sc->sc_dev.dv_xname); 702 if (status & ICH_S2CR) 703 printf("%s: The 3rd codec is ready.\n", 704 sc->sc_dev.dv_xname); 705 #endif 706 return 0; 707 } 708 709 int 710 auich_open(void *v, int flags) 711 { 712 return 0; 713 } 714 715 void 716 auich_close(void *v) 717 { 718 } 719 720 int 721 auich_query_encoding(void *v, struct audio_encoding *aep) 722 { 723 static const struct auich_encoding { 724 const char *name; 725 int encoding, precision, flags; 726 } *p, auich_encoding[] = { 727 {AudioEulinear, AUDIO_ENCODING_ULINEAR, 728 8, AUDIO_ENCODINGFLAG_EMULATED}, 729 {AudioEmulaw, AUDIO_ENCODING_ULAW, 730 8, AUDIO_ENCODINGFLAG_EMULATED}, 731 {AudioEalaw, AUDIO_ENCODING_ALAW, 732 8, AUDIO_ENCODINGFLAG_EMULATED}, 733 {AudioEslinear, AUDIO_ENCODING_SLINEAR, 734 8, AUDIO_ENCODINGFLAG_EMULATED}, 735 {AudioEslinear_le, AUDIO_ENCODING_SLINEAR_LE, 736 16, 0}, 737 {AudioEulinear_le, AUDIO_ENCODING_ULINEAR_LE, 738 16, AUDIO_ENCODINGFLAG_EMULATED}, 739 {AudioEslinear_be, AUDIO_ENCODING_SLINEAR_BE, 740 16, AUDIO_ENCODINGFLAG_EMULATED}, 741 {AudioEulinear_be, AUDIO_ENCODING_ULINEAR_BE, 742 16, AUDIO_ENCODINGFLAG_EMULATED}, 743 }; 744 745 if (aep->index >= 8) 746 return (EINVAL); 747 748 p = &auich_encoding[aep->index]; 749 strcpy(aep->name, p->name); 750 aep->encoding = p->encoding; 751 aep->precision = p->precision; 752 aep->flags = p->flags; 753 return (0); 754 } 755 756 int 757 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 758 { 759 int ret; 760 u_long ratetmp; 761 762 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 763 ratetmp = srate; 764 if (mode == AUMODE_RECORD) 765 return sc->codec_if->vtbl->set_rate(sc->codec_if, 766 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 767 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 768 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 769 if (ret) 770 return ret; 771 ratetmp = srate; 772 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 773 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 774 if (ret) 775 return ret; 776 ratetmp = srate; 777 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 778 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 779 return ret; 780 } 781 782 int 783 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 784 struct audio_params *rec) 785 { 786 struct auich_softc *sc = v; 787 struct audio_params *p; 788 int mode; 789 u_int32_t control; 790 791 for (mode = AUMODE_RECORD; mode != -1; 792 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 793 if ((setmode & mode) == 0) 794 continue; 795 796 p = mode == AUMODE_PLAY ? play : rec; 797 if (p == NULL) 798 continue; 799 800 if (p->sample_rate < 8000 || 801 p->sample_rate > 48000) 802 return (EINVAL); 803 804 if (p->precision == 8) 805 p->factor = 2; 806 else 807 p->factor = 1; 808 809 p->sw_code = NULL; 810 /* setup hardware formats */ 811 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 812 p->hw_precision = 16; 813 814 if (mode == AUMODE_RECORD) { 815 if (p->channels < 1 || p->channels > 2) 816 return EINVAL; 817 } else { 818 switch (p->channels) { 819 case 1: 820 break; 821 case 2: 822 break; 823 case 4: 824 if (!SUPPORTS_4CH(sc->codec_if)) 825 return EINVAL; 826 break; 827 case 6: 828 if (!SUPPORTS_6CH(sc->codec_if)) 829 return EINVAL; 830 break; 831 default: 832 return EINVAL; 833 } 834 } 835 /* If monaural is requested, aurateconv expands a monaural 836 * stream to stereo. */ 837 if (p->channels == 1) 838 p->hw_channels = 2; 839 840 switch (p->encoding) { 841 case AUDIO_ENCODING_SLINEAR_BE: 842 if (p->precision == 16) { 843 p->sw_code = swap_bytes; 844 } else { 845 if (mode == AUMODE_PLAY) 846 p->sw_code = linear8_to_linear16_le; 847 else 848 p->sw_code = linear16_to_linear8_le; 849 } 850 break; 851 852 case AUDIO_ENCODING_SLINEAR_LE: 853 if (p->precision != 16) { 854 if (mode == AUMODE_PLAY) 855 p->sw_code = linear8_to_linear16_le; 856 else 857 p->sw_code = linear16_to_linear8_le; 858 } 859 break; 860 861 case AUDIO_ENCODING_ULINEAR_BE: 862 if (p->precision == 16) { 863 if (mode == AUMODE_PLAY) 864 p->sw_code = 865 swap_bytes_change_sign16_le; 866 else 867 p->sw_code = 868 change_sign16_swap_bytes_le; 869 } else { 870 if (mode == AUMODE_PLAY) 871 p->sw_code = 872 ulinear8_to_slinear16_le; 873 else 874 p->sw_code = 875 slinear16_to_ulinear8_le; 876 } 877 break; 878 879 case AUDIO_ENCODING_ULINEAR_LE: 880 if (p->precision == 16) { 881 p->sw_code = change_sign16_le; 882 } else { 883 if (mode == AUMODE_PLAY) 884 p->sw_code = 885 ulinear8_to_slinear16_le; 886 else 887 p->sw_code = 888 slinear16_to_ulinear8_le; 889 } 890 break; 891 892 case AUDIO_ENCODING_ULAW: 893 if (mode == AUMODE_PLAY) { 894 p->sw_code = mulaw_to_slinear16_le; 895 } else { 896 p->sw_code = slinear16_to_mulaw_le; 897 } 898 break; 899 900 case AUDIO_ENCODING_ALAW: 901 if (mode == AUMODE_PLAY) { 902 p->sw_code = alaw_to_slinear16_le; 903 } else { 904 p->sw_code = slinear16_to_alaw_le; 905 } 906 break; 907 908 default: 909 return (EINVAL); 910 } 911 912 if (IS_FIXED_RATE(sc->codec_if)) { 913 p->hw_sample_rate = AC97_SINGLE_RATE; 914 /* If hw_sample_rate is changed, aurateconv works. */ 915 } else { 916 if (auich_set_rate(sc, mode, p->sample_rate)) 917 return EINVAL; 918 } 919 if (mode == AUMODE_PLAY) { 920 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 921 control &= ~ICH_PCM246_MASK; 922 if (p->channels == 4) { 923 control |= ICH_PCM4; 924 } else if (p->channels == 6) { 925 control |= ICH_PCM6; 926 } 927 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 928 } 929 } 930 931 return (0); 932 } 933 934 int 935 auich_round_blocksize(void *v, int blk) 936 { 937 938 return (blk & ~0x3f); /* keep good alignment */ 939 } 940 941 int 942 auich_halt_output(void *v) 943 { 944 struct auich_softc *sc = v; 945 946 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 947 948 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 949 sc->pcmo.intr = NULL; 950 951 return (0); 952 } 953 954 int 955 auich_halt_input(void *v) 956 { 957 struct auich_softc *sc = v; 958 959 DPRINTF(ICH_DEBUG_DMA, 960 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 961 962 /* XXX halt both unless known otherwise */ 963 964 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 965 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 966 sc->pcmi.intr = NULL; 967 968 return (0); 969 } 970 971 int 972 auich_getdev(void *v, struct audio_device *adp) 973 { 974 struct auich_softc *sc = v; 975 976 *adp = sc->sc_audev; 977 return (0); 978 } 979 980 int 981 auich_set_port(void *v, mixer_ctrl_t *cp) 982 { 983 struct auich_softc *sc = v; 984 985 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 986 } 987 988 int 989 auich_get_port(void *v, mixer_ctrl_t *cp) 990 { 991 struct auich_softc *sc = v; 992 993 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 994 } 995 996 int 997 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 998 { 999 struct auich_softc *sc = v; 1000 1001 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 1002 } 1003 1004 void * 1005 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 1006 int flags) 1007 { 1008 struct auich_softc *sc = v; 1009 struct auich_dma *p; 1010 int error; 1011 1012 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1013 return (NULL); 1014 1015 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1016 if (p == NULL) 1017 return (NULL); 1018 1019 error = auich_allocmem(sc, size, 0, p); 1020 if (error) { 1021 free(p, pool); 1022 return (NULL); 1023 } 1024 1025 p->next = sc->sc_dmas; 1026 sc->sc_dmas = p; 1027 1028 return (KERNADDR(p)); 1029 } 1030 1031 void 1032 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1033 { 1034 struct auich_softc *sc = v; 1035 struct auich_dma *p, **pp; 1036 1037 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1038 if (KERNADDR(p) == ptr) { 1039 auich_freemem(sc, p); 1040 *pp = p->next; 1041 free(p, pool); 1042 return; 1043 } 1044 } 1045 } 1046 1047 size_t 1048 auich_round_buffersize(void *v, int direction, size_t size) 1049 { 1050 1051 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1052 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1053 1054 return size; 1055 } 1056 1057 paddr_t 1058 auich_mappage(void *v, void *mem, off_t off, int prot) 1059 { 1060 struct auich_softc *sc = v; 1061 struct auich_dma *p; 1062 1063 if (off < 0) 1064 return (-1); 1065 1066 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1067 ; 1068 if (!p) 1069 return (-1); 1070 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1071 off, prot, BUS_DMA_WAITOK)); 1072 } 1073 1074 int 1075 auich_get_props(void *v) 1076 { 1077 struct auich_softc *sc = v; 1078 int props; 1079 1080 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1081 /* 1082 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1083 * rate because of aurateconv. Applications can't know what rate the 1084 * device can process in the case of mmap(). 1085 */ 1086 if (!IS_FIXED_RATE(sc->codec_if)) 1087 props |= AUDIO_PROP_MMAP; 1088 return props; 1089 } 1090 1091 int 1092 auich_intr(void *v) 1093 { 1094 struct auich_softc *sc = v; 1095 int ret = 0, gsts; 1096 1097 #ifdef DIAGNOSTIC 1098 int csts; 1099 #endif 1100 1101 #ifdef DIAGNOSTIC 1102 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1103 if (csts & PCI_STATUS_MASTER_ABORT) { 1104 printf("auich_intr: PCI master abort\n"); 1105 } 1106 #endif 1107 1108 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 1109 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1110 1111 if (gsts & ICH_POINT) { 1112 int sts; 1113 1114 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1115 ICH_PCMO + sc->sc_sts_reg); 1116 DPRINTF(ICH_DEBUG_INTR, 1117 ("auich_intr: osts=0x%x\n", sts)); 1118 1119 if (sts & ICH_FIFOE) 1120 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1121 1122 if (sts & ICH_BCIS) { 1123 struct auich_dmalist *q; 1124 int blksize, qptr, i; 1125 1126 blksize = sc->pcmo.blksize; 1127 qptr = sc->pcmo.qptr; 1128 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1129 ICH_PCMO + ICH_CIV); 1130 1131 while (qptr != i) { 1132 q = &sc->pcmo.dmalist[qptr]; 1133 1134 q->base = sc->pcmo.p; 1135 q->len = (blksize >> sc->sc_sample_shift) | 1136 ICH_DMAF_IOC; 1137 DPRINTF(ICH_DEBUG_INTR, 1138 ("auich_intr: %p, %p = %x @ 0x%x\n", 1139 &sc->pcmo.dmalist[i], q, q->len, q->base)); 1140 1141 sc->pcmo.p += blksize; 1142 if (sc->pcmo.p >= sc->pcmo.end) 1143 sc->pcmo.p = sc->pcmo.start; 1144 1145 qptr = (qptr + 1) & ICH_LVI_MASK; 1146 if (sc->pcmo.intr) 1147 sc->pcmo.intr(sc->pcmo.arg); 1148 } 1149 1150 sc->pcmo.qptr = qptr; 1151 bus_space_write_1(sc->iot, sc->aud_ioh, 1152 ICH_PCMO + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1153 } 1154 1155 /* int ack */ 1156 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1157 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1158 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1159 ret++; 1160 } 1161 1162 if (gsts & ICH_PIINT) { 1163 int sts; 1164 1165 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1166 ICH_PCMI + sc->sc_sts_reg); 1167 DPRINTF(ICH_DEBUG_INTR, 1168 ("auich_intr: ists=0x%x\n", sts)); 1169 1170 if (sts & ICH_FIFOE) 1171 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1172 1173 if (sts & ICH_BCIS) { 1174 struct auich_dmalist *q; 1175 int blksize, qptr, i; 1176 1177 blksize = sc->pcmi.blksize; 1178 qptr = sc->pcmi.qptr; 1179 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1180 ICH_PCMI + ICH_CIV); 1181 1182 while (qptr != i) { 1183 q = &sc->pcmi.dmalist[qptr]; 1184 1185 q->base = sc->pcmi.p; 1186 q->len = (blksize >> sc->sc_sample_shift) | 1187 ICH_DMAF_IOC; 1188 DPRINTF(ICH_DEBUG_INTR, 1189 ("auich_intr: %p, %p = %x @ 0x%x\n", 1190 &sc->pcmi.dmalist[i], q, q->len, q->base)); 1191 1192 sc->pcmi.p += blksize; 1193 if (sc->pcmi.p >= sc->pcmi.end) 1194 sc->pcmi.p = sc->pcmi.start; 1195 1196 qptr = (qptr + 1) & ICH_LVI_MASK; 1197 if (sc->pcmi.intr) 1198 sc->pcmi.intr(sc->pcmi.arg); 1199 } 1200 1201 sc->pcmi.qptr = qptr; 1202 bus_space_write_1(sc->iot, sc->aud_ioh, 1203 ICH_PCMI + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1204 } 1205 1206 /* int ack */ 1207 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1208 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1209 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1210 ret++; 1211 } 1212 1213 if (gsts & ICH_MIINT) { 1214 int sts; 1215 1216 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1217 ICH_MICI + sc->sc_sts_reg); 1218 DPRINTF(ICH_DEBUG_INTR, 1219 ("auich_intr: ists=0x%x\n", sts)); 1220 1221 if (sts & ICH_FIFOE) 1222 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1223 1224 /* TODO mic input DMA */ 1225 1226 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1227 } 1228 1229 return ret; 1230 } 1231 1232 int 1233 auich_trigger_output(void *v, void *start, void *end, int blksize, 1234 void (*intr)(void *), void *arg, struct audio_params *param) 1235 { 1236 struct auich_softc *sc = v; 1237 struct auich_dmalist *q; 1238 struct auich_dma *p; 1239 size_t size; 1240 int qptr; 1241 #ifdef DIAGNOSTIC 1242 int csts; 1243 #endif 1244 1245 DPRINTF(ICH_DEBUG_DMA, 1246 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1247 start, end, blksize, intr, arg, param)); 1248 1249 sc->pcmo.intr = intr; 1250 sc->pcmo.arg = arg; 1251 #ifdef DIAGNOSTIC 1252 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1253 if (csts & PCI_STATUS_MASTER_ABORT) { 1254 printf("auich_trigger_output: PCI master abort\n"); 1255 } 1256 #endif 1257 1258 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1259 ; 1260 if (!p) { 1261 printf("auich_trigger_output: bad addr %p\n", start); 1262 return (EINVAL); 1263 } 1264 1265 size = (size_t)((caddr_t)end - (caddr_t)start); 1266 1267 /* 1268 * The logic behind this is: 1269 * setup one buffer to play, then LVI dump out the rest 1270 * to the scatter-gather chain. 1271 */ 1272 sc->pcmo.start = DMAADDR(p); 1273 sc->pcmo.p = sc->pcmo.start; 1274 sc->pcmo.end = sc->pcmo.start + size; 1275 sc->pcmo.blksize = blksize; 1276 1277 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1278 q = &sc->pcmo.dmalist[qptr]; 1279 1280 q->base = sc->pcmo.p; 1281 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1282 1283 sc->pcmo.p += blksize; 1284 if (sc->pcmo.p >= sc->pcmo.end) 1285 sc->pcmo.p = sc->pcmo.start; 1286 } 1287 1288 sc->pcmo.qptr = qptr = 0; 1289 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1290 (qptr - 1) & ICH_LVI_MASK); 1291 1292 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1293 sc->sc_cddma + ICH_PCMO_OFF(0)); 1294 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1295 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1296 1297 return (0); 1298 } 1299 1300 int 1301 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1302 void *v; 1303 void *start, *end; 1304 int blksize; 1305 void (*intr)(void *); 1306 void *arg; 1307 struct audio_params *param; 1308 { 1309 struct auich_softc *sc = v; 1310 struct auich_dmalist *q; 1311 struct auich_dma *p; 1312 size_t size; 1313 int qptr; 1314 #ifdef DIAGNOSTIC 1315 int csts; 1316 #endif 1317 1318 DPRINTF(ICH_DEBUG_DMA, 1319 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1320 start, end, blksize, intr, arg, param)); 1321 1322 sc->pcmi.intr = intr; 1323 sc->pcmi.arg = arg; 1324 1325 #ifdef DIAGNOSTIC 1326 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1327 if (csts & PCI_STATUS_MASTER_ABORT) { 1328 printf("auich_trigger_input: PCI master abort\n"); 1329 } 1330 #endif 1331 1332 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1333 ; 1334 if (!p) { 1335 printf("auich_trigger_input: bad addr %p\n", start); 1336 return (EINVAL); 1337 } 1338 1339 size = (size_t)((caddr_t)end - (caddr_t)start); 1340 1341 /* 1342 * The logic behind this is: 1343 * setup one buffer to play, then LVI dump out the rest 1344 * to the scatter-gather chain. 1345 */ 1346 sc->pcmi.start = DMAADDR(p); 1347 sc->pcmi.p = sc->pcmi.start; 1348 sc->pcmi.end = sc->pcmi.start + size; 1349 sc->pcmi.blksize = blksize; 1350 1351 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1352 q = &sc->pcmi.dmalist[qptr]; 1353 1354 q->base = sc->pcmi.p; 1355 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1356 1357 sc->pcmi.p += blksize; 1358 if (sc->pcmi.p >= sc->pcmi.end) 1359 sc->pcmi.p = sc->pcmi.start; 1360 } 1361 1362 sc->pcmi.qptr = qptr = 0; 1363 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1364 (qptr - 1) & ICH_LVI_MASK); 1365 1366 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1367 sc->sc_cddma + ICH_PCMI_OFF(0)); 1368 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1369 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1370 1371 return (0); 1372 } 1373 1374 int 1375 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1376 struct auich_dma *p) 1377 { 1378 int error; 1379 1380 p->size = size; 1381 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1382 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1383 &p->nsegs, BUS_DMA_NOWAIT); 1384 if (error) 1385 return (error); 1386 1387 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1388 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1389 if (error) 1390 goto free; 1391 1392 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1393 0, BUS_DMA_NOWAIT, &p->map); 1394 if (error) 1395 goto unmap; 1396 1397 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1398 BUS_DMA_NOWAIT); 1399 if (error) 1400 goto destroy; 1401 return (0); 1402 1403 destroy: 1404 bus_dmamap_destroy(sc->dmat, p->map); 1405 unmap: 1406 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1407 free: 1408 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1409 return (error); 1410 } 1411 1412 int 1413 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1414 { 1415 1416 bus_dmamap_unload(sc->dmat, p->map); 1417 bus_dmamap_destroy(sc->dmat, p->map); 1418 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1419 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1420 return (0); 1421 } 1422 1423 int 1424 auich_alloc_cdata(struct auich_softc *sc) 1425 { 1426 bus_dma_segment_t seg; 1427 int error, rseg; 1428 1429 /* 1430 * Allocate the control data structure, and create and load the 1431 * DMA map for it. 1432 */ 1433 if ((error = bus_dmamem_alloc(sc->dmat, 1434 sizeof(struct auich_cdata), 1435 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1436 printf("%s: unable to allocate control data, error = %d\n", 1437 sc->sc_dev.dv_xname, error); 1438 goto fail_0; 1439 } 1440 1441 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1442 sizeof(struct auich_cdata), 1443 (caddr_t *) &sc->sc_cdata, 1444 sc->sc_dmamap_flags)) != 0) { 1445 printf("%s: unable to map control data, error = %d\n", 1446 sc->sc_dev.dv_xname, error); 1447 goto fail_1; 1448 } 1449 1450 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1451 sizeof(struct auich_cdata), 0, 0, 1452 &sc->sc_cddmamap)) != 0) { 1453 printf("%s: unable to create control data DMA map, " 1454 "error = %d\n", sc->sc_dev.dv_xname, error); 1455 goto fail_2; 1456 } 1457 1458 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1459 sc->sc_cdata, sizeof(struct auich_cdata), 1460 NULL, 0)) != 0) { 1461 printf("%s: unable tp load control data DMA map, " 1462 "error = %d\n", sc->sc_dev.dv_xname, error); 1463 goto fail_3; 1464 } 1465 1466 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1467 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1468 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1469 1470 return (0); 1471 1472 fail_3: 1473 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1474 fail_2: 1475 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1476 sizeof(struct auich_cdata)); 1477 fail_1: 1478 bus_dmamem_free(sc->dmat, &seg, rseg); 1479 fail_0: 1480 return (error); 1481 } 1482 1483 void 1484 auich_powerhook(int why, void *addr) 1485 { 1486 struct auich_softc *sc = (struct auich_softc *)addr; 1487 1488 switch (why) { 1489 case PWR_SUSPEND: 1490 case PWR_STANDBY: 1491 /* Power down */ 1492 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1493 sc->sc_suspend = why; 1494 break; 1495 1496 case PWR_RESUME: 1497 /* Wake up */ 1498 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1499 if (sc->sc_suspend == PWR_RESUME) { 1500 printf("%s: resume without suspend.\n", 1501 sc->sc_dev.dv_xname); 1502 sc->sc_suspend = why; 1503 return; 1504 } 1505 sc->sc_suspend = why; 1506 auich_reset_codec(sc); 1507 DELAY(1000); 1508 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1509 break; 1510 1511 case PWR_SOFTSUSPEND: 1512 case PWR_SOFTSTANDBY: 1513 case PWR_SOFTRESUME: 1514 break; 1515 } 1516 } 1517 1518 /* 1519 * Calibrate card (some boards are overclocked and need scaling) 1520 */ 1521 void 1522 auich_calibrate(struct auich_softc *sc) 1523 { 1524 struct timeval t1, t2; 1525 uint8_t ociv, nciv; 1526 uint64_t wait_us; 1527 uint32_t actual_48k_rate, bytes, ac97rate; 1528 void *temp_buffer; 1529 struct auich_dma *p; 1530 u_long rate; 1531 1532 /* 1533 * Grab audio from input for fixed interval and compare how 1534 * much we actually get with what we expect. Interval needs 1535 * to be sufficiently short that no interrupts are 1536 * generated. 1537 */ 1538 1539 /* Force the codec to a known state first. */ 1540 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1541 rate = 48000; 1542 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1543 &rate); 1544 1545 /* Setup a buffer */ 1546 bytes = 64000; 1547 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1548 1549 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1550 ; 1551 if (p == NULL) { 1552 printf("auich_calibrate: bad address %p\n", temp_buffer); 1553 return; 1554 } 1555 sc->pcmi.dmalist[0].base = DMAADDR(p); 1556 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1557 1558 /* 1559 * our data format is stereo, 16 bit so each sample is 4 bytes. 1560 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1561 * we're going to start recording with interrupts disabled and measure 1562 * the time taken for one block to complete. we know the block size, 1563 * we know the time in microseconds, we calculate the sample rate: 1564 * 1565 * actual_rate [bps] = bytes / (time [s] * 4) 1566 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1567 * actual_rate [Hz] = (bytes * 250000) / time [us] 1568 */ 1569 1570 /* prepare */ 1571 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1572 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1573 sc->sc_cddma + ICH_PCMI_OFF(0)); 1574 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1575 (0 - 1) & ICH_LVI_MASK); 1576 1577 /* start */ 1578 microtime(&t1); 1579 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1580 1581 /* wait */ 1582 nciv = ociv; 1583 do { 1584 microtime(&t2); 1585 if (t2.tv_sec - t1.tv_sec > 1) 1586 break; 1587 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1588 ICH_PCMI + ICH_CIV); 1589 } while (nciv == ociv); 1590 microtime(&t2); 1591 1592 /* stop */ 1593 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1594 1595 /* reset */ 1596 DELAY(100); 1597 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1598 1599 /* turn time delta into us */ 1600 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1601 1602 auich_freem(sc, temp_buffer, M_DEVBUF); 1603 1604 if (nciv == ociv) { 1605 printf("%s: ac97 link rate calibration timed out after %" 1606 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1607 return; 1608 } 1609 1610 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1611 1612 if (actual_48k_rate < 50000) 1613 ac97rate = 48000; 1614 else 1615 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1616 1617 printf("%s: measured ac97 link rate at %d Hz", 1618 sc->sc_dev.dv_xname, actual_48k_rate); 1619 if (ac97rate != actual_48k_rate) 1620 printf(", will use %d Hz", ac97rate); 1621 printf("\n"); 1622 1623 sc->sc_ac97_clock = ac97rate; 1624 } 1625
Indexes created Wed Oct 22 13:09:56 GMT 2025