auich.c revision 1.76
1 /* $NetBSD: auich.c,v 1.76 2004/11/10 14:14:09 cube Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.76 2004/11/10 14:14:09 cube Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 bus_space_tag_t iot; 179 bus_space_handle_t mix_ioh; 180 bus_space_handle_t aud_ioh; 181 bus_dma_tag_t dmat; 182 183 struct ac97_codec_if *codec_if; 184 struct ac97_host_if host_if; 185 186 /* DMA scatter-gather lists. */ 187 bus_dmamap_t sc_cddmamap; 188 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 189 190 struct auich_cdata *sc_cdata; 191 192 struct auich_ring { 193 int qptr; 194 struct auich_dmalist *dmalist; 195 196 u_int32_t start, p, end; 197 int blksize; 198 199 void (*intr)(void *); 200 void *arg; 201 } pcmo, pcmi, mici; 202 203 struct auich_dma *sc_dmas; 204 205 #ifdef DIAGNOSTIC 206 pci_chipset_tag_t sc_pc; 207 pcitag_t sc_pt; 208 #endif 209 /* SiS 7012 hack */ 210 int sc_sample_shift; 211 int sc_sts_reg; 212 /* 440MX workaround */ 213 int sc_dmamap_flags; 214 215 216 /* Power Management */ 217 void *sc_powerhook; 218 int sc_suspend; 219 220 /* sysctl */ 221 struct sysctllog *sc_log; 222 uint32_t sc_ac97_clock; 223 int sc_ac97_clock_mib; 224 }; 225 226 /* Debug */ 227 #ifdef AUICH_DEBUG 228 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 229 int auich_debug = 0xfffe; 230 #define ICH_DEBUG_CODECIO 0x0001 231 #define ICH_DEBUG_DMA 0x0002 232 #define ICH_DEBUG_INTR 0x0004 233 #else 234 #define DPRINTF(x,y) /* nothing */ 235 #endif 236 237 int auich_match(struct device *, struct cfdata *, void *); 238 void auich_attach(struct device *, struct device *, void *); 239 int auich_intr(void *); 240 241 CFATTACH_DECL(auich, sizeof(struct auich_softc), 242 auich_match, auich_attach, NULL, NULL); 243 244 int auich_open(void *, int); 245 void auich_close(void *); 246 int auich_query_encoding(void *, struct audio_encoding *); 247 int auich_set_params(void *, int, int, struct audio_params *, 248 struct audio_params *); 249 int auich_round_blocksize(void *, int); 250 int auich_halt_output(void *); 251 int auich_halt_input(void *); 252 int auich_getdev(void *, struct audio_device *); 253 int auich_set_port(void *, mixer_ctrl_t *); 254 int auich_get_port(void *, mixer_ctrl_t *); 255 int auich_query_devinfo(void *, mixer_devinfo_t *); 256 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 257 void auich_freem(void *, void *, struct malloc_type *); 258 size_t auich_round_buffersize(void *, int, size_t); 259 paddr_t auich_mappage(void *, void *, off_t, int); 260 int auich_get_props(void *); 261 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 262 void *, struct audio_params *); 263 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 264 void *, struct audio_params *); 265 266 int auich_alloc_cdata(struct auich_softc *); 267 268 int auich_allocmem(struct auich_softc *, size_t, size_t, 269 struct auich_dma *); 270 int auich_freemem(struct auich_softc *, struct auich_dma *); 271 272 void auich_powerhook(int, void *); 273 int auich_set_rate(struct auich_softc *, int, u_long); 274 static int auich_sysctl_verify(SYSCTLFN_ARGS); 275 void auich_finish_attach(struct device *); 276 void auich_calibrate(struct auich_softc *); 277 278 279 const struct audio_hw_if auich_hw_if = { 280 auich_open, 281 auich_close, 282 NULL, /* drain */ 283 auich_query_encoding, 284 auich_set_params, 285 auich_round_blocksize, 286 NULL, /* commit_setting */ 287 NULL, /* init_output */ 288 NULL, /* init_input */ 289 NULL, /* start_output */ 290 NULL, /* start_input */ 291 auich_halt_output, 292 auich_halt_input, 293 NULL, /* speaker_ctl */ 294 auich_getdev, 295 NULL, /* getfd */ 296 auich_set_port, 297 auich_get_port, 298 auich_query_devinfo, 299 auich_allocm, 300 auich_freem, 301 auich_round_buffersize, 302 auich_mappage, 303 auich_get_props, 304 auich_trigger_output, 305 auich_trigger_input, 306 NULL, /* dev_ioctl */ 307 }; 308 309 int auich_attach_codec(void *, struct ac97_codec_if *); 310 int auich_read_codec(void *, u_int8_t, u_int16_t *); 311 int auich_write_codec(void *, u_int8_t, u_int16_t); 312 int auich_reset_codec(void *); 313 314 static const struct auich_devtype { 315 int vendor; 316 int product; 317 const char *name; 318 const char *shortname; /* must be less than 11 characters */ 319 } auich_devices[] = { 320 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 321 "i82801AA (ICH) AC-97 Audio", "ICH" }, 322 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 323 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 324 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 325 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 326 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 327 "i82440MX AC-97 Audio", "440MX" }, 328 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 329 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 330 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 331 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 332 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 333 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 334 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 335 "SiS 7012 AC-97 Audio", "SiS7012" }, 336 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 337 "nForce MCP AC-97 Audio", "nForce" }, 338 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 339 "nForce2 MCP-T AC-97 Audio", "nForce2" }, 340 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 341 "nForce3 MCP-T AC-97 Audio", "nForce3" }, 342 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_MCPT_AC, 343 "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 344 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 345 "AMD768 AC-97 Audio", "AMD768" }, 346 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 347 "AMD8111 AC-97 Audio", "AMD8111" }, 348 { 0, 0, 349 NULL, NULL }, 350 }; 351 352 static const struct auich_devtype * 353 auich_lookup(struct pci_attach_args *pa) 354 { 355 const struct auich_devtype *d; 356 357 for (d = auich_devices; d->name != NULL; d++) { 358 if (PCI_VENDOR(pa->pa_id) == d->vendor 359 && PCI_PRODUCT(pa->pa_id) == d->product) 360 return (d); 361 } 362 363 return (NULL); 364 } 365 366 int 367 auich_match(struct device *parent, struct cfdata *match, void *aux) 368 { 369 struct pci_attach_args *pa = aux; 370 371 if (auich_lookup(pa) != NULL) 372 return (1); 373 374 return (0); 375 } 376 377 void 378 auich_attach(struct device *parent, struct device *self, void *aux) 379 { 380 struct auich_softc *sc = (struct auich_softc *)self; 381 struct pci_attach_args *pa = aux; 382 pci_intr_handle_t ih; 383 bus_size_t mix_size, aud_size; 384 pcireg_t v; 385 const char *intrstr; 386 const struct auich_devtype *d; 387 struct sysctlnode *node; 388 int err, node_mib; 389 390 aprint_naive(": Audio controller\n"); 391 392 d = auich_lookup(pa); 393 if (d == NULL) 394 panic("auich_attach: impossible"); 395 396 #ifdef DIAGNOSTIC 397 sc->sc_pc = pa->pa_pc; 398 sc->sc_pt = pa->pa_tag; 399 #endif 400 401 aprint_normal(": %s\n", d->name); 402 403 if ((d->vendor == PCI_VENDOR_INTEL 404 && d->product == PCI_PRODUCT_INTEL_82801DB_AC) 405 || (d->vendor == PCI_VENDOR_INTEL 406 && d->product == PCI_PRODUCT_INTEL_82801EB_AC)) { 407 /* 408 * Use native mode for ICH4/ICH5 409 */ 410 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 411 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 412 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 413 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 414 v | ICH_CFG_IOSE); 415 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 416 0, &sc->iot, &sc->mix_ioh, NULL, 417 &mix_size)) { 418 aprint_error("%s: can't map codec i/o space\n", 419 sc->sc_dev.dv_xname); 420 return; 421 } 422 } 423 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 424 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 425 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 426 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 427 v | ICH_CFG_IOSE); 428 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 429 0, &sc->iot, &sc->aud_ioh, NULL, 430 &aud_size)) { 431 aprint_error("%s: can't map device i/o space\n", 432 sc->sc_dev.dv_xname); 433 return; 434 } 435 } 436 } else { 437 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 438 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 439 aprint_error("%s: can't map codec i/o space\n", 440 sc->sc_dev.dv_xname); 441 return; 442 } 443 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 444 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 445 aprint_error("%s: can't map device i/o space\n", 446 sc->sc_dev.dv_xname); 447 return; 448 } 449 } 450 sc->dmat = pa->pa_dmat; 451 452 /* enable bus mastering */ 453 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 454 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 455 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 456 457 /* Map and establish the interrupt. */ 458 if (pci_intr_map(pa, &ih)) { 459 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 460 return; 461 } 462 intrstr = pci_intr_string(pa->pa_pc, ih); 463 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 464 auich_intr, sc); 465 if (sc->sc_ih == NULL) { 466 aprint_error("%s: can't establish interrupt", 467 sc->sc_dev.dv_xname); 468 if (intrstr != NULL) 469 aprint_normal(" at %s", intrstr); 470 aprint_normal("\n"); 471 return; 472 } 473 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 474 475 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 476 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 477 "0x%02x", PCI_REVISION(pa->pa_class)); 478 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 479 480 /* SiS 7012 needs special handling */ 481 if (d->vendor == PCI_VENDOR_SIS 482 && d->product == PCI_PRODUCT_SIS_7012_AC) { 483 sc->sc_sts_reg = ICH_PICB; 484 sc->sc_sample_shift = 0; 485 } else { 486 sc->sc_sts_reg = ICH_STS; 487 sc->sc_sample_shift = 1; 488 } 489 490 /* Workaround for a 440MX B-stepping erratum */ 491 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 492 if (d->vendor == PCI_VENDOR_INTEL 493 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 494 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 495 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 496 } 497 498 /* Set up DMA lists. */ 499 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 500 auich_alloc_cdata(sc); 501 502 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 503 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 504 505 sc->host_if.arg = sc; 506 sc->host_if.attach = auich_attach_codec; 507 sc->host_if.read = auich_read_codec; 508 sc->host_if.write = auich_write_codec; 509 sc->host_if.reset = auich_reset_codec; 510 511 if (ac97_attach(&sc->host_if) != 0) 512 return; 513 514 /* Watch for power change */ 515 sc->sc_suspend = PWR_RESUME; 516 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 517 518 config_interrupts(self, auich_finish_attach); 519 520 /* sysctl setup */ 521 if (AC97_IS_FIXED_RATE(sc->codec_if)) 522 return; 523 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 524 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 525 CTL_HW, CTL_EOL); 526 if (err != 0) 527 goto sysctl_err; 528 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 529 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 530 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 531 if (err != 0) 532 goto sysctl_err; 533 node_mib = node->sysctl_num; 534 /* passing the sc address instead of &sc->sc_ac97_clock */ 535 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 536 CTLTYPE_INT, "ac97rate", 537 SYSCTL_DESCR("AC'97 codec link rate"), 538 auich_sysctl_verify, 0, sc, 0, 539 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 540 if (err != 0) 541 goto sysctl_err; 542 sc->sc_ac97_clock_mib = node->sysctl_num; 543 544 return; 545 546 sysctl_err: 547 printf("%s: failed to add sysctl nodes. (%d)\n", 548 sc->sc_dev.dv_xname, err); 549 return; /* failure of sysctl is not fatal. */ 550 } 551 552 #if 0 553 int 554 auich_detach(struct device *self, int flags) 555 { 556 struct auich_softc *sc; 557 558 sc = (struct auich_softc *)self; 559 /* sysctl */ 560 sysctl_teardown(&sc->sc_log); 561 /* audio */ 562 if (sc->sc_audiodev != NULL) 563 config_detach(sc->sc_audiodev, flags); 564 /* XXX ac97 */ 565 /* XXX memory */ 566 return 0; 567 } 568 #endif 569 570 static int 571 auich_sysctl_verify(SYSCTLFN_ARGS) 572 { 573 int error, tmp; 574 struct sysctlnode node; 575 struct auich_softc *sc; 576 577 node = *rnode; 578 sc = rnode->sysctl_data; 579 tmp = sc->sc_ac97_clock; 580 node.sysctl_data = &tmp; 581 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 582 if (error || newp == NULL) 583 return error; 584 585 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 586 if (tmp < 48000 || tmp > 96000) 587 return EINVAL; 588 sc->sc_ac97_clock = tmp; 589 } 590 591 return 0; 592 } 593 594 void 595 auich_finish_attach(struct device *self) 596 { 597 struct auich_softc *sc = (void *)self; 598 599 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 600 auich_calibrate(sc); 601 602 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 603 } 604 605 #define ICH_CODECIO_INTERVAL 10 606 int 607 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 608 { 609 struct auich_softc *sc = v; 610 int i; 611 uint32_t status; 612 613 /* wait for an access semaphore */ 614 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 615 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 616 DELAY(ICH_CODECIO_INTERVAL)); 617 618 if (i > 0) { 619 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 620 DPRINTF(ICH_DEBUG_CODECIO, 621 ("auich_read_codec(%x, %x)\n", reg, *val)); 622 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 623 if (status & ICH_RCS) { 624 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 625 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 626 *val = 0xffff; 627 } 628 return 0; 629 } else { 630 DPRINTF(ICH_DEBUG_CODECIO, 631 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 632 return -1; 633 } 634 } 635 636 int 637 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 638 { 639 struct auich_softc *sc = v; 640 int i; 641 642 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 643 /* wait for an access semaphore */ 644 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 645 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 646 DELAY(ICH_CODECIO_INTERVAL)); 647 648 if (i > 0) { 649 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 650 return 0; 651 } else { 652 DPRINTF(ICH_DEBUG_CODECIO, 653 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 654 return -1; 655 } 656 } 657 658 int 659 auich_attach_codec(void *v, struct ac97_codec_if *cif) 660 { 661 struct auich_softc *sc = v; 662 663 sc->codec_if = cif; 664 return 0; 665 } 666 667 int 668 auich_reset_codec(void *v) 669 { 670 struct auich_softc *sc = v; 671 int i; 672 uint32_t control, status; 673 674 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 675 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 676 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 677 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 678 679 for (i = 500000; i >= 0; i--) { 680 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 681 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 682 break; 683 DELAY(1); 684 } 685 if (i <= 0) { 686 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 687 return ETIMEDOUT; 688 } 689 #ifdef DEBUG 690 if (status & ICH_SCR) 691 printf("%s: The 2nd codec is ready.\n", 692 sc->sc_dev.dv_xname); 693 if (status & ICH_S2CR) 694 printf("%s: The 3rd codec is ready.\n", 695 sc->sc_dev.dv_xname); 696 #endif 697 return 0; 698 } 699 700 int 701 auich_open(void *v, int flags) 702 { 703 return 0; 704 } 705 706 void 707 auich_close(void *v) 708 { 709 } 710 711 int 712 auich_query_encoding(void *v, struct audio_encoding *aep) 713 { 714 static const struct auich_encoding { 715 const char *name; 716 int encoding, precision, flags; 717 } *p, auich_encoding[] = { 718 {AudioEulinear, AUDIO_ENCODING_ULINEAR, 719 8, AUDIO_ENCODINGFLAG_EMULATED}, 720 {AudioEmulaw, AUDIO_ENCODING_ULAW, 721 8, AUDIO_ENCODINGFLAG_EMULATED}, 722 {AudioEalaw, AUDIO_ENCODING_ALAW, 723 8, AUDIO_ENCODINGFLAG_EMULATED}, 724 {AudioEslinear, AUDIO_ENCODING_SLINEAR, 725 8, AUDIO_ENCODINGFLAG_EMULATED}, 726 {AudioEslinear_le, AUDIO_ENCODING_SLINEAR_LE, 727 16, 0}, 728 {AudioEulinear_le, AUDIO_ENCODING_ULINEAR_LE, 729 16, AUDIO_ENCODINGFLAG_EMULATED}, 730 {AudioEslinear_be, AUDIO_ENCODING_SLINEAR_BE, 731 16, AUDIO_ENCODINGFLAG_EMULATED}, 732 {AudioEulinear_be, AUDIO_ENCODING_ULINEAR_BE, 733 16, AUDIO_ENCODINGFLAG_EMULATED}, 734 }; 735 736 if (aep->index >= 8) 737 return (EINVAL); 738 739 p = &auich_encoding[aep->index]; 740 strcpy(aep->name, p->name); 741 aep->encoding = p->encoding; 742 aep->precision = p->precision; 743 aep->flags = p->flags; 744 return (0); 745 } 746 747 int 748 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 749 { 750 int ret; 751 u_long ratetmp; 752 753 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 754 ratetmp = srate; 755 if (mode == AUMODE_RECORD) 756 return sc->codec_if->vtbl->set_rate(sc->codec_if, 757 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 758 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 759 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 760 if (ret) 761 return ret; 762 ratetmp = srate; 763 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 764 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 765 if (ret) 766 return ret; 767 ratetmp = srate; 768 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 769 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 770 return ret; 771 } 772 773 int 774 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 775 struct audio_params *rec) 776 { 777 struct auich_softc *sc = v; 778 struct audio_params *p; 779 int mode; 780 u_int32_t control; 781 782 for (mode = AUMODE_RECORD; mode != -1; 783 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 784 if ((setmode & mode) == 0) 785 continue; 786 787 p = mode == AUMODE_PLAY ? play : rec; 788 if (p == NULL) 789 continue; 790 791 if (p->sample_rate < 8000 || 792 p->sample_rate > 48000) 793 return (EINVAL); 794 795 if (p->precision == 8) 796 p->factor = 2; 797 else 798 p->factor = 1; 799 800 p->sw_code = NULL; 801 /* setup hardware formats */ 802 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 803 p->hw_precision = 16; 804 805 if (mode == AUMODE_RECORD) { 806 if (p->channels < 1 || p->channels > 2) 807 return EINVAL; 808 } else { 809 switch (p->channels) { 810 case 1: 811 break; 812 case 2: 813 break; 814 case 4: 815 if (!AC97_IS_4CH(sc->codec_if)) 816 return EINVAL; 817 break; 818 case 6: 819 if (!AC97_IS_6CH(sc->codec_if)) 820 return EINVAL; 821 break; 822 default: 823 return EINVAL; 824 } 825 } 826 /* If monaural is requested, aurateconv expands a monaural 827 * stream to stereo. */ 828 if (p->channels == 1) 829 p->hw_channels = 2; 830 831 switch (p->encoding) { 832 case AUDIO_ENCODING_SLINEAR_BE: 833 if (p->precision == 16) { 834 p->sw_code = swap_bytes; 835 } else { 836 if (mode == AUMODE_PLAY) 837 p->sw_code = linear8_to_linear16_le; 838 else 839 p->sw_code = linear16_to_linear8_le; 840 } 841 break; 842 843 case AUDIO_ENCODING_SLINEAR_LE: 844 if (p->precision != 16) { 845 if (mode == AUMODE_PLAY) 846 p->sw_code = linear8_to_linear16_le; 847 else 848 p->sw_code = linear16_to_linear8_le; 849 } 850 break; 851 852 case AUDIO_ENCODING_ULINEAR_BE: 853 if (p->precision == 16) { 854 if (mode == AUMODE_PLAY) 855 p->sw_code = 856 swap_bytes_change_sign16_le; 857 else 858 p->sw_code = 859 change_sign16_swap_bytes_le; 860 } else { 861 if (mode == AUMODE_PLAY) 862 p->sw_code = 863 ulinear8_to_slinear16_le; 864 else 865 p->sw_code = 866 slinear16_to_ulinear8_le; 867 } 868 break; 869 870 case AUDIO_ENCODING_ULINEAR_LE: 871 if (p->precision == 16) { 872 p->sw_code = change_sign16_le; 873 } else { 874 if (mode == AUMODE_PLAY) 875 p->sw_code = 876 ulinear8_to_slinear16_le; 877 else 878 p->sw_code = 879 slinear16_to_ulinear8_le; 880 } 881 break; 882 883 case AUDIO_ENCODING_ULAW: 884 if (mode == AUMODE_PLAY) { 885 p->sw_code = mulaw_to_slinear16_le; 886 } else { 887 p->sw_code = slinear16_to_mulaw_le; 888 } 889 break; 890 891 case AUDIO_ENCODING_ALAW: 892 if (mode == AUMODE_PLAY) { 893 p->sw_code = alaw_to_slinear16_le; 894 } else { 895 p->sw_code = slinear16_to_alaw_le; 896 } 897 break; 898 899 default: 900 return (EINVAL); 901 } 902 903 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 904 p->hw_sample_rate = AC97_SINGLE_RATE; 905 /* If hw_sample_rate is changed, aurateconv works. */ 906 } else { 907 if (auich_set_rate(sc, mode, p->sample_rate)) 908 return EINVAL; 909 } 910 if (mode == AUMODE_PLAY) { 911 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 912 control &= ~ICH_PCM246_MASK; 913 if (p->channels == 4) { 914 control |= ICH_PCM4; 915 } else if (p->channels == 6) { 916 control |= ICH_PCM6; 917 } 918 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 919 } 920 } 921 922 return (0); 923 } 924 925 int 926 auich_round_blocksize(void *v, int blk) 927 { 928 929 return (blk & ~0x3f); /* keep good alignment */ 930 } 931 932 int 933 auich_halt_output(void *v) 934 { 935 struct auich_softc *sc = v; 936 937 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 938 939 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 940 sc->pcmo.intr = NULL; 941 942 return (0); 943 } 944 945 int 946 auich_halt_input(void *v) 947 { 948 struct auich_softc *sc = v; 949 950 DPRINTF(ICH_DEBUG_DMA, 951 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 952 953 /* XXX halt both unless known otherwise */ 954 955 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 956 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 957 sc->pcmi.intr = NULL; 958 959 return (0); 960 } 961 962 int 963 auich_getdev(void *v, struct audio_device *adp) 964 { 965 struct auich_softc *sc = v; 966 967 *adp = sc->sc_audev; 968 return (0); 969 } 970 971 int 972 auich_set_port(void *v, mixer_ctrl_t *cp) 973 { 974 struct auich_softc *sc = v; 975 976 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 977 } 978 979 int 980 auich_get_port(void *v, mixer_ctrl_t *cp) 981 { 982 struct auich_softc *sc = v; 983 984 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 985 } 986 987 int 988 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 989 { 990 struct auich_softc *sc = v; 991 992 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 993 } 994 995 void * 996 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 997 int flags) 998 { 999 struct auich_softc *sc = v; 1000 struct auich_dma *p; 1001 int error; 1002 1003 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1004 return (NULL); 1005 1006 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1007 if (p == NULL) 1008 return (NULL); 1009 1010 error = auich_allocmem(sc, size, 0, p); 1011 if (error) { 1012 free(p, pool); 1013 return (NULL); 1014 } 1015 1016 p->next = sc->sc_dmas; 1017 sc->sc_dmas = p; 1018 1019 return (KERNADDR(p)); 1020 } 1021 1022 void 1023 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1024 { 1025 struct auich_softc *sc = v; 1026 struct auich_dma *p, **pp; 1027 1028 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1029 if (KERNADDR(p) == ptr) { 1030 auich_freemem(sc, p); 1031 *pp = p->next; 1032 free(p, pool); 1033 return; 1034 } 1035 } 1036 } 1037 1038 size_t 1039 auich_round_buffersize(void *v, int direction, size_t size) 1040 { 1041 1042 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1043 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1044 1045 return size; 1046 } 1047 1048 paddr_t 1049 auich_mappage(void *v, void *mem, off_t off, int prot) 1050 { 1051 struct auich_softc *sc = v; 1052 struct auich_dma *p; 1053 1054 if (off < 0) 1055 return (-1); 1056 1057 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1058 ; 1059 if (!p) 1060 return (-1); 1061 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1062 off, prot, BUS_DMA_WAITOK)); 1063 } 1064 1065 int 1066 auich_get_props(void *v) 1067 { 1068 struct auich_softc *sc = v; 1069 int props; 1070 1071 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1072 /* 1073 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1074 * rate because of aurateconv. Applications can't know what rate the 1075 * device can process in the case of mmap(). 1076 */ 1077 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 1078 props |= AUDIO_PROP_MMAP; 1079 return props; 1080 } 1081 1082 int 1083 auich_intr(void *v) 1084 { 1085 struct auich_softc *sc = v; 1086 int ret = 0, gsts; 1087 1088 #ifdef DIAGNOSTIC 1089 int csts; 1090 #endif 1091 1092 #ifdef DIAGNOSTIC 1093 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1094 if (csts & PCI_STATUS_MASTER_ABORT) { 1095 printf("auich_intr: PCI master abort\n"); 1096 } 1097 #endif 1098 1099 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 1100 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1101 1102 if (gsts & ICH_POINT) { 1103 int sts; 1104 1105 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1106 ICH_PCMO + sc->sc_sts_reg); 1107 DPRINTF(ICH_DEBUG_INTR, 1108 ("auich_intr: osts=0x%x\n", sts)); 1109 1110 if (sts & ICH_FIFOE) 1111 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1112 1113 if (sts & ICH_BCIS) { 1114 struct auich_dmalist *q; 1115 int blksize, qptr, i; 1116 1117 blksize = sc->pcmo.blksize; 1118 qptr = sc->pcmo.qptr; 1119 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1120 ICH_PCMO + ICH_CIV); 1121 1122 while (qptr != i) { 1123 q = &sc->pcmo.dmalist[qptr]; 1124 1125 q->base = sc->pcmo.p; 1126 q->len = (blksize >> sc->sc_sample_shift) | 1127 ICH_DMAF_IOC; 1128 DPRINTF(ICH_DEBUG_INTR, 1129 ("auich_intr: %p, %p = %x @ 0x%x\n", 1130 &sc->pcmo.dmalist[i], q, q->len, q->base)); 1131 1132 sc->pcmo.p += blksize; 1133 if (sc->pcmo.p >= sc->pcmo.end) 1134 sc->pcmo.p = sc->pcmo.start; 1135 1136 qptr = (qptr + 1) & ICH_LVI_MASK; 1137 if (sc->pcmo.intr) 1138 sc->pcmo.intr(sc->pcmo.arg); 1139 } 1140 1141 sc->pcmo.qptr = qptr; 1142 bus_space_write_1(sc->iot, sc->aud_ioh, 1143 ICH_PCMO + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1144 } 1145 1146 /* int ack */ 1147 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1148 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1149 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1150 ret++; 1151 } 1152 1153 if (gsts & ICH_PIINT) { 1154 int sts; 1155 1156 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1157 ICH_PCMI + sc->sc_sts_reg); 1158 DPRINTF(ICH_DEBUG_INTR, 1159 ("auich_intr: ists=0x%x\n", sts)); 1160 1161 if (sts & ICH_FIFOE) 1162 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1163 1164 if (sts & ICH_BCIS) { 1165 struct auich_dmalist *q; 1166 int blksize, qptr, i; 1167 1168 blksize = sc->pcmi.blksize; 1169 qptr = sc->pcmi.qptr; 1170 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1171 ICH_PCMI + ICH_CIV); 1172 1173 while (qptr != i) { 1174 q = &sc->pcmi.dmalist[qptr]; 1175 1176 q->base = sc->pcmi.p; 1177 q->len = (blksize >> sc->sc_sample_shift) | 1178 ICH_DMAF_IOC; 1179 DPRINTF(ICH_DEBUG_INTR, 1180 ("auich_intr: %p, %p = %x @ 0x%x\n", 1181 &sc->pcmi.dmalist[i], q, q->len, q->base)); 1182 1183 sc->pcmi.p += blksize; 1184 if (sc->pcmi.p >= sc->pcmi.end) 1185 sc->pcmi.p = sc->pcmi.start; 1186 1187 qptr = (qptr + 1) & ICH_LVI_MASK; 1188 if (sc->pcmi.intr) 1189 sc->pcmi.intr(sc->pcmi.arg); 1190 } 1191 1192 sc->pcmi.qptr = qptr; 1193 bus_space_write_1(sc->iot, sc->aud_ioh, 1194 ICH_PCMI + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1195 } 1196 1197 /* int ack */ 1198 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1199 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1200 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1201 ret++; 1202 } 1203 1204 if (gsts & ICH_MIINT) { 1205 int sts; 1206 1207 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1208 ICH_MICI + sc->sc_sts_reg); 1209 DPRINTF(ICH_DEBUG_INTR, 1210 ("auich_intr: ists=0x%x\n", sts)); 1211 1212 if (sts & ICH_FIFOE) 1213 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1214 1215 /* TODO mic input DMA */ 1216 1217 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1218 } 1219 1220 return ret; 1221 } 1222 1223 int 1224 auich_trigger_output(void *v, void *start, void *end, int blksize, 1225 void (*intr)(void *), void *arg, struct audio_params *param) 1226 { 1227 struct auich_softc *sc = v; 1228 struct auich_dmalist *q; 1229 struct auich_dma *p; 1230 size_t size; 1231 int qptr; 1232 #ifdef DIAGNOSTIC 1233 int csts; 1234 #endif 1235 1236 DPRINTF(ICH_DEBUG_DMA, 1237 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1238 start, end, blksize, intr, arg, param)); 1239 1240 sc->pcmo.intr = intr; 1241 sc->pcmo.arg = arg; 1242 #ifdef DIAGNOSTIC 1243 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1244 if (csts & PCI_STATUS_MASTER_ABORT) { 1245 printf("auich_trigger_output: PCI master abort\n"); 1246 } 1247 #endif 1248 1249 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1250 ; 1251 if (!p) { 1252 printf("auich_trigger_output: bad addr %p\n", start); 1253 return (EINVAL); 1254 } 1255 1256 size = (size_t)((caddr_t)end - (caddr_t)start); 1257 1258 /* 1259 * The logic behind this is: 1260 * setup one buffer to play, then LVI dump out the rest 1261 * to the scatter-gather chain. 1262 */ 1263 sc->pcmo.start = DMAADDR(p); 1264 sc->pcmo.p = sc->pcmo.start; 1265 sc->pcmo.end = sc->pcmo.start + size; 1266 sc->pcmo.blksize = blksize; 1267 1268 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1269 q = &sc->pcmo.dmalist[qptr]; 1270 1271 q->base = sc->pcmo.p; 1272 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1273 1274 sc->pcmo.p += blksize; 1275 if (sc->pcmo.p >= sc->pcmo.end) 1276 sc->pcmo.p = sc->pcmo.start; 1277 } 1278 1279 sc->pcmo.qptr = qptr = 0; 1280 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1281 (qptr - 1) & ICH_LVI_MASK); 1282 1283 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1284 sc->sc_cddma + ICH_PCMO_OFF(0)); 1285 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1286 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1287 1288 return (0); 1289 } 1290 1291 int 1292 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1293 void *v; 1294 void *start, *end; 1295 int blksize; 1296 void (*intr)(void *); 1297 void *arg; 1298 struct audio_params *param; 1299 { 1300 struct auich_softc *sc = v; 1301 struct auich_dmalist *q; 1302 struct auich_dma *p; 1303 size_t size; 1304 int qptr; 1305 #ifdef DIAGNOSTIC 1306 int csts; 1307 #endif 1308 1309 DPRINTF(ICH_DEBUG_DMA, 1310 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1311 start, end, blksize, intr, arg, param)); 1312 1313 sc->pcmi.intr = intr; 1314 sc->pcmi.arg = arg; 1315 1316 #ifdef DIAGNOSTIC 1317 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1318 if (csts & PCI_STATUS_MASTER_ABORT) { 1319 printf("auich_trigger_input: PCI master abort\n"); 1320 } 1321 #endif 1322 1323 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1324 ; 1325 if (!p) { 1326 printf("auich_trigger_input: bad addr %p\n", start); 1327 return (EINVAL); 1328 } 1329 1330 size = (size_t)((caddr_t)end - (caddr_t)start); 1331 1332 /* 1333 * The logic behind this is: 1334 * setup one buffer to play, then LVI dump out the rest 1335 * to the scatter-gather chain. 1336 */ 1337 sc->pcmi.start = DMAADDR(p); 1338 sc->pcmi.p = sc->pcmi.start; 1339 sc->pcmi.end = sc->pcmi.start + size; 1340 sc->pcmi.blksize = blksize; 1341 1342 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1343 q = &sc->pcmi.dmalist[qptr]; 1344 1345 q->base = sc->pcmi.p; 1346 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1347 1348 sc->pcmi.p += blksize; 1349 if (sc->pcmi.p >= sc->pcmi.end) 1350 sc->pcmi.p = sc->pcmi.start; 1351 } 1352 1353 sc->pcmi.qptr = qptr = 0; 1354 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1355 (qptr - 1) & ICH_LVI_MASK); 1356 1357 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1358 sc->sc_cddma + ICH_PCMI_OFF(0)); 1359 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1360 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1361 1362 return (0); 1363 } 1364 1365 int 1366 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1367 struct auich_dma *p) 1368 { 1369 int error; 1370 1371 p->size = size; 1372 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1373 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1374 &p->nsegs, BUS_DMA_NOWAIT); 1375 if (error) 1376 return (error); 1377 1378 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1379 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1380 if (error) 1381 goto free; 1382 1383 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1384 0, BUS_DMA_NOWAIT, &p->map); 1385 if (error) 1386 goto unmap; 1387 1388 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1389 BUS_DMA_NOWAIT); 1390 if (error) 1391 goto destroy; 1392 return (0); 1393 1394 destroy: 1395 bus_dmamap_destroy(sc->dmat, p->map); 1396 unmap: 1397 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1398 free: 1399 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1400 return (error); 1401 } 1402 1403 int 1404 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1405 { 1406 1407 bus_dmamap_unload(sc->dmat, p->map); 1408 bus_dmamap_destroy(sc->dmat, p->map); 1409 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1410 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1411 return (0); 1412 } 1413 1414 int 1415 auich_alloc_cdata(struct auich_softc *sc) 1416 { 1417 bus_dma_segment_t seg; 1418 int error, rseg; 1419 1420 /* 1421 * Allocate the control data structure, and create and load the 1422 * DMA map for it. 1423 */ 1424 if ((error = bus_dmamem_alloc(sc->dmat, 1425 sizeof(struct auich_cdata), 1426 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1427 printf("%s: unable to allocate control data, error = %d\n", 1428 sc->sc_dev.dv_xname, error); 1429 goto fail_0; 1430 } 1431 1432 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1433 sizeof(struct auich_cdata), 1434 (caddr_t *) &sc->sc_cdata, 1435 sc->sc_dmamap_flags)) != 0) { 1436 printf("%s: unable to map control data, error = %d\n", 1437 sc->sc_dev.dv_xname, error); 1438 goto fail_1; 1439 } 1440 1441 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1442 sizeof(struct auich_cdata), 0, 0, 1443 &sc->sc_cddmamap)) != 0) { 1444 printf("%s: unable to create control data DMA map, " 1445 "error = %d\n", sc->sc_dev.dv_xname, error); 1446 goto fail_2; 1447 } 1448 1449 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1450 sc->sc_cdata, sizeof(struct auich_cdata), 1451 NULL, 0)) != 0) { 1452 printf("%s: unable tp load control data DMA map, " 1453 "error = %d\n", sc->sc_dev.dv_xname, error); 1454 goto fail_3; 1455 } 1456 1457 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1458 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1459 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1460 1461 return (0); 1462 1463 fail_3: 1464 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1465 fail_2: 1466 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1467 sizeof(struct auich_cdata)); 1468 fail_1: 1469 bus_dmamem_free(sc->dmat, &seg, rseg); 1470 fail_0: 1471 return (error); 1472 } 1473 1474 void 1475 auich_powerhook(int why, void *addr) 1476 { 1477 struct auich_softc *sc = (struct auich_softc *)addr; 1478 1479 switch (why) { 1480 case PWR_SUSPEND: 1481 case PWR_STANDBY: 1482 /* Power down */ 1483 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1484 sc->sc_suspend = why; 1485 break; 1486 1487 case PWR_RESUME: 1488 /* Wake up */ 1489 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1490 if (sc->sc_suspend == PWR_RESUME) { 1491 printf("%s: resume without suspend.\n", 1492 sc->sc_dev.dv_xname); 1493 sc->sc_suspend = why; 1494 return; 1495 } 1496 sc->sc_suspend = why; 1497 auich_reset_codec(sc); 1498 DELAY(1000); 1499 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1500 break; 1501 1502 case PWR_SOFTSUSPEND: 1503 case PWR_SOFTSTANDBY: 1504 case PWR_SOFTRESUME: 1505 break; 1506 } 1507 } 1508 1509 /* 1510 * Calibrate card (some boards are overclocked and need scaling) 1511 */ 1512 void 1513 auich_calibrate(struct auich_softc *sc) 1514 { 1515 struct timeval t1, t2; 1516 uint8_t ociv, nciv; 1517 uint64_t wait_us; 1518 uint32_t actual_48k_rate, bytes, ac97rate; 1519 void *temp_buffer; 1520 struct auich_dma *p; 1521 u_long rate; 1522 1523 /* 1524 * Grab audio from input for fixed interval and compare how 1525 * much we actually get with what we expect. Interval needs 1526 * to be sufficiently short that no interrupts are 1527 * generated. 1528 */ 1529 1530 /* Force the codec to a known state first. */ 1531 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1532 rate = sc->sc_ac97_clock = 48000; 1533 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1534 &rate); 1535 1536 /* Setup a buffer */ 1537 bytes = 64000; 1538 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1539 1540 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1541 ; 1542 if (p == NULL) { 1543 printf("auich_calibrate: bad address %p\n", temp_buffer); 1544 return; 1545 } 1546 sc->pcmi.dmalist[0].base = DMAADDR(p); 1547 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1548 1549 /* 1550 * our data format is stereo, 16 bit so each sample is 4 bytes. 1551 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1552 * we're going to start recording with interrupts disabled and measure 1553 * the time taken for one block to complete. we know the block size, 1554 * we know the time in microseconds, we calculate the sample rate: 1555 * 1556 * actual_rate [bps] = bytes / (time [s] * 4) 1557 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1558 * actual_rate [Hz] = (bytes * 250000) / time [us] 1559 */ 1560 1561 /* prepare */ 1562 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1563 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1564 sc->sc_cddma + ICH_PCMI_OFF(0)); 1565 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1566 (0 - 1) & ICH_LVI_MASK); 1567 1568 /* start */ 1569 microtime(&t1); 1570 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1571 1572 /* wait */ 1573 nciv = ociv; 1574 do { 1575 microtime(&t2); 1576 if (t2.tv_sec - t1.tv_sec > 1) 1577 break; 1578 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1579 ICH_PCMI + ICH_CIV); 1580 } while (nciv == ociv); 1581 microtime(&t2); 1582 1583 /* stop */ 1584 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1585 1586 /* reset */ 1587 DELAY(100); 1588 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1589 1590 /* turn time delta into us */ 1591 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1592 1593 auich_freem(sc, temp_buffer, M_DEVBUF); 1594 1595 if (nciv == ociv) { 1596 printf("%s: ac97 link rate calibration timed out after %" 1597 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1598 return; 1599 } 1600 1601 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1602 1603 if (actual_48k_rate < 50000) 1604 ac97rate = 48000; 1605 else 1606 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1607 1608 printf("%s: measured ac97 link rate at %d Hz", 1609 sc->sc_dev.dv_xname, actual_48k_rate); 1610 if (ac97rate != actual_48k_rate) 1611 printf(", will use %d Hz", ac97rate); 1612 printf("\n"); 1613 1614 sc->sc_ac97_clock = ac97rate; 1615 } 1616
Indexes created Thu Oct 23 18:09:57 GMT 2025