auich.c revision 1.78
1 /* $NetBSD: auich.c,v 1.78 2004/11/10 17:22:25 cube Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.78 2004/11/10 17:22:25 cube Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 bus_space_tag_t iot; 179 bus_space_handle_t mix_ioh; 180 bus_space_handle_t aud_ioh; 181 bus_dma_tag_t dmat; 182 183 struct ac97_codec_if *codec_if; 184 struct ac97_host_if host_if; 185 186 /* DMA scatter-gather lists. */ 187 bus_dmamap_t sc_cddmamap; 188 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 189 190 struct auich_cdata *sc_cdata; 191 192 struct auich_ring { 193 int qptr; 194 struct auich_dmalist *dmalist; 195 196 u_int32_t start, p, end; 197 int blksize; 198 199 void (*intr)(void *); 200 void *arg; 201 } pcmo, pcmi, mici; 202 203 struct auich_dma *sc_dmas; 204 205 #ifdef DIAGNOSTIC 206 pci_chipset_tag_t sc_pc; 207 pcitag_t sc_pt; 208 #endif 209 /* SiS 7012 hack */ 210 int sc_sample_shift; 211 int sc_sts_reg; 212 /* 440MX workaround */ 213 int sc_dmamap_flags; 214 215 216 /* Power Management */ 217 void *sc_powerhook; 218 int sc_suspend; 219 220 /* sysctl */ 221 struct sysctllog *sc_log; 222 uint32_t sc_ac97_clock; 223 int sc_ac97_clock_mib; 224 }; 225 226 /* Debug */ 227 #ifdef AUICH_DEBUG 228 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 229 int auich_debug = 0xfffe; 230 #define ICH_DEBUG_CODECIO 0x0001 231 #define ICH_DEBUG_DMA 0x0002 232 #define ICH_DEBUG_INTR 0x0004 233 #else 234 #define DPRINTF(x,y) /* nothing */ 235 #endif 236 237 int auich_match(struct device *, struct cfdata *, void *); 238 void auich_attach(struct device *, struct device *, void *); 239 int auich_intr(void *); 240 241 CFATTACH_DECL(auich, sizeof(struct auich_softc), 242 auich_match, auich_attach, NULL, NULL); 243 244 int auich_open(void *, int); 245 void auich_close(void *); 246 int auich_query_encoding(void *, struct audio_encoding *); 247 int auich_set_params(void *, int, int, struct audio_params *, 248 struct audio_params *); 249 int auich_round_blocksize(void *, int); 250 int auich_halt_output(void *); 251 int auich_halt_input(void *); 252 int auich_getdev(void *, struct audio_device *); 253 int auich_set_port(void *, mixer_ctrl_t *); 254 int auich_get_port(void *, mixer_ctrl_t *); 255 int auich_query_devinfo(void *, mixer_devinfo_t *); 256 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 257 void auich_freem(void *, void *, struct malloc_type *); 258 size_t auich_round_buffersize(void *, int, size_t); 259 paddr_t auich_mappage(void *, void *, off_t, int); 260 int auich_get_props(void *); 261 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 262 void *, struct audio_params *); 263 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 264 void *, struct audio_params *); 265 266 int auich_alloc_cdata(struct auich_softc *); 267 268 int auich_allocmem(struct auich_softc *, size_t, size_t, 269 struct auich_dma *); 270 int auich_freemem(struct auich_softc *, struct auich_dma *); 271 272 void auich_powerhook(int, void *); 273 int auich_set_rate(struct auich_softc *, int, u_long); 274 static int auich_sysctl_verify(SYSCTLFN_ARGS); 275 void auich_finish_attach(struct device *); 276 void auich_calibrate(struct auich_softc *); 277 278 279 const struct audio_hw_if auich_hw_if = { 280 auich_open, 281 auich_close, 282 NULL, /* drain */ 283 auich_query_encoding, 284 auich_set_params, 285 auich_round_blocksize, 286 NULL, /* commit_setting */ 287 NULL, /* init_output */ 288 NULL, /* init_input */ 289 NULL, /* start_output */ 290 NULL, /* start_input */ 291 auich_halt_output, 292 auich_halt_input, 293 NULL, /* speaker_ctl */ 294 auich_getdev, 295 NULL, /* getfd */ 296 auich_set_port, 297 auich_get_port, 298 auich_query_devinfo, 299 auich_allocm, 300 auich_freem, 301 auich_round_buffersize, 302 auich_mappage, 303 auich_get_props, 304 auich_trigger_output, 305 auich_trigger_input, 306 NULL, /* dev_ioctl */ 307 }; 308 309 int auich_attach_codec(void *, struct ac97_codec_if *); 310 int auich_read_codec(void *, u_int8_t, u_int16_t *); 311 int auich_write_codec(void *, u_int8_t, u_int16_t); 312 int auich_reset_codec(void *); 313 314 static const struct auich_devtype { 315 int vendor; 316 int product; 317 const char *name; 318 const char *shortname; /* must be less than 11 characters */ 319 } auich_devices[] = { 320 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 321 "i82801AA (ICH) AC-97 Audio", "ICH" }, 322 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 323 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 324 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 325 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 326 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 327 "i82440MX AC-97 Audio", "440MX" }, 328 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC, 329 "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 330 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC, 331 "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 332 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC, 333 "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 334 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_AC, 335 "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 336 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC, 337 "SiS 7012 AC-97 Audio", "SiS7012" }, 338 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC, 339 "nForce MCP AC-97 Audio", "nForce" }, 340 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC, 341 "nForce2 MCP-T AC-97 Audio", "nForce2" }, 342 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC, 343 "nForce3 MCP-T AC-97 Audio", "nForce3" }, 344 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_MCPT_AC, 345 "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 346 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_AC, 347 "AMD768 AC-97 Audio", "AMD768" }, 348 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC8111_AC, 349 "AMD8111 AC-97 Audio", "AMD8111" }, 350 { 0, 0, 351 NULL, NULL }, 352 }; 353 354 static const struct auich_devtype * 355 auich_lookup(struct pci_attach_args *pa) 356 { 357 const struct auich_devtype *d; 358 359 for (d = auich_devices; d->name != NULL; d++) { 360 if (PCI_VENDOR(pa->pa_id) == d->vendor 361 && PCI_PRODUCT(pa->pa_id) == d->product) 362 return (d); 363 } 364 365 return (NULL); 366 } 367 368 int 369 auich_match(struct device *parent, struct cfdata *match, void *aux) 370 { 371 struct pci_attach_args *pa = aux; 372 373 if (auich_lookup(pa) != NULL) 374 return (1); 375 376 return (0); 377 } 378 379 void 380 auich_attach(struct device *parent, struct device *self, void *aux) 381 { 382 struct auich_softc *sc = (struct auich_softc *)self; 383 struct pci_attach_args *pa = aux; 384 pci_intr_handle_t ih; 385 bus_size_t mix_size, aud_size; 386 pcireg_t v; 387 const char *intrstr; 388 const struct auich_devtype *d; 389 struct sysctlnode *node; 390 int err, node_mib; 391 392 aprint_naive(": Audio controller\n"); 393 394 d = auich_lookup(pa); 395 if (d == NULL) 396 panic("auich_attach: impossible"); 397 398 #ifdef DIAGNOSTIC 399 sc->sc_pc = pa->pa_pc; 400 sc->sc_pt = pa->pa_tag; 401 #endif 402 403 aprint_normal(": %s\n", d->name); 404 405 if (d->vendor == PCI_VENDOR_INTEL && 406 (d->product == PCI_PRODUCT_INTEL_82801DB_AC || 407 d->product == PCI_PRODUCT_INTEL_82801EB_AC || 408 d->product == PCI_PRODUCT_INTEL_82801FB_AC)) { 409 /* 410 * Use native mode for ICH4/ICH5/ICH6 411 */ 412 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 413 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 414 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 415 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 416 v | ICH_CFG_IOSE); 417 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 418 0, &sc->iot, &sc->mix_ioh, NULL, 419 &mix_size)) { 420 aprint_error("%s: can't map codec i/o space\n", 421 sc->sc_dev.dv_xname); 422 return; 423 } 424 } 425 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 426 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 427 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 428 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 429 v | ICH_CFG_IOSE); 430 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 431 0, &sc->iot, &sc->aud_ioh, NULL, 432 &aud_size)) { 433 aprint_error("%s: can't map device i/o space\n", 434 sc->sc_dev.dv_xname); 435 return; 436 } 437 } 438 } else { 439 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 440 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 441 aprint_error("%s: can't map codec i/o space\n", 442 sc->sc_dev.dv_xname); 443 return; 444 } 445 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 446 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 447 aprint_error("%s: can't map device i/o space\n", 448 sc->sc_dev.dv_xname); 449 return; 450 } 451 } 452 sc->dmat = pa->pa_dmat; 453 454 /* enable bus mastering */ 455 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 456 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 457 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 458 459 /* Map and establish the interrupt. */ 460 if (pci_intr_map(pa, &ih)) { 461 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 462 return; 463 } 464 intrstr = pci_intr_string(pa->pa_pc, ih); 465 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 466 auich_intr, sc); 467 if (sc->sc_ih == NULL) { 468 aprint_error("%s: can't establish interrupt", 469 sc->sc_dev.dv_xname); 470 if (intrstr != NULL) 471 aprint_normal(" at %s", intrstr); 472 aprint_normal("\n"); 473 return; 474 } 475 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 476 477 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 478 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 479 "0x%02x", PCI_REVISION(pa->pa_class)); 480 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 481 482 /* SiS 7012 needs special handling */ 483 if (d->vendor == PCI_VENDOR_SIS 484 && d->product == PCI_PRODUCT_SIS_7012_AC) { 485 sc->sc_sts_reg = ICH_PICB; 486 sc->sc_sample_shift = 0; 487 } else { 488 sc->sc_sts_reg = ICH_STS; 489 sc->sc_sample_shift = 1; 490 } 491 492 /* Workaround for a 440MX B-stepping erratum */ 493 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 494 if (d->vendor == PCI_VENDOR_INTEL 495 && d->product == PCI_PRODUCT_INTEL_82440MX_ACA) { 496 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 497 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 498 } 499 500 /* Set up DMA lists. */ 501 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 502 auich_alloc_cdata(sc); 503 504 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 505 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 506 507 sc->host_if.arg = sc; 508 sc->host_if.attach = auich_attach_codec; 509 sc->host_if.read = auich_read_codec; 510 sc->host_if.write = auich_write_codec; 511 sc->host_if.reset = auich_reset_codec; 512 513 if (ac97_attach(&sc->host_if) != 0) 514 return; 515 516 /* Watch for power change */ 517 sc->sc_suspend = PWR_RESUME; 518 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 519 520 config_interrupts(self, auich_finish_attach); 521 522 /* sysctl setup */ 523 if (AC97_IS_FIXED_RATE(sc->codec_if)) 524 return; 525 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 526 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 527 CTL_HW, CTL_EOL); 528 if (err != 0) 529 goto sysctl_err; 530 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 531 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 532 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 533 if (err != 0) 534 goto sysctl_err; 535 node_mib = node->sysctl_num; 536 /* passing the sc address instead of &sc->sc_ac97_clock */ 537 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 538 CTLTYPE_INT, "ac97rate", 539 SYSCTL_DESCR("AC'97 codec link rate"), 540 auich_sysctl_verify, 0, sc, 0, 541 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 542 if (err != 0) 543 goto sysctl_err; 544 sc->sc_ac97_clock_mib = node->sysctl_num; 545 546 return; 547 548 sysctl_err: 549 printf("%s: failed to add sysctl nodes. (%d)\n", 550 sc->sc_dev.dv_xname, err); 551 return; /* failure of sysctl is not fatal. */ 552 } 553 554 #if 0 555 int 556 auich_detach(struct device *self, int flags) 557 { 558 struct auich_softc *sc; 559 560 sc = (struct auich_softc *)self; 561 /* sysctl */ 562 sysctl_teardown(&sc->sc_log); 563 /* audio */ 564 if (sc->sc_audiodev != NULL) 565 config_detach(sc->sc_audiodev, flags); 566 /* XXX ac97 */ 567 /* XXX memory */ 568 return 0; 569 } 570 #endif 571 572 static int 573 auich_sysctl_verify(SYSCTLFN_ARGS) 574 { 575 int error, tmp; 576 struct sysctlnode node; 577 struct auich_softc *sc; 578 579 node = *rnode; 580 sc = rnode->sysctl_data; 581 tmp = sc->sc_ac97_clock; 582 node.sysctl_data = &tmp; 583 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 584 if (error || newp == NULL) 585 return error; 586 587 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 588 if (tmp < 48000 || tmp > 96000) 589 return EINVAL; 590 sc->sc_ac97_clock = tmp; 591 } 592 593 return 0; 594 } 595 596 void 597 auich_finish_attach(struct device *self) 598 { 599 struct auich_softc *sc = (void *)self; 600 601 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 602 auich_calibrate(sc); 603 604 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 605 } 606 607 #define ICH_CODECIO_INTERVAL 10 608 int 609 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 610 { 611 struct auich_softc *sc = v; 612 int i; 613 uint32_t status; 614 615 /* wait for an access semaphore */ 616 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 617 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 618 DELAY(ICH_CODECIO_INTERVAL)); 619 620 if (i > 0) { 621 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 622 DPRINTF(ICH_DEBUG_CODECIO, 623 ("auich_read_codec(%x, %x)\n", reg, *val)); 624 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 625 if (status & ICH_RCS) { 626 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 627 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 628 *val = 0xffff; 629 DPRINTF(ICH_DEBUG_CODECIO, 630 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 631 return -1; 632 } 633 return 0; 634 } else { 635 DPRINTF(ICH_DEBUG_CODECIO, 636 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 637 return -1; 638 } 639 } 640 641 int 642 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 643 { 644 struct auich_softc *sc = v; 645 int i; 646 647 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 648 /* wait for an access semaphore */ 649 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 650 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 651 DELAY(ICH_CODECIO_INTERVAL)); 652 653 if (i > 0) { 654 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 655 return 0; 656 } else { 657 DPRINTF(ICH_DEBUG_CODECIO, 658 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 659 return -1; 660 } 661 } 662 663 int 664 auich_attach_codec(void *v, struct ac97_codec_if *cif) 665 { 666 struct auich_softc *sc = v; 667 668 sc->codec_if = cif; 669 return 0; 670 } 671 672 int 673 auich_reset_codec(void *v) 674 { 675 struct auich_softc *sc = v; 676 int i; 677 uint32_t control, status; 678 679 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 680 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 681 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 682 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 683 684 for (i = 500000; i >= 0; i--) { 685 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 686 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 687 break; 688 DELAY(1); 689 } 690 if (i <= 0) { 691 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 692 return ETIMEDOUT; 693 } 694 #ifdef DEBUG 695 if (status & ICH_SCR) 696 printf("%s: The 2nd codec is ready.\n", 697 sc->sc_dev.dv_xname); 698 if (status & ICH_S2CR) 699 printf("%s: The 3rd codec is ready.\n", 700 sc->sc_dev.dv_xname); 701 #endif 702 return 0; 703 } 704 705 int 706 auich_open(void *v, int flags) 707 { 708 return 0; 709 } 710 711 void 712 auich_close(void *v) 713 { 714 } 715 716 int 717 auich_query_encoding(void *v, struct audio_encoding *aep) 718 { 719 static const struct auich_encoding { 720 const char *name; 721 int encoding, precision, flags; 722 } *p, auich_encoding[] = { 723 {AudioEulinear, AUDIO_ENCODING_ULINEAR, 724 8, AUDIO_ENCODINGFLAG_EMULATED}, 725 {AudioEmulaw, AUDIO_ENCODING_ULAW, 726 8, AUDIO_ENCODINGFLAG_EMULATED}, 727 {AudioEalaw, AUDIO_ENCODING_ALAW, 728 8, AUDIO_ENCODINGFLAG_EMULATED}, 729 {AudioEslinear, AUDIO_ENCODING_SLINEAR, 730 8, AUDIO_ENCODINGFLAG_EMULATED}, 731 {AudioEslinear_le, AUDIO_ENCODING_SLINEAR_LE, 732 16, 0}, 733 {AudioEulinear_le, AUDIO_ENCODING_ULINEAR_LE, 734 16, AUDIO_ENCODINGFLAG_EMULATED}, 735 {AudioEslinear_be, AUDIO_ENCODING_SLINEAR_BE, 736 16, AUDIO_ENCODINGFLAG_EMULATED}, 737 {AudioEulinear_be, AUDIO_ENCODING_ULINEAR_BE, 738 16, AUDIO_ENCODINGFLAG_EMULATED}, 739 }; 740 741 if (aep->index >= 8) 742 return (EINVAL); 743 744 p = &auich_encoding[aep->index]; 745 strcpy(aep->name, p->name); 746 aep->encoding = p->encoding; 747 aep->precision = p->precision; 748 aep->flags = p->flags; 749 return (0); 750 } 751 752 int 753 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 754 { 755 int ret; 756 u_long ratetmp; 757 758 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 759 ratetmp = srate; 760 if (mode == AUMODE_RECORD) 761 return sc->codec_if->vtbl->set_rate(sc->codec_if, 762 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 763 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 764 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 765 if (ret) 766 return ret; 767 ratetmp = srate; 768 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 769 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 770 if (ret) 771 return ret; 772 ratetmp = srate; 773 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 774 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 775 return ret; 776 } 777 778 int 779 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 780 struct audio_params *rec) 781 { 782 struct auich_softc *sc = v; 783 struct audio_params *p; 784 int mode; 785 u_int32_t control; 786 787 for (mode = AUMODE_RECORD; mode != -1; 788 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 789 if ((setmode & mode) == 0) 790 continue; 791 792 p = mode == AUMODE_PLAY ? play : rec; 793 if (p == NULL) 794 continue; 795 796 if (p->sample_rate < 8000 || 797 p->sample_rate > 48000) 798 return (EINVAL); 799 800 if (p->precision == 8) 801 p->factor = 2; 802 else 803 p->factor = 1; 804 805 p->sw_code = NULL; 806 /* setup hardware formats */ 807 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 808 p->hw_precision = 16; 809 810 if (mode == AUMODE_RECORD) { 811 if (p->channels < 1 || p->channels > 2) 812 return EINVAL; 813 } else { 814 switch (p->channels) { 815 case 1: 816 break; 817 case 2: 818 break; 819 case 4: 820 if (!AC97_IS_4CH(sc->codec_if)) 821 return EINVAL; 822 break; 823 case 6: 824 if (!AC97_IS_6CH(sc->codec_if)) 825 return EINVAL; 826 break; 827 default: 828 return EINVAL; 829 } 830 } 831 /* If monaural is requested, aurateconv expands a monaural 832 * stream to stereo. */ 833 if (p->channels == 1) 834 p->hw_channels = 2; 835 836 switch (p->encoding) { 837 case AUDIO_ENCODING_SLINEAR_BE: 838 if (p->precision == 16) { 839 p->sw_code = swap_bytes; 840 } else { 841 if (mode == AUMODE_PLAY) 842 p->sw_code = linear8_to_linear16_le; 843 else 844 p->sw_code = linear16_to_linear8_le; 845 } 846 break; 847 848 case AUDIO_ENCODING_SLINEAR_LE: 849 if (p->precision != 16) { 850 if (mode == AUMODE_PLAY) 851 p->sw_code = linear8_to_linear16_le; 852 else 853 p->sw_code = linear16_to_linear8_le; 854 } 855 break; 856 857 case AUDIO_ENCODING_ULINEAR_BE: 858 if (p->precision == 16) { 859 if (mode == AUMODE_PLAY) 860 p->sw_code = 861 swap_bytes_change_sign16_le; 862 else 863 p->sw_code = 864 change_sign16_swap_bytes_le; 865 } else { 866 if (mode == AUMODE_PLAY) 867 p->sw_code = 868 ulinear8_to_slinear16_le; 869 else 870 p->sw_code = 871 slinear16_to_ulinear8_le; 872 } 873 break; 874 875 case AUDIO_ENCODING_ULINEAR_LE: 876 if (p->precision == 16) { 877 p->sw_code = change_sign16_le; 878 } else { 879 if (mode == AUMODE_PLAY) 880 p->sw_code = 881 ulinear8_to_slinear16_le; 882 else 883 p->sw_code = 884 slinear16_to_ulinear8_le; 885 } 886 break; 887 888 case AUDIO_ENCODING_ULAW: 889 if (mode == AUMODE_PLAY) { 890 p->sw_code = mulaw_to_slinear16_le; 891 } else { 892 p->sw_code = slinear16_to_mulaw_le; 893 } 894 break; 895 896 case AUDIO_ENCODING_ALAW: 897 if (mode == AUMODE_PLAY) { 898 p->sw_code = alaw_to_slinear16_le; 899 } else { 900 p->sw_code = slinear16_to_alaw_le; 901 } 902 break; 903 904 default: 905 return (EINVAL); 906 } 907 908 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 909 p->hw_sample_rate = AC97_SINGLE_RATE; 910 /* If hw_sample_rate is changed, aurateconv works. */ 911 } else { 912 if (auich_set_rate(sc, mode, p->sample_rate)) 913 return EINVAL; 914 } 915 if (mode == AUMODE_PLAY) { 916 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 917 control &= ~ICH_PCM246_MASK; 918 if (p->channels == 4) { 919 control |= ICH_PCM4; 920 } else if (p->channels == 6) { 921 control |= ICH_PCM6; 922 } 923 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 924 } 925 } 926 927 return (0); 928 } 929 930 int 931 auich_round_blocksize(void *v, int blk) 932 { 933 934 return (blk & ~0x3f); /* keep good alignment */ 935 } 936 937 int 938 auich_halt_output(void *v) 939 { 940 struct auich_softc *sc = v; 941 942 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 943 944 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 945 sc->pcmo.intr = NULL; 946 947 return (0); 948 } 949 950 int 951 auich_halt_input(void *v) 952 { 953 struct auich_softc *sc = v; 954 955 DPRINTF(ICH_DEBUG_DMA, 956 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 957 958 /* XXX halt both unless known otherwise */ 959 960 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 961 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 962 sc->pcmi.intr = NULL; 963 964 return (0); 965 } 966 967 int 968 auich_getdev(void *v, struct audio_device *adp) 969 { 970 struct auich_softc *sc = v; 971 972 *adp = sc->sc_audev; 973 return (0); 974 } 975 976 int 977 auich_set_port(void *v, mixer_ctrl_t *cp) 978 { 979 struct auich_softc *sc = v; 980 981 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 982 } 983 984 int 985 auich_get_port(void *v, mixer_ctrl_t *cp) 986 { 987 struct auich_softc *sc = v; 988 989 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 990 } 991 992 int 993 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 994 { 995 struct auich_softc *sc = v; 996 997 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 998 } 999 1000 void * 1001 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 1002 int flags) 1003 { 1004 struct auich_softc *sc = v; 1005 struct auich_dma *p; 1006 int error; 1007 1008 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1009 return (NULL); 1010 1011 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1012 if (p == NULL) 1013 return (NULL); 1014 1015 error = auich_allocmem(sc, size, 0, p); 1016 if (error) { 1017 free(p, pool); 1018 return (NULL); 1019 } 1020 1021 p->next = sc->sc_dmas; 1022 sc->sc_dmas = p; 1023 1024 return (KERNADDR(p)); 1025 } 1026 1027 void 1028 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1029 { 1030 struct auich_softc *sc = v; 1031 struct auich_dma *p, **pp; 1032 1033 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1034 if (KERNADDR(p) == ptr) { 1035 auich_freemem(sc, p); 1036 *pp = p->next; 1037 free(p, pool); 1038 return; 1039 } 1040 } 1041 } 1042 1043 size_t 1044 auich_round_buffersize(void *v, int direction, size_t size) 1045 { 1046 1047 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1048 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1049 1050 return size; 1051 } 1052 1053 paddr_t 1054 auich_mappage(void *v, void *mem, off_t off, int prot) 1055 { 1056 struct auich_softc *sc = v; 1057 struct auich_dma *p; 1058 1059 if (off < 0) 1060 return (-1); 1061 1062 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1063 ; 1064 if (!p) 1065 return (-1); 1066 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1067 off, prot, BUS_DMA_WAITOK)); 1068 } 1069 1070 int 1071 auich_get_props(void *v) 1072 { 1073 struct auich_softc *sc = v; 1074 int props; 1075 1076 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1077 /* 1078 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1079 * rate because of aurateconv. Applications can't know what rate the 1080 * device can process in the case of mmap(). 1081 */ 1082 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 1083 props |= AUDIO_PROP_MMAP; 1084 return props; 1085 } 1086 1087 int 1088 auich_intr(void *v) 1089 { 1090 struct auich_softc *sc = v; 1091 int ret = 0, gsts; 1092 1093 #ifdef DIAGNOSTIC 1094 int csts; 1095 #endif 1096 1097 #ifdef DIAGNOSTIC 1098 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1099 if (csts & PCI_STATUS_MASTER_ABORT) { 1100 printf("auich_intr: PCI master abort\n"); 1101 } 1102 #endif 1103 1104 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 1105 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1106 1107 if (gsts & ICH_POINT) { 1108 int sts; 1109 1110 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1111 ICH_PCMO + sc->sc_sts_reg); 1112 DPRINTF(ICH_DEBUG_INTR, 1113 ("auich_intr: osts=0x%x\n", sts)); 1114 1115 if (sts & ICH_FIFOE) 1116 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1117 1118 if (sts & ICH_BCIS) { 1119 struct auich_dmalist *q; 1120 int blksize, qptr, i; 1121 1122 blksize = sc->pcmo.blksize; 1123 qptr = sc->pcmo.qptr; 1124 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1125 ICH_PCMO + ICH_CIV); 1126 1127 while (qptr != i) { 1128 q = &sc->pcmo.dmalist[qptr]; 1129 1130 q->base = sc->pcmo.p; 1131 q->len = (blksize >> sc->sc_sample_shift) | 1132 ICH_DMAF_IOC; 1133 DPRINTF(ICH_DEBUG_INTR, 1134 ("auich_intr: %p, %p = %x @ 0x%x\n", 1135 &sc->pcmo.dmalist[i], q, q->len, q->base)); 1136 1137 sc->pcmo.p += blksize; 1138 if (sc->pcmo.p >= sc->pcmo.end) 1139 sc->pcmo.p = sc->pcmo.start; 1140 1141 qptr = (qptr + 1) & ICH_LVI_MASK; 1142 if (sc->pcmo.intr) 1143 sc->pcmo.intr(sc->pcmo.arg); 1144 } 1145 1146 sc->pcmo.qptr = qptr; 1147 bus_space_write_1(sc->iot, sc->aud_ioh, 1148 ICH_PCMO + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1149 } 1150 1151 /* int ack */ 1152 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1153 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1154 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1155 ret++; 1156 } 1157 1158 if (gsts & ICH_PIINT) { 1159 int sts; 1160 1161 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1162 ICH_PCMI + sc->sc_sts_reg); 1163 DPRINTF(ICH_DEBUG_INTR, 1164 ("auich_intr: ists=0x%x\n", sts)); 1165 1166 if (sts & ICH_FIFOE) 1167 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1168 1169 if (sts & ICH_BCIS) { 1170 struct auich_dmalist *q; 1171 int blksize, qptr, i; 1172 1173 blksize = sc->pcmi.blksize; 1174 qptr = sc->pcmi.qptr; 1175 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1176 ICH_PCMI + ICH_CIV); 1177 1178 while (qptr != i) { 1179 q = &sc->pcmi.dmalist[qptr]; 1180 1181 q->base = sc->pcmi.p; 1182 q->len = (blksize >> sc->sc_sample_shift) | 1183 ICH_DMAF_IOC; 1184 DPRINTF(ICH_DEBUG_INTR, 1185 ("auich_intr: %p, %p = %x @ 0x%x\n", 1186 &sc->pcmi.dmalist[i], q, q->len, q->base)); 1187 1188 sc->pcmi.p += blksize; 1189 if (sc->pcmi.p >= sc->pcmi.end) 1190 sc->pcmi.p = sc->pcmi.start; 1191 1192 qptr = (qptr + 1) & ICH_LVI_MASK; 1193 if (sc->pcmi.intr) 1194 sc->pcmi.intr(sc->pcmi.arg); 1195 } 1196 1197 sc->pcmi.qptr = qptr; 1198 bus_space_write_1(sc->iot, sc->aud_ioh, 1199 ICH_PCMI + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1200 } 1201 1202 /* int ack */ 1203 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1204 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1205 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1206 ret++; 1207 } 1208 1209 if (gsts & ICH_MIINT) { 1210 int sts; 1211 1212 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1213 ICH_MICI + sc->sc_sts_reg); 1214 DPRINTF(ICH_DEBUG_INTR, 1215 ("auich_intr: ists=0x%x\n", sts)); 1216 1217 if (sts & ICH_FIFOE) 1218 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1219 1220 /* TODO mic input DMA */ 1221 1222 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1223 } 1224 1225 return ret; 1226 } 1227 1228 int 1229 auich_trigger_output(void *v, void *start, void *end, int blksize, 1230 void (*intr)(void *), void *arg, struct audio_params *param) 1231 { 1232 struct auich_softc *sc = v; 1233 struct auich_dmalist *q; 1234 struct auich_dma *p; 1235 size_t size; 1236 int qptr; 1237 #ifdef DIAGNOSTIC 1238 int csts; 1239 #endif 1240 1241 DPRINTF(ICH_DEBUG_DMA, 1242 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1243 start, end, blksize, intr, arg, param)); 1244 1245 sc->pcmo.intr = intr; 1246 sc->pcmo.arg = arg; 1247 #ifdef DIAGNOSTIC 1248 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1249 if (csts & PCI_STATUS_MASTER_ABORT) { 1250 printf("auich_trigger_output: PCI master abort\n"); 1251 } 1252 #endif 1253 1254 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1255 ; 1256 if (!p) { 1257 printf("auich_trigger_output: bad addr %p\n", start); 1258 return (EINVAL); 1259 } 1260 1261 size = (size_t)((caddr_t)end - (caddr_t)start); 1262 1263 /* 1264 * The logic behind this is: 1265 * setup one buffer to play, then LVI dump out the rest 1266 * to the scatter-gather chain. 1267 */ 1268 sc->pcmo.start = DMAADDR(p); 1269 sc->pcmo.p = sc->pcmo.start; 1270 sc->pcmo.end = sc->pcmo.start + size; 1271 sc->pcmo.blksize = blksize; 1272 1273 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1274 q = &sc->pcmo.dmalist[qptr]; 1275 1276 q->base = sc->pcmo.p; 1277 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1278 1279 sc->pcmo.p += blksize; 1280 if (sc->pcmo.p >= sc->pcmo.end) 1281 sc->pcmo.p = sc->pcmo.start; 1282 } 1283 1284 sc->pcmo.qptr = qptr = 0; 1285 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1286 (qptr - 1) & ICH_LVI_MASK); 1287 1288 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1289 sc->sc_cddma + ICH_PCMO_OFF(0)); 1290 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1291 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1292 1293 return (0); 1294 } 1295 1296 int 1297 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1298 void *v; 1299 void *start, *end; 1300 int blksize; 1301 void (*intr)(void *); 1302 void *arg; 1303 struct audio_params *param; 1304 { 1305 struct auich_softc *sc = v; 1306 struct auich_dmalist *q; 1307 struct auich_dma *p; 1308 size_t size; 1309 int qptr; 1310 #ifdef DIAGNOSTIC 1311 int csts; 1312 #endif 1313 1314 DPRINTF(ICH_DEBUG_DMA, 1315 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1316 start, end, blksize, intr, arg, param)); 1317 1318 sc->pcmi.intr = intr; 1319 sc->pcmi.arg = arg; 1320 1321 #ifdef DIAGNOSTIC 1322 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1323 if (csts & PCI_STATUS_MASTER_ABORT) { 1324 printf("auich_trigger_input: PCI master abort\n"); 1325 } 1326 #endif 1327 1328 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1329 ; 1330 if (!p) { 1331 printf("auich_trigger_input: bad addr %p\n", start); 1332 return (EINVAL); 1333 } 1334 1335 size = (size_t)((caddr_t)end - (caddr_t)start); 1336 1337 /* 1338 * The logic behind this is: 1339 * setup one buffer to play, then LVI dump out the rest 1340 * to the scatter-gather chain. 1341 */ 1342 sc->pcmi.start = DMAADDR(p); 1343 sc->pcmi.p = sc->pcmi.start; 1344 sc->pcmi.end = sc->pcmi.start + size; 1345 sc->pcmi.blksize = blksize; 1346 1347 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1348 q = &sc->pcmi.dmalist[qptr]; 1349 1350 q->base = sc->pcmi.p; 1351 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1352 1353 sc->pcmi.p += blksize; 1354 if (sc->pcmi.p >= sc->pcmi.end) 1355 sc->pcmi.p = sc->pcmi.start; 1356 } 1357 1358 sc->pcmi.qptr = qptr = 0; 1359 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1360 (qptr - 1) & ICH_LVI_MASK); 1361 1362 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1363 sc->sc_cddma + ICH_PCMI_OFF(0)); 1364 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1365 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1366 1367 return (0); 1368 } 1369 1370 int 1371 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1372 struct auich_dma *p) 1373 { 1374 int error; 1375 1376 p->size = size; 1377 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1378 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1379 &p->nsegs, BUS_DMA_NOWAIT); 1380 if (error) 1381 return (error); 1382 1383 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1384 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1385 if (error) 1386 goto free; 1387 1388 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1389 0, BUS_DMA_NOWAIT, &p->map); 1390 if (error) 1391 goto unmap; 1392 1393 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1394 BUS_DMA_NOWAIT); 1395 if (error) 1396 goto destroy; 1397 return (0); 1398 1399 destroy: 1400 bus_dmamap_destroy(sc->dmat, p->map); 1401 unmap: 1402 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1403 free: 1404 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1405 return (error); 1406 } 1407 1408 int 1409 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1410 { 1411 1412 bus_dmamap_unload(sc->dmat, p->map); 1413 bus_dmamap_destroy(sc->dmat, p->map); 1414 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1415 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1416 return (0); 1417 } 1418 1419 int 1420 auich_alloc_cdata(struct auich_softc *sc) 1421 { 1422 bus_dma_segment_t seg; 1423 int error, rseg; 1424 1425 /* 1426 * Allocate the control data structure, and create and load the 1427 * DMA map for it. 1428 */ 1429 if ((error = bus_dmamem_alloc(sc->dmat, 1430 sizeof(struct auich_cdata), 1431 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1432 printf("%s: unable to allocate control data, error = %d\n", 1433 sc->sc_dev.dv_xname, error); 1434 goto fail_0; 1435 } 1436 1437 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1438 sizeof(struct auich_cdata), 1439 (caddr_t *) &sc->sc_cdata, 1440 sc->sc_dmamap_flags)) != 0) { 1441 printf("%s: unable to map control data, error = %d\n", 1442 sc->sc_dev.dv_xname, error); 1443 goto fail_1; 1444 } 1445 1446 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1447 sizeof(struct auich_cdata), 0, 0, 1448 &sc->sc_cddmamap)) != 0) { 1449 printf("%s: unable to create control data DMA map, " 1450 "error = %d\n", sc->sc_dev.dv_xname, error); 1451 goto fail_2; 1452 } 1453 1454 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1455 sc->sc_cdata, sizeof(struct auich_cdata), 1456 NULL, 0)) != 0) { 1457 printf("%s: unable tp load control data DMA map, " 1458 "error = %d\n", sc->sc_dev.dv_xname, error); 1459 goto fail_3; 1460 } 1461 1462 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1463 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1464 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1465 1466 return (0); 1467 1468 fail_3: 1469 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1470 fail_2: 1471 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1472 sizeof(struct auich_cdata)); 1473 fail_1: 1474 bus_dmamem_free(sc->dmat, &seg, rseg); 1475 fail_0: 1476 return (error); 1477 } 1478 1479 void 1480 auich_powerhook(int why, void *addr) 1481 { 1482 struct auich_softc *sc = (struct auich_softc *)addr; 1483 1484 switch (why) { 1485 case PWR_SUSPEND: 1486 case PWR_STANDBY: 1487 /* Power down */ 1488 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1489 sc->sc_suspend = why; 1490 break; 1491 1492 case PWR_RESUME: 1493 /* Wake up */ 1494 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1495 if (sc->sc_suspend == PWR_RESUME) { 1496 printf("%s: resume without suspend.\n", 1497 sc->sc_dev.dv_xname); 1498 sc->sc_suspend = why; 1499 return; 1500 } 1501 sc->sc_suspend = why; 1502 auich_reset_codec(sc); 1503 DELAY(1000); 1504 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1505 break; 1506 1507 case PWR_SOFTSUSPEND: 1508 case PWR_SOFTSTANDBY: 1509 case PWR_SOFTRESUME: 1510 break; 1511 } 1512 } 1513 1514 /* 1515 * Calibrate card (some boards are overclocked and need scaling) 1516 */ 1517 void 1518 auich_calibrate(struct auich_softc *sc) 1519 { 1520 struct timeval t1, t2; 1521 uint8_t ociv, nciv; 1522 uint64_t wait_us; 1523 uint32_t actual_48k_rate, bytes, ac97rate; 1524 void *temp_buffer; 1525 struct auich_dma *p; 1526 u_long rate; 1527 1528 /* 1529 * Grab audio from input for fixed interval and compare how 1530 * much we actually get with what we expect. Interval needs 1531 * to be sufficiently short that no interrupts are 1532 * generated. 1533 */ 1534 1535 /* Force the codec to a known state first. */ 1536 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1537 rate = sc->sc_ac97_clock = 48000; 1538 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1539 &rate); 1540 1541 /* Setup a buffer */ 1542 bytes = 64000; 1543 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1544 1545 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1546 ; 1547 if (p == NULL) { 1548 printf("auich_calibrate: bad address %p\n", temp_buffer); 1549 return; 1550 } 1551 sc->pcmi.dmalist[0].base = DMAADDR(p); 1552 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1553 1554 /* 1555 * our data format is stereo, 16 bit so each sample is 4 bytes. 1556 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1557 * we're going to start recording with interrupts disabled and measure 1558 * the time taken for one block to complete. we know the block size, 1559 * we know the time in microseconds, we calculate the sample rate: 1560 * 1561 * actual_rate [bps] = bytes / (time [s] * 4) 1562 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1563 * actual_rate [Hz] = (bytes * 250000) / time [us] 1564 */ 1565 1566 /* prepare */ 1567 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1568 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1569 sc->sc_cddma + ICH_PCMI_OFF(0)); 1570 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1571 (0 - 1) & ICH_LVI_MASK); 1572 1573 /* start */ 1574 microtime(&t1); 1575 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1576 1577 /* wait */ 1578 nciv = ociv; 1579 do { 1580 microtime(&t2); 1581 if (t2.tv_sec - t1.tv_sec > 1) 1582 break; 1583 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1584 ICH_PCMI + ICH_CIV); 1585 } while (nciv == ociv); 1586 microtime(&t2); 1587 1588 /* stop */ 1589 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1590 1591 /* reset */ 1592 DELAY(100); 1593 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1594 1595 /* turn time delta into us */ 1596 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1597 1598 auich_freem(sc, temp_buffer, M_DEVBUF); 1599 1600 if (nciv == ociv) { 1601 printf("%s: ac97 link rate calibration timed out after %" 1602 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1603 return; 1604 } 1605 1606 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1607 1608 if (actual_48k_rate < 50000) 1609 ac97rate = 48000; 1610 else 1611 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1612 1613 printf("%s: measured ac97 link rate at %d Hz", 1614 sc->sc_dev.dv_xname, actual_48k_rate); 1615 if (ac97rate != actual_48k_rate) 1616 printf(", will use %d Hz", ac97rate); 1617 printf("\n"); 1618 1619 sc->sc_ac97_clock = ac97rate; 1620 } 1621
Indexes created Thu Oct 23 22:10:10 GMT 2025