auich.c revision 1.79
1 /* $NetBSD: auich.c,v 1.79 2004/11/11 03:06:21 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.79 2004/11/11 03:06:21 kent Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 bus_space_tag_t iot; 179 bus_space_handle_t mix_ioh; 180 bus_space_handle_t aud_ioh; 181 bus_dma_tag_t dmat; 182 183 struct ac97_codec_if *codec_if; 184 struct ac97_host_if host_if; 185 186 /* DMA scatter-gather lists. */ 187 bus_dmamap_t sc_cddmamap; 188 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 189 190 struct auich_cdata *sc_cdata; 191 192 struct auich_ring { 193 int qptr; 194 struct auich_dmalist *dmalist; 195 196 u_int32_t start, p, end; 197 int blksize; 198 199 void (*intr)(void *); 200 void *arg; 201 } pcmo, pcmi, mici; 202 203 struct auich_dma *sc_dmas; 204 205 #ifdef DIAGNOSTIC 206 pci_chipset_tag_t sc_pc; 207 pcitag_t sc_pt; 208 #endif 209 /* SiS 7012 hack */ 210 int sc_sample_shift; 211 int sc_sts_reg; 212 /* 440MX workaround */ 213 int sc_dmamap_flags; 214 215 216 /* Power Management */ 217 void *sc_powerhook; 218 int sc_suspend; 219 220 /* sysctl */ 221 struct sysctllog *sc_log; 222 uint32_t sc_ac97_clock; 223 int sc_ac97_clock_mib; 224 }; 225 226 /* Debug */ 227 #ifdef AUICH_DEBUG 228 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 229 int auich_debug = 0xfffe; 230 #define ICH_DEBUG_CODECIO 0x0001 231 #define ICH_DEBUG_DMA 0x0002 232 #define ICH_DEBUG_INTR 0x0004 233 #else 234 #define DPRINTF(x,y) /* nothing */ 235 #endif 236 237 int auich_match(struct device *, struct cfdata *, void *); 238 void auich_attach(struct device *, struct device *, void *); 239 int auich_intr(void *); 240 241 CFATTACH_DECL(auich, sizeof(struct auich_softc), 242 auich_match, auich_attach, NULL, NULL); 243 244 int auich_open(void *, int); 245 void auich_close(void *); 246 int auich_query_encoding(void *, struct audio_encoding *); 247 int auich_set_params(void *, int, int, struct audio_params *, 248 struct audio_params *); 249 int auich_round_blocksize(void *, int); 250 int auich_halt_output(void *); 251 int auich_halt_input(void *); 252 int auich_getdev(void *, struct audio_device *); 253 int auich_set_port(void *, mixer_ctrl_t *); 254 int auich_get_port(void *, mixer_ctrl_t *); 255 int auich_query_devinfo(void *, mixer_devinfo_t *); 256 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 257 void auich_freem(void *, void *, struct malloc_type *); 258 size_t auich_round_buffersize(void *, int, size_t); 259 paddr_t auich_mappage(void *, void *, off_t, int); 260 int auich_get_props(void *); 261 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 262 void *, struct audio_params *); 263 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 264 void *, struct audio_params *); 265 266 int auich_alloc_cdata(struct auich_softc *); 267 268 int auich_allocmem(struct auich_softc *, size_t, size_t, 269 struct auich_dma *); 270 int auich_freemem(struct auich_softc *, struct auich_dma *); 271 272 void auich_powerhook(int, void *); 273 int auich_set_rate(struct auich_softc *, int, u_long); 274 static int auich_sysctl_verify(SYSCTLFN_ARGS); 275 void auich_finish_attach(struct device *); 276 void auich_calibrate(struct auich_softc *); 277 278 279 const struct audio_hw_if auich_hw_if = { 280 auich_open, 281 auich_close, 282 NULL, /* drain */ 283 auich_query_encoding, 284 auich_set_params, 285 auich_round_blocksize, 286 NULL, /* commit_setting */ 287 NULL, /* init_output */ 288 NULL, /* init_input */ 289 NULL, /* start_output */ 290 NULL, /* start_input */ 291 auich_halt_output, 292 auich_halt_input, 293 NULL, /* speaker_ctl */ 294 auich_getdev, 295 NULL, /* getfd */ 296 auich_set_port, 297 auich_get_port, 298 auich_query_devinfo, 299 auich_allocm, 300 auich_freem, 301 auich_round_buffersize, 302 auich_mappage, 303 auich_get_props, 304 auich_trigger_output, 305 auich_trigger_input, 306 NULL, /* dev_ioctl */ 307 }; 308 309 int auich_attach_codec(void *, struct ac97_codec_if *); 310 int auich_read_codec(void *, u_int8_t, u_int16_t *); 311 int auich_write_codec(void *, u_int8_t, u_int16_t); 312 int auich_reset_codec(void *); 313 314 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 315 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 316 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 317 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 318 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 319 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 320 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 321 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 322 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 323 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 324 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 325 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 326 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 327 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 328 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 329 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 330 331 static const struct auich_devtype { 332 pcireg_t id; 333 const char *name; 334 const char *shortname; /* must be less than 11 characters */ 335 } auich_devices[] = { 336 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 337 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 338 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 339 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 340 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 341 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 342 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 343 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 344 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 345 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 346 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 347 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 348 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 349 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 350 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 351 { 0, NULL, NULL }, 352 }; 353 354 static const struct auich_devtype * 355 auich_lookup(struct pci_attach_args *pa) 356 { 357 const struct auich_devtype *d; 358 359 for (d = auich_devices; d->name != NULL; d++) { 360 if (pa->pa_id == d->id) 361 return (d); 362 } 363 364 return (NULL); 365 } 366 367 int 368 auich_match(struct device *parent, struct cfdata *match, void *aux) 369 { 370 struct pci_attach_args *pa = aux; 371 372 if (auich_lookup(pa) != NULL) 373 return (1); 374 375 return (0); 376 } 377 378 void 379 auich_attach(struct device *parent, struct device *self, void *aux) 380 { 381 struct auich_softc *sc = (struct auich_softc *)self; 382 struct pci_attach_args *pa = aux; 383 pci_intr_handle_t ih; 384 bus_size_t mix_size, aud_size; 385 pcireg_t v; 386 const char *intrstr; 387 const struct auich_devtype *d; 388 struct sysctlnode *node; 389 int err, node_mib; 390 391 aprint_naive(": Audio controller\n"); 392 393 d = auich_lookup(pa); 394 if (d == NULL) 395 panic("auich_attach: impossible"); 396 397 #ifdef DIAGNOSTIC 398 sc->sc_pc = pa->pa_pc; 399 sc->sc_pt = pa->pa_tag; 400 #endif 401 402 aprint_normal(": %s\n", d->name); 403 404 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6) { 405 /* 406 * Use native mode for ICH4/ICH5/ICH6 407 */ 408 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 409 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 410 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 411 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 412 v | ICH_CFG_IOSE); 413 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 414 0, &sc->iot, &sc->mix_ioh, NULL, 415 &mix_size)) { 416 aprint_error("%s: can't map codec i/o space\n", 417 sc->sc_dev.dv_xname); 418 return; 419 } 420 } 421 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 422 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 423 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 424 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 425 v | ICH_CFG_IOSE); 426 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 427 0, &sc->iot, &sc->aud_ioh, NULL, 428 &aud_size)) { 429 aprint_error("%s: can't map device i/o space\n", 430 sc->sc_dev.dv_xname); 431 return; 432 } 433 } 434 } else { 435 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 436 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 437 aprint_error("%s: can't map codec i/o space\n", 438 sc->sc_dev.dv_xname); 439 return; 440 } 441 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 442 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 443 aprint_error("%s: can't map device i/o space\n", 444 sc->sc_dev.dv_xname); 445 return; 446 } 447 } 448 sc->dmat = pa->pa_dmat; 449 450 /* enable bus mastering */ 451 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 452 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 453 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 454 455 /* Map and establish the interrupt. */ 456 if (pci_intr_map(pa, &ih)) { 457 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 458 return; 459 } 460 intrstr = pci_intr_string(pa->pa_pc, ih); 461 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 462 auich_intr, sc); 463 if (sc->sc_ih == NULL) { 464 aprint_error("%s: can't establish interrupt", 465 sc->sc_dev.dv_xname); 466 if (intrstr != NULL) 467 aprint_normal(" at %s", intrstr); 468 aprint_normal("\n"); 469 return; 470 } 471 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 472 473 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 474 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 475 "0x%02x", PCI_REVISION(pa->pa_class)); 476 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 477 478 /* SiS 7012 needs special handling */ 479 if (d->id == PCIID_SIS7012) { 480 sc->sc_sts_reg = ICH_PICB; 481 sc->sc_sample_shift = 0; 482 } else { 483 sc->sc_sts_reg = ICH_STS; 484 sc->sc_sample_shift = 1; 485 } 486 487 /* Workaround for a 440MX B-stepping erratum */ 488 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 489 if (d->id == PCIID_440MX) { 490 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 491 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 492 } 493 494 /* Set up DMA lists. */ 495 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 496 auich_alloc_cdata(sc); 497 498 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 499 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 500 501 sc->host_if.arg = sc; 502 sc->host_if.attach = auich_attach_codec; 503 sc->host_if.read = auich_read_codec; 504 sc->host_if.write = auich_write_codec; 505 sc->host_if.reset = auich_reset_codec; 506 507 if (ac97_attach(&sc->host_if) != 0) 508 return; 509 510 /* Watch for power change */ 511 sc->sc_suspend = PWR_RESUME; 512 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 513 514 config_interrupts(self, auich_finish_attach); 515 516 /* sysctl setup */ 517 if (AC97_IS_FIXED_RATE(sc->codec_if)) 518 return; 519 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 520 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 521 CTL_HW, CTL_EOL); 522 if (err != 0) 523 goto sysctl_err; 524 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 525 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 526 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 527 if (err != 0) 528 goto sysctl_err; 529 node_mib = node->sysctl_num; 530 /* passing the sc address instead of &sc->sc_ac97_clock */ 531 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 532 CTLTYPE_INT, "ac97rate", 533 SYSCTL_DESCR("AC'97 codec link rate"), 534 auich_sysctl_verify, 0, sc, 0, 535 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 536 if (err != 0) 537 goto sysctl_err; 538 sc->sc_ac97_clock_mib = node->sysctl_num; 539 540 return; 541 542 sysctl_err: 543 printf("%s: failed to add sysctl nodes. (%d)\n", 544 sc->sc_dev.dv_xname, err); 545 return; /* failure of sysctl is not fatal. */ 546 } 547 548 #if 0 549 int 550 auich_detach(struct device *self, int flags) 551 { 552 struct auich_softc *sc; 553 554 sc = (struct auich_softc *)self; 555 /* sysctl */ 556 sysctl_teardown(&sc->sc_log); 557 /* audio */ 558 if (sc->sc_audiodev != NULL) 559 config_detach(sc->sc_audiodev, flags); 560 /* XXX ac97 */ 561 /* XXX memory */ 562 return 0; 563 } 564 #endif 565 566 static int 567 auich_sysctl_verify(SYSCTLFN_ARGS) 568 { 569 int error, tmp; 570 struct sysctlnode node; 571 struct auich_softc *sc; 572 573 node = *rnode; 574 sc = rnode->sysctl_data; 575 tmp = sc->sc_ac97_clock; 576 node.sysctl_data = &tmp; 577 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 578 if (error || newp == NULL) 579 return error; 580 581 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 582 if (tmp < 48000 || tmp > 96000) 583 return EINVAL; 584 sc->sc_ac97_clock = tmp; 585 } 586 587 return 0; 588 } 589 590 void 591 auich_finish_attach(struct device *self) 592 { 593 struct auich_softc *sc = (void *)self; 594 595 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 596 auich_calibrate(sc); 597 598 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 599 } 600 601 #define ICH_CODECIO_INTERVAL 10 602 int 603 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 604 { 605 struct auich_softc *sc = v; 606 int i; 607 uint32_t status; 608 609 /* wait for an access semaphore */ 610 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 611 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 612 DELAY(ICH_CODECIO_INTERVAL)); 613 614 if (i > 0) { 615 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 616 DPRINTF(ICH_DEBUG_CODECIO, 617 ("auich_read_codec(%x, %x)\n", reg, *val)); 618 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 619 if (status & ICH_RCS) { 620 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 621 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 622 *val = 0xffff; 623 DPRINTF(ICH_DEBUG_CODECIO, 624 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 625 return -1; 626 } 627 return 0; 628 } else { 629 DPRINTF(ICH_DEBUG_CODECIO, 630 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 631 return -1; 632 } 633 } 634 635 int 636 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 637 { 638 struct auich_softc *sc = v; 639 int i; 640 641 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 642 /* wait for an access semaphore */ 643 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 644 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 645 DELAY(ICH_CODECIO_INTERVAL)); 646 647 if (i > 0) { 648 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 649 return 0; 650 } else { 651 DPRINTF(ICH_DEBUG_CODECIO, 652 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 653 return -1; 654 } 655 } 656 657 int 658 auich_attach_codec(void *v, struct ac97_codec_if *cif) 659 { 660 struct auich_softc *sc = v; 661 662 sc->codec_if = cif; 663 return 0; 664 } 665 666 int 667 auich_reset_codec(void *v) 668 { 669 struct auich_softc *sc = v; 670 int i; 671 uint32_t control, status; 672 673 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 674 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 675 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 676 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 677 678 for (i = 500000; i >= 0; i--) { 679 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 680 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 681 break; 682 DELAY(1); 683 } 684 if (i <= 0) { 685 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 686 return ETIMEDOUT; 687 } 688 #ifdef DEBUG 689 if (status & ICH_SCR) 690 printf("%s: The 2nd codec is ready.\n", 691 sc->sc_dev.dv_xname); 692 if (status & ICH_S2CR) 693 printf("%s: The 3rd codec is ready.\n", 694 sc->sc_dev.dv_xname); 695 #endif 696 return 0; 697 } 698 699 int 700 auich_open(void *v, int flags) 701 { 702 return 0; 703 } 704 705 void 706 auich_close(void *v) 707 { 708 } 709 710 int 711 auich_query_encoding(void *v, struct audio_encoding *aep) 712 { 713 static const struct auich_encoding { 714 const char *name; 715 int encoding, precision, flags; 716 } *p, auich_encoding[] = { 717 {AudioEulinear, AUDIO_ENCODING_ULINEAR, 718 8, AUDIO_ENCODINGFLAG_EMULATED}, 719 {AudioEmulaw, AUDIO_ENCODING_ULAW, 720 8, AUDIO_ENCODINGFLAG_EMULATED}, 721 {AudioEalaw, AUDIO_ENCODING_ALAW, 722 8, AUDIO_ENCODINGFLAG_EMULATED}, 723 {AudioEslinear, AUDIO_ENCODING_SLINEAR, 724 8, AUDIO_ENCODINGFLAG_EMULATED}, 725 {AudioEslinear_le, AUDIO_ENCODING_SLINEAR_LE, 726 16, 0}, 727 {AudioEulinear_le, AUDIO_ENCODING_ULINEAR_LE, 728 16, AUDIO_ENCODINGFLAG_EMULATED}, 729 {AudioEslinear_be, AUDIO_ENCODING_SLINEAR_BE, 730 16, AUDIO_ENCODINGFLAG_EMULATED}, 731 {AudioEulinear_be, AUDIO_ENCODING_ULINEAR_BE, 732 16, AUDIO_ENCODINGFLAG_EMULATED}, 733 }; 734 735 if (aep->index >= 8) 736 return (EINVAL); 737 738 p = &auich_encoding[aep->index]; 739 strcpy(aep->name, p->name); 740 aep->encoding = p->encoding; 741 aep->precision = p->precision; 742 aep->flags = p->flags; 743 return (0); 744 } 745 746 int 747 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 748 { 749 int ret; 750 u_long ratetmp; 751 752 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 753 ratetmp = srate; 754 if (mode == AUMODE_RECORD) 755 return sc->codec_if->vtbl->set_rate(sc->codec_if, 756 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 757 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 758 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 759 if (ret) 760 return ret; 761 ratetmp = srate; 762 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 763 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 764 if (ret) 765 return ret; 766 ratetmp = srate; 767 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 768 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 769 return ret; 770 } 771 772 int 773 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 774 struct audio_params *rec) 775 { 776 struct auich_softc *sc = v; 777 struct audio_params *p; 778 int mode; 779 u_int32_t control; 780 781 for (mode = AUMODE_RECORD; mode != -1; 782 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 783 if ((setmode & mode) == 0) 784 continue; 785 786 p = mode == AUMODE_PLAY ? play : rec; 787 if (p == NULL) 788 continue; 789 790 if (p->sample_rate < 8000 || 791 p->sample_rate > 48000) 792 return (EINVAL); 793 794 if (p->precision == 8) 795 p->factor = 2; 796 else 797 p->factor = 1; 798 799 p->sw_code = NULL; 800 /* setup hardware formats */ 801 p->hw_encoding = AUDIO_ENCODING_SLINEAR_LE; 802 p->hw_precision = 16; 803 804 if (mode == AUMODE_RECORD) { 805 if (p->channels < 1 || p->channels > 2) 806 return EINVAL; 807 } else { 808 switch (p->channels) { 809 case 1: 810 break; 811 case 2: 812 break; 813 case 4: 814 if (!AC97_IS_4CH(sc->codec_if)) 815 return EINVAL; 816 break; 817 case 6: 818 if (!AC97_IS_6CH(sc->codec_if)) 819 return EINVAL; 820 break; 821 default: 822 return EINVAL; 823 } 824 } 825 /* If monaural is requested, aurateconv expands a monaural 826 * stream to stereo. */ 827 if (p->channels == 1) 828 p->hw_channels = 2; 829 830 switch (p->encoding) { 831 case AUDIO_ENCODING_SLINEAR_BE: 832 if (p->precision == 16) { 833 p->sw_code = swap_bytes; 834 } else { 835 if (mode == AUMODE_PLAY) 836 p->sw_code = linear8_to_linear16_le; 837 else 838 p->sw_code = linear16_to_linear8_le; 839 } 840 break; 841 842 case AUDIO_ENCODING_SLINEAR_LE: 843 if (p->precision != 16) { 844 if (mode == AUMODE_PLAY) 845 p->sw_code = linear8_to_linear16_le; 846 else 847 p->sw_code = linear16_to_linear8_le; 848 } 849 break; 850 851 case AUDIO_ENCODING_ULINEAR_BE: 852 if (p->precision == 16) { 853 if (mode == AUMODE_PLAY) 854 p->sw_code = 855 swap_bytes_change_sign16_le; 856 else 857 p->sw_code = 858 change_sign16_swap_bytes_le; 859 } else { 860 if (mode == AUMODE_PLAY) 861 p->sw_code = 862 ulinear8_to_slinear16_le; 863 else 864 p->sw_code = 865 slinear16_to_ulinear8_le; 866 } 867 break; 868 869 case AUDIO_ENCODING_ULINEAR_LE: 870 if (p->precision == 16) { 871 p->sw_code = change_sign16_le; 872 } else { 873 if (mode == AUMODE_PLAY) 874 p->sw_code = 875 ulinear8_to_slinear16_le; 876 else 877 p->sw_code = 878 slinear16_to_ulinear8_le; 879 } 880 break; 881 882 case AUDIO_ENCODING_ULAW: 883 if (mode == AUMODE_PLAY) { 884 p->sw_code = mulaw_to_slinear16_le; 885 } else { 886 p->sw_code = slinear16_to_mulaw_le; 887 } 888 break; 889 890 case AUDIO_ENCODING_ALAW: 891 if (mode == AUMODE_PLAY) { 892 p->sw_code = alaw_to_slinear16_le; 893 } else { 894 p->sw_code = slinear16_to_alaw_le; 895 } 896 break; 897 898 default: 899 return (EINVAL); 900 } 901 902 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 903 p->hw_sample_rate = AC97_SINGLE_RATE; 904 /* If hw_sample_rate is changed, aurateconv works. */ 905 } else { 906 if (auich_set_rate(sc, mode, p->sample_rate)) 907 return EINVAL; 908 } 909 if (mode == AUMODE_PLAY) { 910 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 911 control &= ~ICH_PCM246_MASK; 912 if (p->channels == 4) { 913 control |= ICH_PCM4; 914 } else if (p->channels == 6) { 915 control |= ICH_PCM6; 916 } 917 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 918 } 919 } 920 921 return (0); 922 } 923 924 int 925 auich_round_blocksize(void *v, int blk) 926 { 927 928 return (blk & ~0x3f); /* keep good alignment */ 929 } 930 931 int 932 auich_halt_output(void *v) 933 { 934 struct auich_softc *sc = v; 935 936 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 937 938 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 939 sc->pcmo.intr = NULL; 940 941 return (0); 942 } 943 944 int 945 auich_halt_input(void *v) 946 { 947 struct auich_softc *sc = v; 948 949 DPRINTF(ICH_DEBUG_DMA, 950 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 951 952 /* XXX halt both unless known otherwise */ 953 954 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 955 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 956 sc->pcmi.intr = NULL; 957 958 return (0); 959 } 960 961 int 962 auich_getdev(void *v, struct audio_device *adp) 963 { 964 struct auich_softc *sc = v; 965 966 *adp = sc->sc_audev; 967 return (0); 968 } 969 970 int 971 auich_set_port(void *v, mixer_ctrl_t *cp) 972 { 973 struct auich_softc *sc = v; 974 975 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 976 } 977 978 int 979 auich_get_port(void *v, mixer_ctrl_t *cp) 980 { 981 struct auich_softc *sc = v; 982 983 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 984 } 985 986 int 987 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 988 { 989 struct auich_softc *sc = v; 990 991 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 992 } 993 994 void * 995 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 996 int flags) 997 { 998 struct auich_softc *sc = v; 999 struct auich_dma *p; 1000 int error; 1001 1002 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1003 return (NULL); 1004 1005 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1006 if (p == NULL) 1007 return (NULL); 1008 1009 error = auich_allocmem(sc, size, 0, p); 1010 if (error) { 1011 free(p, pool); 1012 return (NULL); 1013 } 1014 1015 p->next = sc->sc_dmas; 1016 sc->sc_dmas = p; 1017 1018 return (KERNADDR(p)); 1019 } 1020 1021 void 1022 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1023 { 1024 struct auich_softc *sc = v; 1025 struct auich_dma *p, **pp; 1026 1027 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1028 if (KERNADDR(p) == ptr) { 1029 auich_freemem(sc, p); 1030 *pp = p->next; 1031 free(p, pool); 1032 return; 1033 } 1034 } 1035 } 1036 1037 size_t 1038 auich_round_buffersize(void *v, int direction, size_t size) 1039 { 1040 1041 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1042 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1043 1044 return size; 1045 } 1046 1047 paddr_t 1048 auich_mappage(void *v, void *mem, off_t off, int prot) 1049 { 1050 struct auich_softc *sc = v; 1051 struct auich_dma *p; 1052 1053 if (off < 0) 1054 return (-1); 1055 1056 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1057 ; 1058 if (!p) 1059 return (-1); 1060 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1061 off, prot, BUS_DMA_WAITOK)); 1062 } 1063 1064 int 1065 auich_get_props(void *v) 1066 { 1067 struct auich_softc *sc = v; 1068 int props; 1069 1070 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1071 /* 1072 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1073 * rate because of aurateconv. Applications can't know what rate the 1074 * device can process in the case of mmap(). 1075 */ 1076 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 1077 props |= AUDIO_PROP_MMAP; 1078 return props; 1079 } 1080 1081 int 1082 auich_intr(void *v) 1083 { 1084 struct auich_softc *sc = v; 1085 int ret = 0, gsts; 1086 1087 #ifdef DIAGNOSTIC 1088 int csts; 1089 #endif 1090 1091 #ifdef DIAGNOSTIC 1092 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1093 if (csts & PCI_STATUS_MASTER_ABORT) { 1094 printf("auich_intr: PCI master abort\n"); 1095 } 1096 #endif 1097 1098 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 1099 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1100 1101 if (gsts & ICH_POINT) { 1102 int sts; 1103 1104 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1105 ICH_PCMO + sc->sc_sts_reg); 1106 DPRINTF(ICH_DEBUG_INTR, 1107 ("auich_intr: osts=0x%x\n", sts)); 1108 1109 if (sts & ICH_FIFOE) 1110 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1111 1112 if (sts & ICH_BCIS) { 1113 struct auich_dmalist *q; 1114 int blksize, qptr, i; 1115 1116 blksize = sc->pcmo.blksize; 1117 qptr = sc->pcmo.qptr; 1118 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1119 ICH_PCMO + ICH_CIV); 1120 1121 while (qptr != i) { 1122 q = &sc->pcmo.dmalist[qptr]; 1123 1124 q->base = sc->pcmo.p; 1125 q->len = (blksize >> sc->sc_sample_shift) | 1126 ICH_DMAF_IOC; 1127 DPRINTF(ICH_DEBUG_INTR, 1128 ("auich_intr: %p, %p = %x @ 0x%x\n", 1129 &sc->pcmo.dmalist[i], q, q->len, q->base)); 1130 1131 sc->pcmo.p += blksize; 1132 if (sc->pcmo.p >= sc->pcmo.end) 1133 sc->pcmo.p = sc->pcmo.start; 1134 1135 qptr = (qptr + 1) & ICH_LVI_MASK; 1136 if (sc->pcmo.intr) 1137 sc->pcmo.intr(sc->pcmo.arg); 1138 } 1139 1140 sc->pcmo.qptr = qptr; 1141 bus_space_write_1(sc->iot, sc->aud_ioh, 1142 ICH_PCMO + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1143 } 1144 1145 /* int ack */ 1146 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1147 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1148 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1149 ret++; 1150 } 1151 1152 if (gsts & ICH_PIINT) { 1153 int sts; 1154 1155 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1156 ICH_PCMI + sc->sc_sts_reg); 1157 DPRINTF(ICH_DEBUG_INTR, 1158 ("auich_intr: ists=0x%x\n", sts)); 1159 1160 if (sts & ICH_FIFOE) 1161 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1162 1163 if (sts & ICH_BCIS) { 1164 struct auich_dmalist *q; 1165 int blksize, qptr, i; 1166 1167 blksize = sc->pcmi.blksize; 1168 qptr = sc->pcmi.qptr; 1169 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1170 ICH_PCMI + ICH_CIV); 1171 1172 while (qptr != i) { 1173 q = &sc->pcmi.dmalist[qptr]; 1174 1175 q->base = sc->pcmi.p; 1176 q->len = (blksize >> sc->sc_sample_shift) | 1177 ICH_DMAF_IOC; 1178 DPRINTF(ICH_DEBUG_INTR, 1179 ("auich_intr: %p, %p = %x @ 0x%x\n", 1180 &sc->pcmi.dmalist[i], q, q->len, q->base)); 1181 1182 sc->pcmi.p += blksize; 1183 if (sc->pcmi.p >= sc->pcmi.end) 1184 sc->pcmi.p = sc->pcmi.start; 1185 1186 qptr = (qptr + 1) & ICH_LVI_MASK; 1187 if (sc->pcmi.intr) 1188 sc->pcmi.intr(sc->pcmi.arg); 1189 } 1190 1191 sc->pcmi.qptr = qptr; 1192 bus_space_write_1(sc->iot, sc->aud_ioh, 1193 ICH_PCMI + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1194 } 1195 1196 /* int ack */ 1197 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1198 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1199 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1200 ret++; 1201 } 1202 1203 if (gsts & ICH_MIINT) { 1204 int sts; 1205 1206 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1207 ICH_MICI + sc->sc_sts_reg); 1208 DPRINTF(ICH_DEBUG_INTR, 1209 ("auich_intr: ists=0x%x\n", sts)); 1210 1211 if (sts & ICH_FIFOE) 1212 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1213 1214 /* TODO mic input DMA */ 1215 1216 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1217 } 1218 1219 return ret; 1220 } 1221 1222 int 1223 auich_trigger_output(void *v, void *start, void *end, int blksize, 1224 void (*intr)(void *), void *arg, struct audio_params *param) 1225 { 1226 struct auich_softc *sc = v; 1227 struct auich_dmalist *q; 1228 struct auich_dma *p; 1229 size_t size; 1230 int qptr; 1231 #ifdef DIAGNOSTIC 1232 int csts; 1233 #endif 1234 1235 DPRINTF(ICH_DEBUG_DMA, 1236 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1237 start, end, blksize, intr, arg, param)); 1238 1239 sc->pcmo.intr = intr; 1240 sc->pcmo.arg = arg; 1241 #ifdef DIAGNOSTIC 1242 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1243 if (csts & PCI_STATUS_MASTER_ABORT) { 1244 printf("auich_trigger_output: PCI master abort\n"); 1245 } 1246 #endif 1247 1248 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1249 ; 1250 if (!p) { 1251 printf("auich_trigger_output: bad addr %p\n", start); 1252 return (EINVAL); 1253 } 1254 1255 size = (size_t)((caddr_t)end - (caddr_t)start); 1256 1257 /* 1258 * The logic behind this is: 1259 * setup one buffer to play, then LVI dump out the rest 1260 * to the scatter-gather chain. 1261 */ 1262 sc->pcmo.start = DMAADDR(p); 1263 sc->pcmo.p = sc->pcmo.start; 1264 sc->pcmo.end = sc->pcmo.start + size; 1265 sc->pcmo.blksize = blksize; 1266 1267 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1268 q = &sc->pcmo.dmalist[qptr]; 1269 1270 q->base = sc->pcmo.p; 1271 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1272 1273 sc->pcmo.p += blksize; 1274 if (sc->pcmo.p >= sc->pcmo.end) 1275 sc->pcmo.p = sc->pcmo.start; 1276 } 1277 1278 sc->pcmo.qptr = qptr = 0; 1279 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1280 (qptr - 1) & ICH_LVI_MASK); 1281 1282 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1283 sc->sc_cddma + ICH_PCMO_OFF(0)); 1284 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1285 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1286 1287 return (0); 1288 } 1289 1290 int 1291 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1292 void *v; 1293 void *start, *end; 1294 int blksize; 1295 void (*intr)(void *); 1296 void *arg; 1297 struct audio_params *param; 1298 { 1299 struct auich_softc *sc = v; 1300 struct auich_dmalist *q; 1301 struct auich_dma *p; 1302 size_t size; 1303 int qptr; 1304 #ifdef DIAGNOSTIC 1305 int csts; 1306 #endif 1307 1308 DPRINTF(ICH_DEBUG_DMA, 1309 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1310 start, end, blksize, intr, arg, param)); 1311 1312 sc->pcmi.intr = intr; 1313 sc->pcmi.arg = arg; 1314 1315 #ifdef DIAGNOSTIC 1316 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1317 if (csts & PCI_STATUS_MASTER_ABORT) { 1318 printf("auich_trigger_input: PCI master abort\n"); 1319 } 1320 #endif 1321 1322 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1323 ; 1324 if (!p) { 1325 printf("auich_trigger_input: bad addr %p\n", start); 1326 return (EINVAL); 1327 } 1328 1329 size = (size_t)((caddr_t)end - (caddr_t)start); 1330 1331 /* 1332 * The logic behind this is: 1333 * setup one buffer to play, then LVI dump out the rest 1334 * to the scatter-gather chain. 1335 */ 1336 sc->pcmi.start = DMAADDR(p); 1337 sc->pcmi.p = sc->pcmi.start; 1338 sc->pcmi.end = sc->pcmi.start + size; 1339 sc->pcmi.blksize = blksize; 1340 1341 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1342 q = &sc->pcmi.dmalist[qptr]; 1343 1344 q->base = sc->pcmi.p; 1345 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1346 1347 sc->pcmi.p += blksize; 1348 if (sc->pcmi.p >= sc->pcmi.end) 1349 sc->pcmi.p = sc->pcmi.start; 1350 } 1351 1352 sc->pcmi.qptr = qptr = 0; 1353 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1354 (qptr - 1) & ICH_LVI_MASK); 1355 1356 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1357 sc->sc_cddma + ICH_PCMI_OFF(0)); 1358 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1359 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1360 1361 return (0); 1362 } 1363 1364 int 1365 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1366 struct auich_dma *p) 1367 { 1368 int error; 1369 1370 p->size = size; 1371 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1372 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1373 &p->nsegs, BUS_DMA_NOWAIT); 1374 if (error) 1375 return (error); 1376 1377 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1378 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1379 if (error) 1380 goto free; 1381 1382 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1383 0, BUS_DMA_NOWAIT, &p->map); 1384 if (error) 1385 goto unmap; 1386 1387 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1388 BUS_DMA_NOWAIT); 1389 if (error) 1390 goto destroy; 1391 return (0); 1392 1393 destroy: 1394 bus_dmamap_destroy(sc->dmat, p->map); 1395 unmap: 1396 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1397 free: 1398 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1399 return (error); 1400 } 1401 1402 int 1403 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1404 { 1405 1406 bus_dmamap_unload(sc->dmat, p->map); 1407 bus_dmamap_destroy(sc->dmat, p->map); 1408 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1409 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1410 return (0); 1411 } 1412 1413 int 1414 auich_alloc_cdata(struct auich_softc *sc) 1415 { 1416 bus_dma_segment_t seg; 1417 int error, rseg; 1418 1419 /* 1420 * Allocate the control data structure, and create and load the 1421 * DMA map for it. 1422 */ 1423 if ((error = bus_dmamem_alloc(sc->dmat, 1424 sizeof(struct auich_cdata), 1425 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1426 printf("%s: unable to allocate control data, error = %d\n", 1427 sc->sc_dev.dv_xname, error); 1428 goto fail_0; 1429 } 1430 1431 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1432 sizeof(struct auich_cdata), 1433 (caddr_t *) &sc->sc_cdata, 1434 sc->sc_dmamap_flags)) != 0) { 1435 printf("%s: unable to map control data, error = %d\n", 1436 sc->sc_dev.dv_xname, error); 1437 goto fail_1; 1438 } 1439 1440 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1441 sizeof(struct auich_cdata), 0, 0, 1442 &sc->sc_cddmamap)) != 0) { 1443 printf("%s: unable to create control data DMA map, " 1444 "error = %d\n", sc->sc_dev.dv_xname, error); 1445 goto fail_2; 1446 } 1447 1448 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1449 sc->sc_cdata, sizeof(struct auich_cdata), 1450 NULL, 0)) != 0) { 1451 printf("%s: unable tp load control data DMA map, " 1452 "error = %d\n", sc->sc_dev.dv_xname, error); 1453 goto fail_3; 1454 } 1455 1456 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1457 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1458 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1459 1460 return (0); 1461 1462 fail_3: 1463 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1464 fail_2: 1465 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1466 sizeof(struct auich_cdata)); 1467 fail_1: 1468 bus_dmamem_free(sc->dmat, &seg, rseg); 1469 fail_0: 1470 return (error); 1471 } 1472 1473 void 1474 auich_powerhook(int why, void *addr) 1475 { 1476 struct auich_softc *sc = (struct auich_softc *)addr; 1477 1478 switch (why) { 1479 case PWR_SUSPEND: 1480 case PWR_STANDBY: 1481 /* Power down */ 1482 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1483 sc->sc_suspend = why; 1484 break; 1485 1486 case PWR_RESUME: 1487 /* Wake up */ 1488 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1489 if (sc->sc_suspend == PWR_RESUME) { 1490 printf("%s: resume without suspend.\n", 1491 sc->sc_dev.dv_xname); 1492 sc->sc_suspend = why; 1493 return; 1494 } 1495 sc->sc_suspend = why; 1496 auich_reset_codec(sc); 1497 DELAY(1000); 1498 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1499 break; 1500 1501 case PWR_SOFTSUSPEND: 1502 case PWR_SOFTSTANDBY: 1503 case PWR_SOFTRESUME: 1504 break; 1505 } 1506 } 1507 1508 /* 1509 * Calibrate card (some boards are overclocked and need scaling) 1510 */ 1511 void 1512 auich_calibrate(struct auich_softc *sc) 1513 { 1514 struct timeval t1, t2; 1515 uint8_t ociv, nciv; 1516 uint64_t wait_us; 1517 uint32_t actual_48k_rate, bytes, ac97rate; 1518 void *temp_buffer; 1519 struct auich_dma *p; 1520 u_long rate; 1521 1522 /* 1523 * Grab audio from input for fixed interval and compare how 1524 * much we actually get with what we expect. Interval needs 1525 * to be sufficiently short that no interrupts are 1526 * generated. 1527 */ 1528 1529 /* Force the codec to a known state first. */ 1530 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1531 rate = sc->sc_ac97_clock = 48000; 1532 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1533 &rate); 1534 1535 /* Setup a buffer */ 1536 bytes = 64000; 1537 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1538 1539 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1540 ; 1541 if (p == NULL) { 1542 printf("auich_calibrate: bad address %p\n", temp_buffer); 1543 return; 1544 } 1545 sc->pcmi.dmalist[0].base = DMAADDR(p); 1546 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1547 1548 /* 1549 * our data format is stereo, 16 bit so each sample is 4 bytes. 1550 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1551 * we're going to start recording with interrupts disabled and measure 1552 * the time taken for one block to complete. we know the block size, 1553 * we know the time in microseconds, we calculate the sample rate: 1554 * 1555 * actual_rate [bps] = bytes / (time [s] * 4) 1556 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1557 * actual_rate [Hz] = (bytes * 250000) / time [us] 1558 */ 1559 1560 /* prepare */ 1561 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1562 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1563 sc->sc_cddma + ICH_PCMI_OFF(0)); 1564 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1565 (0 - 1) & ICH_LVI_MASK); 1566 1567 /* start */ 1568 microtime(&t1); 1569 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1570 1571 /* wait */ 1572 nciv = ociv; 1573 do { 1574 microtime(&t2); 1575 if (t2.tv_sec - t1.tv_sec > 1) 1576 break; 1577 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1578 ICH_PCMI + ICH_CIV); 1579 } while (nciv == ociv); 1580 microtime(&t2); 1581 1582 /* stop */ 1583 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1584 1585 /* reset */ 1586 DELAY(100); 1587 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1588 1589 /* turn time delta into us */ 1590 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1591 1592 auich_freem(sc, temp_buffer, M_DEVBUF); 1593 1594 if (nciv == ociv) { 1595 printf("%s: ac97 link rate calibration timed out after %" 1596 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1597 return; 1598 } 1599 1600 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1601 1602 if (actual_48k_rate < 50000) 1603 ac97rate = 48000; 1604 else 1605 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1606 1607 printf("%s: measured ac97 link rate at %d Hz", 1608 sc->sc_dev.dv_xname, actual_48k_rate); 1609 if (ac97rate != actual_48k_rate) 1610 printf(", will use %d Hz", ac97rate); 1611 printf("\n"); 1612 1613 sc->sc_ac97_clock = ac97rate; 1614 } 1615
Indexes created Thu Oct 23 22:10:10 GMT 2025