auich.c revision 1.83
1 /* $NetBSD: auich.c,v 1.83 2004/12/11 17:48:56 cube Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.83 2004/12/11 17:48:56 cube Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 187 struct ac97_codec_if *codec_if; 188 struct ac97_host_if host_if; 189 190 /* DMA scatter-gather lists. */ 191 bus_dmamap_t sc_cddmamap; 192 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 193 194 struct auich_cdata *sc_cdata; 195 196 struct auich_ring { 197 int qptr; 198 struct auich_dmalist *dmalist; 199 200 u_int32_t start, p, end; 201 int blksize; 202 203 void (*intr)(void *); 204 void *arg; 205 } pcmo, pcmi, mici; 206 207 struct auich_dma *sc_dmas; 208 209 /* SiS 7012 hack */ 210 int sc_sample_shift; 211 int sc_sts_reg; 212 /* 440MX workaround */ 213 int sc_dmamap_flags; 214 215 /* Power Management */ 216 void *sc_powerhook; 217 int sc_suspend; 218 219 /* sysctl */ 220 struct sysctllog *sc_log; 221 uint32_t sc_ac97_clock; 222 int sc_ac97_clock_mib; 223 224 #define AUICH_NFORMATS 3 225 struct audio_format sc_formats[AUICH_NFORMATS]; 226 struct audio_encoding_set *sc_encodings; 227 }; 228 229 /* Debug */ 230 #ifdef AUICH_DEBUG 231 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 232 int auich_debug = 0xfffe; 233 #define ICH_DEBUG_CODECIO 0x0001 234 #define ICH_DEBUG_DMA 0x0002 235 #define ICH_DEBUG_INTR 0x0004 236 #else 237 #define DPRINTF(x,y) /* nothing */ 238 #endif 239 240 static int auich_match(struct device *, struct cfdata *, void *); 241 static void auich_attach(struct device *, struct device *, void *); 242 static int auich_detach(struct device *, int); 243 static int auich_activate(struct device *, enum devact); 244 static int auich_intr(void *); 245 246 CFATTACH_DECL(auich, sizeof(struct auich_softc), 247 auich_match, auich_attach, auich_detach, auich_activate); 248 249 static int auich_open(void *, int); 250 static void auich_close(void *); 251 static int auich_query_encoding(void *, struct audio_encoding *); 252 static int auich_set_params(void *, int, int, struct audio_params *, 253 struct audio_params *); 254 static int auich_round_blocksize(void *, int); 255 static int auich_halt_output(void *); 256 static int auich_halt_input(void *); 257 static int auich_getdev(void *, struct audio_device *); 258 static int auich_set_port(void *, mixer_ctrl_t *); 259 static int auich_get_port(void *, mixer_ctrl_t *); 260 static int auich_query_devinfo(void *, mixer_devinfo_t *); 261 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 262 static void auich_freem(void *, void *, struct malloc_type *); 263 static size_t auich_round_buffersize(void *, int, size_t); 264 static paddr_t auich_mappage(void *, void *, off_t, int); 265 static int auich_get_props(void *); 266 static int auich_trigger_output(void *, void *, void *, int, 267 void (*)(void *), void *, struct audio_params *); 268 static int auich_trigger_input(void *, void *, void *, int, 269 void (*)(void *), void *, struct audio_params *); 270 271 static int auich_alloc_cdata(struct auich_softc *); 272 273 static int auich_allocmem(struct auich_softc *, size_t, size_t, 274 struct auich_dma *); 275 static int auich_freemem(struct auich_softc *, struct auich_dma *); 276 277 static void auich_powerhook(int, void *); 278 static int auich_set_rate(struct auich_softc *, int, u_long); 279 static int auich_sysctl_verify(SYSCTLFN_ARGS); 280 static void auich_finish_attach(struct device *); 281 static void auich_calibrate(struct auich_softc *); 282 283 static int auich_attach_codec(void *, struct ac97_codec_if *); 284 static int auich_read_codec(void *, u_int8_t, u_int16_t *); 285 static int auich_write_codec(void *, u_int8_t, u_int16_t); 286 static int auich_reset_codec(void *); 287 288 const struct audio_hw_if auich_hw_if = { 289 auich_open, 290 auich_close, 291 NULL, /* drain */ 292 auich_query_encoding, 293 auich_set_params, 294 auich_round_blocksize, 295 NULL, /* commit_setting */ 296 NULL, /* init_output */ 297 NULL, /* init_input */ 298 NULL, /* start_output */ 299 NULL, /* start_input */ 300 auich_halt_output, 301 auich_halt_input, 302 NULL, /* speaker_ctl */ 303 auich_getdev, 304 NULL, /* getfd */ 305 auich_set_port, 306 auich_get_port, 307 auich_query_devinfo, 308 auich_allocm, 309 auich_freem, 310 auich_round_buffersize, 311 auich_mappage, 312 auich_get_props, 313 auich_trigger_output, 314 auich_trigger_input, 315 NULL, /* dev_ioctl */ 316 }; 317 318 #define AUICH_FORMATS_4CH 1 319 #define AUICH_FORMATS_6CH 2 320 static const struct audio_format auich_formats[AUICH_NFORMATS] = { 321 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 322 2, AUFMT_STEREO, 0, {8000, 48000}}, 323 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 324 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 325 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 326 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 327 }; 328 329 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 330 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 331 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 332 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 333 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 334 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 335 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 336 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 337 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 338 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 339 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 340 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 341 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 342 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 343 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 344 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 345 346 static const struct auich_devtype { 347 pcireg_t id; 348 const char *name; 349 const char *shortname; /* must be less than 11 characters */ 350 } auich_devices[] = { 351 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 352 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 353 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 354 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 355 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 356 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 357 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 358 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 359 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 360 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 361 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 362 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 363 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 364 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 365 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 366 { 0, NULL, NULL }, 367 }; 368 369 static const struct auich_devtype * 370 auich_lookup(struct pci_attach_args *pa) 371 { 372 const struct auich_devtype *d; 373 374 for (d = auich_devices; d->name != NULL; d++) { 375 if (pa->pa_id == d->id) 376 return (d); 377 } 378 379 return (NULL); 380 } 381 382 static int 383 auich_match(struct device *parent, struct cfdata *match, void *aux) 384 { 385 struct pci_attach_args *pa = aux; 386 387 if (auich_lookup(pa) != NULL) 388 return (1); 389 390 return (0); 391 } 392 393 static void 394 auich_attach(struct device *parent, struct device *self, void *aux) 395 { 396 struct auich_softc *sc = (struct auich_softc *)self; 397 struct pci_attach_args *pa = aux; 398 pci_intr_handle_t ih; 399 pcireg_t v; 400 const char *intrstr; 401 const struct auich_devtype *d; 402 struct sysctlnode *node; 403 int err, node_mib, i; 404 405 aprint_naive(": Audio controller\n"); 406 407 d = auich_lookup(pa); 408 if (d == NULL) 409 panic("auich_attach: impossible"); 410 411 sc->sc_pc = pa->pa_pc; 412 sc->sc_pt = pa->pa_tag; 413 414 aprint_normal(": %s\n", d->name); 415 416 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6) { 417 /* 418 * Use native mode for ICH4/ICH5/ICH6 419 */ 420 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 421 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 422 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 423 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 424 v | ICH_CFG_IOSE); 425 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 426 0, &sc->iot, &sc->mix_ioh, NULL, 427 &sc->mix_size)) { 428 aprint_error("%s: can't map codec i/o space\n", 429 sc->sc_dev.dv_xname); 430 return; 431 } 432 } 433 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 434 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 435 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 436 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 437 v | ICH_CFG_IOSE); 438 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 439 0, &sc->iot, &sc->aud_ioh, NULL, 440 &sc->aud_size)) { 441 aprint_error("%s: can't map device i/o space\n", 442 sc->sc_dev.dv_xname); 443 return; 444 } 445 } 446 } else { 447 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 448 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 449 aprint_error("%s: can't map codec i/o space\n", 450 sc->sc_dev.dv_xname); 451 return; 452 } 453 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 454 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 455 aprint_error("%s: can't map device i/o space\n", 456 sc->sc_dev.dv_xname); 457 return; 458 } 459 } 460 sc->dmat = pa->pa_dmat; 461 462 /* enable bus mastering */ 463 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 464 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 465 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 466 467 /* Map and establish the interrupt. */ 468 if (pci_intr_map(pa, &ih)) { 469 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 470 return; 471 } 472 intrstr = pci_intr_string(pa->pa_pc, ih); 473 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 474 auich_intr, sc); 475 if (sc->sc_ih == NULL) { 476 aprint_error("%s: can't establish interrupt", 477 sc->sc_dev.dv_xname); 478 if (intrstr != NULL) 479 aprint_normal(" at %s", intrstr); 480 aprint_normal("\n"); 481 return; 482 } 483 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 484 485 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 486 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 487 "0x%02x", PCI_REVISION(pa->pa_class)); 488 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 489 490 /* SiS 7012 needs special handling */ 491 if (d->id == PCIID_SIS7012) { 492 sc->sc_sts_reg = ICH_PICB; 493 sc->sc_sample_shift = 0; 494 /* Un-mute output. From Linux. */ 495 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 496 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 497 ICH_SIS_CTL_UNMUTE); 498 } else { 499 sc->sc_sts_reg = ICH_STS; 500 sc->sc_sample_shift = 1; 501 } 502 503 /* Workaround for a 440MX B-stepping erratum */ 504 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 505 if (d->id == PCIID_440MX) { 506 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 507 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 508 } 509 510 /* Set up DMA lists. */ 511 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 512 auich_alloc_cdata(sc); 513 514 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 515 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 516 517 sc->host_if.arg = sc; 518 sc->host_if.attach = auich_attach_codec; 519 sc->host_if.read = auich_read_codec; 520 sc->host_if.write = auich_write_codec; 521 sc->host_if.reset = auich_reset_codec; 522 523 if (ac97_attach(&sc->host_if) != 0) 524 return; 525 526 /* setup audio_format */ 527 memcpy(sc->sc_formats, auich_formats, sizeof(auich_formats)); 528 if (!AC97_IS_4CH(sc->codec_if)) 529 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_4CH]); 530 if (!AC97_IS_6CH(sc->codec_if)) 531 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_6CH]); 532 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 533 for (i = 0; i < AUICH_NFORMATS; i++) { 534 sc->sc_formats[i].frequency_type = 1; 535 sc->sc_formats[i].frequency[0] = 48000; 536 } 537 } 538 539 if (0 != auconv_create_encodings(sc->sc_formats, AUICH_NFORMATS, 540 &sc->sc_encodings)) { 541 return; 542 } 543 544 /* Watch for power change */ 545 sc->sc_suspend = PWR_RESUME; 546 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 547 548 config_interrupts(self, auich_finish_attach); 549 550 /* sysctl setup */ 551 if (AC97_IS_FIXED_RATE(sc->codec_if)) 552 return; 553 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 554 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 555 CTL_HW, CTL_EOL); 556 if (err != 0) 557 goto sysctl_err; 558 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 559 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 560 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 561 if (err != 0) 562 goto sysctl_err; 563 node_mib = node->sysctl_num; 564 /* passing the sc address instead of &sc->sc_ac97_clock */ 565 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 566 CTLTYPE_INT, "ac97rate", 567 SYSCTL_DESCR("AC'97 codec link rate"), 568 auich_sysctl_verify, 0, sc, 0, 569 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 570 if (err != 0) 571 goto sysctl_err; 572 sc->sc_ac97_clock_mib = node->sysctl_num; 573 574 return; 575 576 sysctl_err: 577 printf("%s: failed to add sysctl nodes. (%d)\n", 578 sc->sc_dev.dv_xname, err); 579 return; /* failure of sysctl is not fatal. */ 580 } 581 582 static int 583 auich_activate(struct device *self, enum devact act) 584 { 585 struct auich_softc *sc; 586 int ret; 587 588 sc = (struct auich_softc *)self; 589 ret = 0; 590 switch (act) { 591 case DVACT_ACTIVATE: 592 return EOPNOTSUPP; 593 case DVACT_DEACTIVATE: 594 if (sc->sc_audiodev != NULL) 595 ret = config_deactivate(sc->sc_audiodev); 596 return ret; 597 } 598 return EOPNOTSUPP; 599 } 600 601 static int 602 auich_detach(struct device *self, int flags) 603 { 604 struct auich_softc *sc; 605 606 sc = (struct auich_softc *)self; 607 608 /* audio */ 609 if (sc->sc_audiodev != NULL) 610 config_detach(sc->sc_audiodev, flags); 611 612 /* sysctl */ 613 sysctl_teardown(&sc->sc_log); 614 615 /* audio_encoding_set */ 616 auconv_delete_encodings(sc->sc_encodings); 617 618 /* ac97 */ 619 if (sc->codec_if != NULL) 620 sc->codec_if->vtbl->detach(sc->codec_if); 621 622 /* PCI */ 623 if (sc->sc_ih != NULL) 624 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 625 if (sc->mix_size != 0) 626 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 627 if (sc->aud_size != 0) 628 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 629 return 0; 630 } 631 632 static int 633 auich_sysctl_verify(SYSCTLFN_ARGS) 634 { 635 int error, tmp; 636 struct sysctlnode node; 637 struct auich_softc *sc; 638 639 node = *rnode; 640 sc = rnode->sysctl_data; 641 tmp = sc->sc_ac97_clock; 642 node.sysctl_data = &tmp; 643 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 644 if (error || newp == NULL) 645 return error; 646 647 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 648 if (tmp < 48000 || tmp > 96000) 649 return EINVAL; 650 sc->sc_ac97_clock = tmp; 651 } 652 653 return 0; 654 } 655 656 static void 657 auich_finish_attach(struct device *self) 658 { 659 struct auich_softc *sc = (void *)self; 660 661 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 662 auich_calibrate(sc); 663 664 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 665 } 666 667 #define ICH_CODECIO_INTERVAL 10 668 static int 669 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 670 { 671 struct auich_softc *sc = v; 672 int i; 673 uint32_t status; 674 675 /* wait for an access semaphore */ 676 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 677 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 678 DELAY(ICH_CODECIO_INTERVAL)); 679 680 if (i > 0) { 681 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 682 DPRINTF(ICH_DEBUG_CODECIO, 683 ("auich_read_codec(%x, %x)\n", reg, *val)); 684 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 685 if (status & ICH_RCS) { 686 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 687 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 688 *val = 0xffff; 689 DPRINTF(ICH_DEBUG_CODECIO, 690 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 691 return -1; 692 } 693 return 0; 694 } else { 695 DPRINTF(ICH_DEBUG_CODECIO, 696 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 697 return -1; 698 } 699 } 700 701 static int 702 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 703 { 704 struct auich_softc *sc = v; 705 int i; 706 707 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 708 /* wait for an access semaphore */ 709 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 710 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 711 DELAY(ICH_CODECIO_INTERVAL)); 712 713 if (i > 0) { 714 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 715 return 0; 716 } else { 717 DPRINTF(ICH_DEBUG_CODECIO, 718 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 719 return -1; 720 } 721 } 722 723 static int 724 auich_attach_codec(void *v, struct ac97_codec_if *cif) 725 { 726 struct auich_softc *sc = v; 727 728 sc->codec_if = cif; 729 return 0; 730 } 731 732 static int 733 auich_reset_codec(void *v) 734 { 735 struct auich_softc *sc = v; 736 int i; 737 uint32_t control, status; 738 739 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 740 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 741 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 742 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 743 744 for (i = 500000; i >= 0; i--) { 745 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 746 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 747 break; 748 DELAY(1); 749 } 750 if (i <= 0) { 751 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 752 return ETIMEDOUT; 753 } 754 #ifdef DEBUG 755 if (status & ICH_SCR) 756 printf("%s: The 2nd codec is ready.\n", 757 sc->sc_dev.dv_xname); 758 if (status & ICH_S2CR) 759 printf("%s: The 3rd codec is ready.\n", 760 sc->sc_dev.dv_xname); 761 #endif 762 return 0; 763 } 764 765 static int 766 auich_open(void *v, int flags) 767 { 768 return 0; 769 } 770 771 static void 772 auich_close(void *v) 773 { 774 } 775 776 static int 777 auich_query_encoding(void *v, struct audio_encoding *aep) 778 { 779 struct auich_softc *sc; 780 781 sc = (struct auich_softc *)v; 782 return auconv_query_encoding(sc->sc_encodings, aep); 783 } 784 785 static int 786 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 787 { 788 int ret; 789 u_long ratetmp; 790 791 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 792 ratetmp = srate; 793 if (mode == AUMODE_RECORD) 794 return sc->codec_if->vtbl->set_rate(sc->codec_if, 795 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 796 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 797 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 798 if (ret) 799 return ret; 800 ratetmp = srate; 801 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 802 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 803 if (ret) 804 return ret; 805 ratetmp = srate; 806 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 807 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 808 return ret; 809 } 810 811 static int 812 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 813 struct audio_params *rec) 814 { 815 struct auich_softc *sc = v; 816 struct audio_params *p; 817 int mode, index; 818 u_int32_t control; 819 820 for (mode = AUMODE_RECORD; mode != -1; 821 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 822 if ((setmode & mode) == 0) 823 continue; 824 825 p = mode == AUMODE_PLAY ? play : rec; 826 if (p == NULL) 827 continue; 828 829 if (p->sample_rate < 8000 || 830 p->sample_rate > 48000) 831 return (EINVAL); 832 833 index = auconv_set_converter(sc->sc_formats, AUICH_NFORMATS, 834 mode, p, TRUE); 835 if (index < 0) 836 return EINVAL; 837 if (sc->sc_formats[index].frequency_type != 1 838 && auich_set_rate(sc, mode, p->hw_sample_rate)) 839 return EINVAL; 840 if (mode == AUMODE_PLAY) { 841 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 842 control &= ~ICH_PCM246_MASK; 843 if (p->hw_channels == 4) { 844 control |= ICH_PCM4; 845 } else if (p->hw_channels == 6) { 846 control |= ICH_PCM6; 847 } 848 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 849 } 850 } 851 852 return (0); 853 } 854 855 static int 856 auich_round_blocksize(void *v, int blk) 857 { 858 859 return (blk & ~0x3f); /* keep good alignment */ 860 } 861 862 static int 863 auich_halt_output(void *v) 864 { 865 struct auich_softc *sc = v; 866 867 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 868 869 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 870 sc->pcmo.intr = NULL; 871 872 return (0); 873 } 874 875 static int 876 auich_halt_input(void *v) 877 { 878 struct auich_softc *sc = v; 879 880 DPRINTF(ICH_DEBUG_DMA, 881 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 882 883 /* XXX halt both unless known otherwise */ 884 885 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 886 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 887 sc->pcmi.intr = NULL; 888 889 return (0); 890 } 891 892 static int 893 auich_getdev(void *v, struct audio_device *adp) 894 { 895 struct auich_softc *sc = v; 896 897 *adp = sc->sc_audev; 898 return (0); 899 } 900 901 static int 902 auich_set_port(void *v, mixer_ctrl_t *cp) 903 { 904 struct auich_softc *sc = v; 905 906 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 907 } 908 909 static int 910 auich_get_port(void *v, mixer_ctrl_t *cp) 911 { 912 struct auich_softc *sc = v; 913 914 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 915 } 916 917 static int 918 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 919 { 920 struct auich_softc *sc = v; 921 922 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 923 } 924 925 static void * 926 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 927 int flags) 928 { 929 struct auich_softc *sc = v; 930 struct auich_dma *p; 931 int error; 932 933 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 934 return (NULL); 935 936 p = malloc(sizeof(*p), pool, flags|M_ZERO); 937 if (p == NULL) 938 return (NULL); 939 940 error = auich_allocmem(sc, size, 0, p); 941 if (error) { 942 free(p, pool); 943 return (NULL); 944 } 945 946 p->next = sc->sc_dmas; 947 sc->sc_dmas = p; 948 949 return (KERNADDR(p)); 950 } 951 952 static void 953 auich_freem(void *v, void *ptr, struct malloc_type *pool) 954 { 955 struct auich_softc *sc = v; 956 struct auich_dma *p, **pp; 957 958 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 959 if (KERNADDR(p) == ptr) { 960 auich_freemem(sc, p); 961 *pp = p->next; 962 free(p, pool); 963 return; 964 } 965 } 966 } 967 968 static size_t 969 auich_round_buffersize(void *v, int direction, size_t size) 970 { 971 972 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 973 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 974 975 return size; 976 } 977 978 static paddr_t 979 auich_mappage(void *v, void *mem, off_t off, int prot) 980 { 981 struct auich_softc *sc = v; 982 struct auich_dma *p; 983 984 if (off < 0) 985 return (-1); 986 987 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 988 ; 989 if (!p) 990 return (-1); 991 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 992 off, prot, BUS_DMA_WAITOK)); 993 } 994 995 static int 996 auich_get_props(void *v) 997 { 998 struct auich_softc *sc = v; 999 int props; 1000 1001 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1002 /* 1003 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1004 * rate because of aurateconv. Applications can't know what rate the 1005 * device can process in the case of mmap(). 1006 */ 1007 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 1008 props |= AUDIO_PROP_MMAP; 1009 return props; 1010 } 1011 1012 static int 1013 auich_intr(void *v) 1014 { 1015 struct auich_softc *sc = v; 1016 int ret = 0, gsts; 1017 1018 #ifdef DIAGNOSTIC 1019 int csts; 1020 #endif 1021 1022 #ifdef DIAGNOSTIC 1023 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1024 if (csts & PCI_STATUS_MASTER_ABORT) { 1025 printf("auich_intr: PCI master abort\n"); 1026 } 1027 #endif 1028 1029 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 1030 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1031 1032 if (gsts & ICH_POINT) { 1033 int sts; 1034 1035 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1036 ICH_PCMO + sc->sc_sts_reg); 1037 DPRINTF(ICH_DEBUG_INTR, 1038 ("auich_intr: osts=0x%x\n", sts)); 1039 1040 if (sts & ICH_FIFOE) 1041 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1042 1043 if (sts & ICH_BCIS) { 1044 struct auich_dmalist *q; 1045 int blksize, qptr, i; 1046 1047 blksize = sc->pcmo.blksize; 1048 qptr = sc->pcmo.qptr; 1049 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1050 ICH_PCMO + ICH_CIV); 1051 1052 while (qptr != i) { 1053 q = &sc->pcmo.dmalist[qptr]; 1054 1055 q->base = sc->pcmo.p; 1056 q->len = (blksize >> sc->sc_sample_shift) | 1057 ICH_DMAF_IOC; 1058 DPRINTF(ICH_DEBUG_INTR, 1059 ("auich_intr: %p, %p = %x @ 0x%x\n", 1060 &sc->pcmo.dmalist[i], q, q->len, q->base)); 1061 1062 sc->pcmo.p += blksize; 1063 if (sc->pcmo.p >= sc->pcmo.end) 1064 sc->pcmo.p = sc->pcmo.start; 1065 1066 qptr = (qptr + 1) & ICH_LVI_MASK; 1067 if (sc->pcmo.intr) 1068 sc->pcmo.intr(sc->pcmo.arg); 1069 } 1070 1071 sc->pcmo.qptr = qptr; 1072 bus_space_write_1(sc->iot, sc->aud_ioh, 1073 ICH_PCMO + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1074 } 1075 1076 /* int ack */ 1077 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1078 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1079 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1080 ret++; 1081 } 1082 1083 if (gsts & ICH_PIINT) { 1084 int sts; 1085 1086 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1087 ICH_PCMI + sc->sc_sts_reg); 1088 DPRINTF(ICH_DEBUG_INTR, 1089 ("auich_intr: ists=0x%x\n", sts)); 1090 1091 if (sts & ICH_FIFOE) 1092 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1093 1094 if (sts & ICH_BCIS) { 1095 struct auich_dmalist *q; 1096 int blksize, qptr, i; 1097 1098 blksize = sc->pcmi.blksize; 1099 qptr = sc->pcmi.qptr; 1100 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1101 ICH_PCMI + ICH_CIV); 1102 1103 while (qptr != i) { 1104 q = &sc->pcmi.dmalist[qptr]; 1105 1106 q->base = sc->pcmi.p; 1107 q->len = (blksize >> sc->sc_sample_shift) | 1108 ICH_DMAF_IOC; 1109 DPRINTF(ICH_DEBUG_INTR, 1110 ("auich_intr: %p, %p = %x @ 0x%x\n", 1111 &sc->pcmi.dmalist[i], q, q->len, q->base)); 1112 1113 sc->pcmi.p += blksize; 1114 if (sc->pcmi.p >= sc->pcmi.end) 1115 sc->pcmi.p = sc->pcmi.start; 1116 1117 qptr = (qptr + 1) & ICH_LVI_MASK; 1118 if (sc->pcmi.intr) 1119 sc->pcmi.intr(sc->pcmi.arg); 1120 } 1121 1122 sc->pcmi.qptr = qptr; 1123 bus_space_write_1(sc->iot, sc->aud_ioh, 1124 ICH_PCMI + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1125 } 1126 1127 /* int ack */ 1128 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1129 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1130 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1131 ret++; 1132 } 1133 1134 if (gsts & ICH_MIINT) { 1135 int sts; 1136 1137 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1138 ICH_MICI + sc->sc_sts_reg); 1139 DPRINTF(ICH_DEBUG_INTR, 1140 ("auich_intr: ists=0x%x\n", sts)); 1141 1142 if (sts & ICH_FIFOE) 1143 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1144 1145 /* TODO mic input DMA */ 1146 1147 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1148 } 1149 1150 return ret; 1151 } 1152 1153 static int 1154 auich_trigger_output(void *v, void *start, void *end, int blksize, 1155 void (*intr)(void *), void *arg, struct audio_params *param) 1156 { 1157 struct auich_softc *sc = v; 1158 struct auich_dmalist *q; 1159 struct auich_dma *p; 1160 size_t size; 1161 int qptr; 1162 #ifdef DIAGNOSTIC 1163 int csts; 1164 #endif 1165 1166 DPRINTF(ICH_DEBUG_DMA, 1167 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1168 start, end, blksize, intr, arg, param)); 1169 1170 sc->pcmo.intr = intr; 1171 sc->pcmo.arg = arg; 1172 #ifdef DIAGNOSTIC 1173 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1174 if (csts & PCI_STATUS_MASTER_ABORT) { 1175 printf("auich_trigger_output: PCI master abort\n"); 1176 } 1177 #endif 1178 1179 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1180 ; 1181 if (!p) { 1182 printf("auich_trigger_output: bad addr %p\n", start); 1183 return (EINVAL); 1184 } 1185 1186 size = (size_t)((caddr_t)end - (caddr_t)start); 1187 1188 /* 1189 * The logic behind this is: 1190 * setup one buffer to play, then LVI dump out the rest 1191 * to the scatter-gather chain. 1192 */ 1193 sc->pcmo.start = DMAADDR(p); 1194 sc->pcmo.p = sc->pcmo.start; 1195 sc->pcmo.end = sc->pcmo.start + size; 1196 sc->pcmo.blksize = blksize; 1197 1198 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1199 q = &sc->pcmo.dmalist[qptr]; 1200 1201 q->base = sc->pcmo.p; 1202 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1203 1204 sc->pcmo.p += blksize; 1205 if (sc->pcmo.p >= sc->pcmo.end) 1206 sc->pcmo.p = sc->pcmo.start; 1207 } 1208 1209 sc->pcmo.qptr = qptr = 0; 1210 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1211 (qptr - 1) & ICH_LVI_MASK); 1212 1213 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1214 sc->sc_cddma + ICH_PCMO_OFF(0)); 1215 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1216 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1217 1218 return (0); 1219 } 1220 1221 static int 1222 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1223 void *v; 1224 void *start, *end; 1225 int blksize; 1226 void (*intr)(void *); 1227 void *arg; 1228 struct audio_params *param; 1229 { 1230 struct auich_softc *sc = v; 1231 struct auich_dmalist *q; 1232 struct auich_dma *p; 1233 size_t size; 1234 int qptr; 1235 #ifdef DIAGNOSTIC 1236 int csts; 1237 #endif 1238 1239 DPRINTF(ICH_DEBUG_DMA, 1240 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1241 start, end, blksize, intr, arg, param)); 1242 1243 sc->pcmi.intr = intr; 1244 sc->pcmi.arg = arg; 1245 1246 #ifdef DIAGNOSTIC 1247 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1248 if (csts & PCI_STATUS_MASTER_ABORT) { 1249 printf("auich_trigger_input: PCI master abort\n"); 1250 } 1251 #endif 1252 1253 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1254 ; 1255 if (!p) { 1256 printf("auich_trigger_input: bad addr %p\n", start); 1257 return (EINVAL); 1258 } 1259 1260 size = (size_t)((caddr_t)end - (caddr_t)start); 1261 1262 /* 1263 * The logic behind this is: 1264 * setup one buffer to play, then LVI dump out the rest 1265 * to the scatter-gather chain. 1266 */ 1267 sc->pcmi.start = DMAADDR(p); 1268 sc->pcmi.p = sc->pcmi.start; 1269 sc->pcmi.end = sc->pcmi.start + size; 1270 sc->pcmi.blksize = blksize; 1271 1272 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1273 q = &sc->pcmi.dmalist[qptr]; 1274 1275 q->base = sc->pcmi.p; 1276 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1277 1278 sc->pcmi.p += blksize; 1279 if (sc->pcmi.p >= sc->pcmi.end) 1280 sc->pcmi.p = sc->pcmi.start; 1281 } 1282 1283 sc->pcmi.qptr = qptr = 0; 1284 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1285 (qptr - 1) & ICH_LVI_MASK); 1286 1287 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1288 sc->sc_cddma + ICH_PCMI_OFF(0)); 1289 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1290 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1291 1292 return (0); 1293 } 1294 1295 static int 1296 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1297 struct auich_dma *p) 1298 { 1299 int error; 1300 1301 p->size = size; 1302 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1303 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1304 &p->nsegs, BUS_DMA_NOWAIT); 1305 if (error) 1306 return (error); 1307 1308 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1309 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1310 if (error) 1311 goto free; 1312 1313 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1314 0, BUS_DMA_NOWAIT, &p->map); 1315 if (error) 1316 goto unmap; 1317 1318 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1319 BUS_DMA_NOWAIT); 1320 if (error) 1321 goto destroy; 1322 return (0); 1323 1324 destroy: 1325 bus_dmamap_destroy(sc->dmat, p->map); 1326 unmap: 1327 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1328 free: 1329 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1330 return (error); 1331 } 1332 1333 static int 1334 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1335 { 1336 1337 bus_dmamap_unload(sc->dmat, p->map); 1338 bus_dmamap_destroy(sc->dmat, p->map); 1339 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1340 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1341 return (0); 1342 } 1343 1344 static int 1345 auich_alloc_cdata(struct auich_softc *sc) 1346 { 1347 bus_dma_segment_t seg; 1348 int error, rseg; 1349 1350 /* 1351 * Allocate the control data structure, and create and load the 1352 * DMA map for it. 1353 */ 1354 if ((error = bus_dmamem_alloc(sc->dmat, 1355 sizeof(struct auich_cdata), 1356 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1357 printf("%s: unable to allocate control data, error = %d\n", 1358 sc->sc_dev.dv_xname, error); 1359 goto fail_0; 1360 } 1361 1362 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1363 sizeof(struct auich_cdata), 1364 (caddr_t *) &sc->sc_cdata, 1365 sc->sc_dmamap_flags)) != 0) { 1366 printf("%s: unable to map control data, error = %d\n", 1367 sc->sc_dev.dv_xname, error); 1368 goto fail_1; 1369 } 1370 1371 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1372 sizeof(struct auich_cdata), 0, 0, 1373 &sc->sc_cddmamap)) != 0) { 1374 printf("%s: unable to create control data DMA map, " 1375 "error = %d\n", sc->sc_dev.dv_xname, error); 1376 goto fail_2; 1377 } 1378 1379 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1380 sc->sc_cdata, sizeof(struct auich_cdata), 1381 NULL, 0)) != 0) { 1382 printf("%s: unable tp load control data DMA map, " 1383 "error = %d\n", sc->sc_dev.dv_xname, error); 1384 goto fail_3; 1385 } 1386 1387 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1388 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1389 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1390 1391 return (0); 1392 1393 fail_3: 1394 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1395 fail_2: 1396 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1397 sizeof(struct auich_cdata)); 1398 fail_1: 1399 bus_dmamem_free(sc->dmat, &seg, rseg); 1400 fail_0: 1401 return (error); 1402 } 1403 1404 static void 1405 auich_powerhook(int why, void *addr) 1406 { 1407 struct auich_softc *sc = (struct auich_softc *)addr; 1408 1409 switch (why) { 1410 case PWR_SUSPEND: 1411 case PWR_STANDBY: 1412 /* Power down */ 1413 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1414 sc->sc_suspend = why; 1415 break; 1416 1417 case PWR_RESUME: 1418 /* Wake up */ 1419 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1420 if (sc->sc_suspend == PWR_RESUME) { 1421 printf("%s: resume without suspend.\n", 1422 sc->sc_dev.dv_xname); 1423 sc->sc_suspend = why; 1424 return; 1425 } 1426 sc->sc_suspend = why; 1427 auich_reset_codec(sc); 1428 DELAY(1000); 1429 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1430 break; 1431 1432 case PWR_SOFTSUSPEND: 1433 case PWR_SOFTSTANDBY: 1434 case PWR_SOFTRESUME: 1435 break; 1436 } 1437 } 1438 1439 /* 1440 * Calibrate card (some boards are overclocked and need scaling) 1441 */ 1442 static void 1443 auich_calibrate(struct auich_softc *sc) 1444 { 1445 struct timeval t1, t2; 1446 uint8_t ociv, nciv; 1447 uint64_t wait_us; 1448 uint32_t actual_48k_rate, bytes, ac97rate; 1449 void *temp_buffer; 1450 struct auich_dma *p; 1451 u_long rate; 1452 1453 /* 1454 * Grab audio from input for fixed interval and compare how 1455 * much we actually get with what we expect. Interval needs 1456 * to be sufficiently short that no interrupts are 1457 * generated. 1458 */ 1459 1460 /* Force the codec to a known state first. */ 1461 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1462 rate = sc->sc_ac97_clock = 48000; 1463 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1464 &rate); 1465 1466 /* Setup a buffer */ 1467 bytes = 64000; 1468 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1469 1470 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1471 ; 1472 if (p == NULL) { 1473 printf("auich_calibrate: bad address %p\n", temp_buffer); 1474 return; 1475 } 1476 sc->pcmi.dmalist[0].base = DMAADDR(p); 1477 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1478 1479 /* 1480 * our data format is stereo, 16 bit so each sample is 4 bytes. 1481 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1482 * we're going to start recording with interrupts disabled and measure 1483 * the time taken for one block to complete. we know the block size, 1484 * we know the time in microseconds, we calculate the sample rate: 1485 * 1486 * actual_rate [bps] = bytes / (time [s] * 4) 1487 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1488 * actual_rate [Hz] = (bytes * 250000) / time [us] 1489 */ 1490 1491 /* prepare */ 1492 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1493 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1494 sc->sc_cddma + ICH_PCMI_OFF(0)); 1495 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1496 (0 - 1) & ICH_LVI_MASK); 1497 1498 /* start */ 1499 microtime(&t1); 1500 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1501 1502 /* wait */ 1503 nciv = ociv; 1504 do { 1505 microtime(&t2); 1506 if (t2.tv_sec - t1.tv_sec > 1) 1507 break; 1508 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1509 ICH_PCMI + ICH_CIV); 1510 } while (nciv == ociv); 1511 microtime(&t2); 1512 1513 /* stop */ 1514 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1515 1516 /* reset */ 1517 DELAY(100); 1518 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1519 1520 /* turn time delta into us */ 1521 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1522 1523 auich_freem(sc, temp_buffer, M_DEVBUF); 1524 1525 if (nciv == ociv) { 1526 printf("%s: ac97 link rate calibration timed out after %" 1527 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1528 return; 1529 } 1530 1531 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1532 1533 if (actual_48k_rate < 50000) 1534 ac97rate = 48000; 1535 else 1536 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1537 1538 printf("%s: measured ac97 link rate at %d Hz", 1539 sc->sc_dev.dv_xname, actual_48k_rate); 1540 if (ac97rate != actual_48k_rate) 1541 printf(", will use %d Hz", ac97rate); 1542 printf("\n"); 1543 1544 sc->sc_ac97_clock = ac97rate; 1545 } 1546
Indexes created Wed Oct 22 13:09:56 GMT 2025