auich.c revision 1.84
1 /* $NetBSD: auich.c,v 1.84 2005/01/10 22:01:37 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.84 2005/01/10 22:01:37 kent Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 187 struct ac97_codec_if *codec_if; 188 struct ac97_host_if host_if; 189 190 /* DMA scatter-gather lists. */ 191 bus_dmamap_t sc_cddmamap; 192 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 193 194 struct auich_cdata *sc_cdata; 195 196 struct auich_ring { 197 int qptr; 198 struct auich_dmalist *dmalist; 199 200 u_int32_t start, p, end; 201 int blksize; 202 203 void (*intr)(void *); 204 void *arg; 205 } pcmo, pcmi, mici; 206 207 struct auich_dma *sc_dmas; 208 209 /* SiS 7012 hack */ 210 int sc_sample_shift; 211 int sc_sts_reg; 212 /* 440MX workaround */ 213 int sc_dmamap_flags; 214 215 /* Power Management */ 216 void *sc_powerhook; 217 int sc_suspend; 218 219 /* sysctl */ 220 struct sysctllog *sc_log; 221 uint32_t sc_ac97_clock; 222 int sc_ac97_clock_mib; 223 224 #define AUICH_NFORMATS 3 225 struct audio_format sc_formats[AUICH_NFORMATS]; 226 struct audio_encoding_set *sc_encodings; 227 }; 228 229 /* Debug */ 230 #ifdef AUICH_DEBUG 231 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 232 int auich_debug = 0xfffe; 233 #define ICH_DEBUG_CODECIO 0x0001 234 #define ICH_DEBUG_DMA 0x0002 235 #define ICH_DEBUG_INTR 0x0004 236 #else 237 #define DPRINTF(x,y) /* nothing */ 238 #endif 239 240 static int auich_match(struct device *, struct cfdata *, void *); 241 static void auich_attach(struct device *, struct device *, void *); 242 static int auich_detach(struct device *, int); 243 static int auich_activate(struct device *, enum devact); 244 static int auich_intr(void *); 245 246 CFATTACH_DECL(auich, sizeof(struct auich_softc), 247 auich_match, auich_attach, auich_detach, auich_activate); 248 249 static int auich_query_encoding(void *, struct audio_encoding *); 250 static int auich_set_params(void *, int, int, audio_params_t *, 251 audio_params_t *, stream_filter_list_t *, 252 stream_filter_list_t *); 253 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 254 static int auich_halt_output(void *); 255 static int auich_halt_input(void *); 256 static int auich_getdev(void *, struct audio_device *); 257 static int auich_set_port(void *, mixer_ctrl_t *); 258 static int auich_get_port(void *, mixer_ctrl_t *); 259 static int auich_query_devinfo(void *, mixer_devinfo_t *); 260 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 261 static void auich_freem(void *, void *, struct malloc_type *); 262 static size_t auich_round_buffersize(void *, int, size_t); 263 static paddr_t auich_mappage(void *, void *, off_t, int); 264 static int auich_get_props(void *); 265 static int auich_trigger_output(void *, void *, void *, int, 266 void (*)(void *), void *, const audio_params_t *); 267 static int auich_trigger_input(void *, void *, void *, int, 268 void (*)(void *), void *, const audio_params_t *); 269 270 static int auich_alloc_cdata(struct auich_softc *); 271 272 static int auich_allocmem(struct auich_softc *, size_t, size_t, 273 struct auich_dma *); 274 static int auich_freemem(struct auich_softc *, struct auich_dma *); 275 276 static void auich_powerhook(int, void *); 277 static int auich_set_rate(struct auich_softc *, int, u_long); 278 static int auich_sysctl_verify(SYSCTLFN_ARGS); 279 static void auich_finish_attach(struct device *); 280 static void auich_calibrate(struct auich_softc *); 281 282 static int auich_attach_codec(void *, struct ac97_codec_if *); 283 static int auich_read_codec(void *, u_int8_t, u_int16_t *); 284 static int auich_write_codec(void *, u_int8_t, u_int16_t); 285 static int auich_reset_codec(void *); 286 287 const struct audio_hw_if auich_hw_if = { 288 NULL, /* open */ 289 NULL, /* close */ 290 NULL, /* drain */ 291 auich_query_encoding, 292 auich_set_params, 293 auich_round_blocksize, 294 NULL, /* commit_setting */ 295 NULL, /* init_output */ 296 NULL, /* init_input */ 297 NULL, /* start_output */ 298 NULL, /* start_input */ 299 auich_halt_output, 300 auich_halt_input, 301 NULL, /* speaker_ctl */ 302 auich_getdev, 303 NULL, /* getfd */ 304 auich_set_port, 305 auich_get_port, 306 auich_query_devinfo, 307 auich_allocm, 308 auich_freem, 309 auich_round_buffersize, 310 auich_mappage, 311 auich_get_props, 312 auich_trigger_output, 313 auich_trigger_input, 314 NULL, /* dev_ioctl */ 315 }; 316 317 #define AUICH_FORMATS_4CH 1 318 #define AUICH_FORMATS_6CH 2 319 static const struct audio_format auich_formats[AUICH_NFORMATS] = { 320 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 321 2, AUFMT_STEREO, 0, {8000, 48000}}, 322 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 323 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 324 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 325 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 326 }; 327 328 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 329 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 330 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 331 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 332 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 333 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 334 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 335 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 336 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 337 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 338 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 339 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 340 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 341 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 342 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 343 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 344 345 static const struct auich_devtype { 346 pcireg_t id; 347 const char *name; 348 const char *shortname; /* must be less than 11 characters */ 349 } auich_devices[] = { 350 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 351 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 352 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 353 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 354 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 355 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 356 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 357 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 358 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 359 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 360 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 361 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 362 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 363 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 364 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 365 { 0, NULL, NULL }, 366 }; 367 368 static const struct auich_devtype * 369 auich_lookup(struct pci_attach_args *pa) 370 { 371 const struct auich_devtype *d; 372 373 for (d = auich_devices; d->name != NULL; d++) { 374 if (pa->pa_id == d->id) 375 return (d); 376 } 377 378 return (NULL); 379 } 380 381 static int 382 auich_match(struct device *parent, struct cfdata *match, void *aux) 383 { 384 struct pci_attach_args *pa = aux; 385 386 if (auich_lookup(pa) != NULL) 387 return (1); 388 389 return (0); 390 } 391 392 static void 393 auich_attach(struct device *parent, struct device *self, void *aux) 394 { 395 struct auich_softc *sc = (struct auich_softc *)self; 396 struct pci_attach_args *pa = aux; 397 pci_intr_handle_t ih; 398 pcireg_t v; 399 const char *intrstr; 400 const struct auich_devtype *d; 401 struct sysctlnode *node; 402 int err, node_mib, i; 403 404 aprint_naive(": Audio controller\n"); 405 406 d = auich_lookup(pa); 407 if (d == NULL) 408 panic("auich_attach: impossible"); 409 410 sc->sc_pc = pa->pa_pc; 411 sc->sc_pt = pa->pa_tag; 412 413 aprint_normal(": %s\n", d->name); 414 415 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6) { 416 /* 417 * Use native mode for ICH4/ICH5/ICH6 418 */ 419 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 420 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 421 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 422 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 423 v | ICH_CFG_IOSE); 424 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 425 0, &sc->iot, &sc->mix_ioh, NULL, 426 &sc->mix_size)) { 427 aprint_error("%s: can't map codec i/o space\n", 428 sc->sc_dev.dv_xname); 429 return; 430 } 431 } 432 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 433 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 434 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 435 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 436 v | ICH_CFG_IOSE); 437 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 438 0, &sc->iot, &sc->aud_ioh, NULL, 439 &sc->aud_size)) { 440 aprint_error("%s: can't map device i/o space\n", 441 sc->sc_dev.dv_xname); 442 return; 443 } 444 } 445 } else { 446 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 447 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 448 aprint_error("%s: can't map codec i/o space\n", 449 sc->sc_dev.dv_xname); 450 return; 451 } 452 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 453 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 454 aprint_error("%s: can't map device i/o space\n", 455 sc->sc_dev.dv_xname); 456 return; 457 } 458 } 459 sc->dmat = pa->pa_dmat; 460 461 /* enable bus mastering */ 462 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 463 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 464 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 465 466 /* Map and establish the interrupt. */ 467 if (pci_intr_map(pa, &ih)) { 468 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 469 return; 470 } 471 intrstr = pci_intr_string(pa->pa_pc, ih); 472 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 473 auich_intr, sc); 474 if (sc->sc_ih == NULL) { 475 aprint_error("%s: can't establish interrupt", 476 sc->sc_dev.dv_xname); 477 if (intrstr != NULL) 478 aprint_normal(" at %s", intrstr); 479 aprint_normal("\n"); 480 return; 481 } 482 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 483 484 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 485 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 486 "0x%02x", PCI_REVISION(pa->pa_class)); 487 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 488 489 /* SiS 7012 needs special handling */ 490 if (d->id == PCIID_SIS7012) { 491 sc->sc_sts_reg = ICH_PICB; 492 sc->sc_sample_shift = 0; 493 /* Un-mute output. From Linux. */ 494 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 495 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 496 ICH_SIS_CTL_UNMUTE); 497 } else { 498 sc->sc_sts_reg = ICH_STS; 499 sc->sc_sample_shift = 1; 500 } 501 502 /* Workaround for a 440MX B-stepping erratum */ 503 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 504 if (d->id == PCIID_440MX) { 505 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 506 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 507 } 508 509 /* Set up DMA lists. */ 510 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 511 auich_alloc_cdata(sc); 512 513 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 514 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 515 516 sc->host_if.arg = sc; 517 sc->host_if.attach = auich_attach_codec; 518 sc->host_if.read = auich_read_codec; 519 sc->host_if.write = auich_write_codec; 520 sc->host_if.reset = auich_reset_codec; 521 522 if (ac97_attach(&sc->host_if, self) != 0) 523 return; 524 525 /* setup audio_format */ 526 memcpy(sc->sc_formats, auich_formats, sizeof(auich_formats)); 527 if (!AC97_IS_4CH(sc->codec_if)) 528 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_4CH]); 529 if (!AC97_IS_6CH(sc->codec_if)) 530 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_6CH]); 531 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 532 for (i = 0; i < AUICH_NFORMATS; i++) { 533 sc->sc_formats[i].frequency_type = 1; 534 sc->sc_formats[i].frequency[0] = 48000; 535 } 536 } 537 538 if (0 != auconv_create_encodings(sc->sc_formats, AUICH_NFORMATS, 539 &sc->sc_encodings)) { 540 return; 541 } 542 543 /* Watch for power change */ 544 sc->sc_suspend = PWR_RESUME; 545 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 546 547 config_interrupts(self, auich_finish_attach); 548 549 /* sysctl setup */ 550 if (AC97_IS_FIXED_RATE(sc->codec_if)) 551 return; 552 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 553 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 554 CTL_HW, CTL_EOL); 555 if (err != 0) 556 goto sysctl_err; 557 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 558 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 559 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 560 if (err != 0) 561 goto sysctl_err; 562 node_mib = node->sysctl_num; 563 /* passing the sc address instead of &sc->sc_ac97_clock */ 564 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 565 CTLTYPE_INT, "ac97rate", 566 SYSCTL_DESCR("AC'97 codec link rate"), 567 auich_sysctl_verify, 0, sc, 0, 568 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 569 if (err != 0) 570 goto sysctl_err; 571 sc->sc_ac97_clock_mib = node->sysctl_num; 572 573 return; 574 575 sysctl_err: 576 printf("%s: failed to add sysctl nodes. (%d)\n", 577 sc->sc_dev.dv_xname, err); 578 return; /* failure of sysctl is not fatal. */ 579 } 580 581 static int 582 auich_activate(struct device *self, enum devact act) 583 { 584 struct auich_softc *sc; 585 int ret; 586 587 sc = (struct auich_softc *)self; 588 ret = 0; 589 switch (act) { 590 case DVACT_ACTIVATE: 591 return EOPNOTSUPP; 592 case DVACT_DEACTIVATE: 593 if (sc->sc_audiodev != NULL) 594 ret = config_deactivate(sc->sc_audiodev); 595 return ret; 596 } 597 return EOPNOTSUPP; 598 } 599 600 static int 601 auich_detach(struct device *self, int flags) 602 { 603 struct auich_softc *sc; 604 605 sc = (struct auich_softc *)self; 606 607 /* audio */ 608 if (sc->sc_audiodev != NULL) 609 config_detach(sc->sc_audiodev, flags); 610 611 /* sysctl */ 612 sysctl_teardown(&sc->sc_log); 613 614 /* audio_encoding_set */ 615 auconv_delete_encodings(sc->sc_encodings); 616 617 /* ac97 */ 618 if (sc->codec_if != NULL) 619 sc->codec_if->vtbl->detach(sc->codec_if); 620 621 /* PCI */ 622 if (sc->sc_ih != NULL) 623 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 624 if (sc->mix_size != 0) 625 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 626 if (sc->aud_size != 0) 627 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 628 return 0; 629 } 630 631 static int 632 auich_sysctl_verify(SYSCTLFN_ARGS) 633 { 634 int error, tmp; 635 struct sysctlnode node; 636 struct auich_softc *sc; 637 638 node = *rnode; 639 sc = rnode->sysctl_data; 640 tmp = sc->sc_ac97_clock; 641 node.sysctl_data = &tmp; 642 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 643 if (error || newp == NULL) 644 return error; 645 646 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 647 if (tmp < 48000 || tmp > 96000) 648 return EINVAL; 649 sc->sc_ac97_clock = tmp; 650 } 651 652 return 0; 653 } 654 655 static void 656 auich_finish_attach(struct device *self) 657 { 658 struct auich_softc *sc = (void *)self; 659 660 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 661 auich_calibrate(sc); 662 663 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 664 } 665 666 #define ICH_CODECIO_INTERVAL 10 667 static int 668 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 669 { 670 struct auich_softc *sc = v; 671 int i; 672 uint32_t status; 673 674 /* wait for an access semaphore */ 675 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 676 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 677 DELAY(ICH_CODECIO_INTERVAL)); 678 679 if (i > 0) { 680 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 681 DPRINTF(ICH_DEBUG_CODECIO, 682 ("auich_read_codec(%x, %x)\n", reg, *val)); 683 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 684 if (status & ICH_RCS) { 685 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 686 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 687 *val = 0xffff; 688 DPRINTF(ICH_DEBUG_CODECIO, 689 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 690 return -1; 691 } 692 return 0; 693 } else { 694 DPRINTF(ICH_DEBUG_CODECIO, 695 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 696 return -1; 697 } 698 } 699 700 static int 701 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 702 { 703 struct auich_softc *sc = v; 704 int i; 705 706 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 707 /* wait for an access semaphore */ 708 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 709 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 710 DELAY(ICH_CODECIO_INTERVAL)); 711 712 if (i > 0) { 713 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 714 return 0; 715 } else { 716 DPRINTF(ICH_DEBUG_CODECIO, 717 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 718 return -1; 719 } 720 } 721 722 static int 723 auich_attach_codec(void *v, struct ac97_codec_if *cif) 724 { 725 struct auich_softc *sc = v; 726 727 sc->codec_if = cif; 728 return 0; 729 } 730 731 static int 732 auich_reset_codec(void *v) 733 { 734 struct auich_softc *sc = v; 735 int i; 736 uint32_t control, status; 737 738 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 739 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 740 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 741 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 742 743 for (i = 500000; i >= 0; i--) { 744 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 745 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 746 break; 747 DELAY(1); 748 } 749 if (i <= 0) { 750 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 751 return ETIMEDOUT; 752 } 753 #ifdef DEBUG 754 if (status & ICH_SCR) 755 printf("%s: The 2nd codec is ready.\n", 756 sc->sc_dev.dv_xname); 757 if (status & ICH_S2CR) 758 printf("%s: The 3rd codec is ready.\n", 759 sc->sc_dev.dv_xname); 760 #endif 761 return 0; 762 } 763 764 static int 765 auich_query_encoding(void *v, struct audio_encoding *aep) 766 { 767 struct auich_softc *sc; 768 769 sc = (struct auich_softc *)v; 770 return auconv_query_encoding(sc->sc_encodings, aep); 771 } 772 773 static int 774 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 775 { 776 int ret; 777 u_int ratetmp; 778 779 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 780 ratetmp = srate; 781 if (mode == AUMODE_RECORD) 782 return sc->codec_if->vtbl->set_rate(sc->codec_if, 783 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 784 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 785 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 786 if (ret) 787 return ret; 788 ratetmp = srate; 789 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 790 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 791 if (ret) 792 return ret; 793 ratetmp = srate; 794 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 795 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 796 return ret; 797 } 798 799 static int 800 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 801 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 802 { 803 struct auich_softc *sc = v; 804 audio_params_t *p; 805 stream_filter_list_t *fil; 806 int mode, index; 807 uint32_t control; 808 809 for (mode = AUMODE_RECORD; mode != -1; 810 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 811 if ((setmode & mode) == 0) 812 continue; 813 814 p = mode == AUMODE_PLAY ? play : rec; 815 fil = mode == AUMODE_PLAY ? pfil : rfil; 816 if (p == NULL) 817 continue; 818 819 if (p->sample_rate < 8000 || 820 p->sample_rate > 48000) 821 return (EINVAL); 822 823 index = auconv_set_converter(sc->sc_formats, AUICH_NFORMATS, 824 mode, p, TRUE, fil); 825 if (index < 0) 826 return EINVAL; 827 if (fil->req_size > 0) 828 p = &fil->filters[0].param; 829 /* p represents HW encoding */ 830 if (sc->sc_formats[index].frequency_type != 1 831 && auich_set_rate(sc, mode, p->sample_rate)) 832 return EINVAL; 833 if (mode == AUMODE_PLAY) { 834 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 835 control &= ~ICH_PCM246_MASK; 836 if (p->channels == 4) { 837 control |= ICH_PCM4; 838 } else if (p->channels == 6) { 839 control |= ICH_PCM6; 840 } 841 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 842 } 843 } 844 845 return (0); 846 } 847 848 static int 849 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 850 { 851 852 return (blk & ~0x3f); /* keep good alignment */ 853 } 854 855 static int 856 auich_halt_output(void *v) 857 { 858 struct auich_softc *sc = v; 859 860 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 861 862 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 863 sc->pcmo.intr = NULL; 864 865 return (0); 866 } 867 868 static int 869 auich_halt_input(void *v) 870 { 871 struct auich_softc *sc = v; 872 873 DPRINTF(ICH_DEBUG_DMA, 874 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 875 876 /* XXX halt both unless known otherwise */ 877 878 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 879 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 880 sc->pcmi.intr = NULL; 881 882 return (0); 883 } 884 885 static int 886 auich_getdev(void *v, struct audio_device *adp) 887 { 888 struct auich_softc *sc = v; 889 890 *adp = sc->sc_audev; 891 return (0); 892 } 893 894 static int 895 auich_set_port(void *v, mixer_ctrl_t *cp) 896 { 897 struct auich_softc *sc = v; 898 899 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 900 } 901 902 static int 903 auich_get_port(void *v, mixer_ctrl_t *cp) 904 { 905 struct auich_softc *sc = v; 906 907 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 908 } 909 910 static int 911 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 912 { 913 struct auich_softc *sc = v; 914 915 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 916 } 917 918 static void * 919 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 920 int flags) 921 { 922 struct auich_softc *sc = v; 923 struct auich_dma *p; 924 int error; 925 926 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 927 return (NULL); 928 929 p = malloc(sizeof(*p), pool, flags|M_ZERO); 930 if (p == NULL) 931 return (NULL); 932 933 error = auich_allocmem(sc, size, 0, p); 934 if (error) { 935 free(p, pool); 936 return (NULL); 937 } 938 939 p->next = sc->sc_dmas; 940 sc->sc_dmas = p; 941 942 return (KERNADDR(p)); 943 } 944 945 static void 946 auich_freem(void *v, void *ptr, struct malloc_type *pool) 947 { 948 struct auich_softc *sc = v; 949 struct auich_dma *p, **pp; 950 951 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 952 if (KERNADDR(p) == ptr) { 953 auich_freemem(sc, p); 954 *pp = p->next; 955 free(p, pool); 956 return; 957 } 958 } 959 } 960 961 static size_t 962 auich_round_buffersize(void *v, int direction, size_t size) 963 { 964 965 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 966 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 967 968 return size; 969 } 970 971 static paddr_t 972 auich_mappage(void *v, void *mem, off_t off, int prot) 973 { 974 struct auich_softc *sc = v; 975 struct auich_dma *p; 976 977 if (off < 0) 978 return (-1); 979 980 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 981 ; 982 if (!p) 983 return (-1); 984 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 985 off, prot, BUS_DMA_WAITOK)); 986 } 987 988 static int 989 auich_get_props(void *v) 990 { 991 struct auich_softc *sc = v; 992 int props; 993 994 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 995 /* 996 * Even if the codec is fixed-rate, set_param() succeeds for any sample 997 * rate because of aurateconv. Applications can't know what rate the 998 * device can process in the case of mmap(). 999 */ 1000 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 1001 props |= AUDIO_PROP_MMAP; 1002 return props; 1003 } 1004 1005 static int 1006 auich_intr(void *v) 1007 { 1008 struct auich_softc *sc = v; 1009 int ret = 0, gsts; 1010 1011 #ifdef DIAGNOSTIC 1012 int csts; 1013 #endif 1014 1015 #ifdef DIAGNOSTIC 1016 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1017 if (csts & PCI_STATUS_MASTER_ABORT) { 1018 printf("auich_intr: PCI master abort\n"); 1019 } 1020 #endif 1021 1022 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 1023 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1024 1025 if (gsts & ICH_POINT) { 1026 int sts; 1027 1028 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1029 ICH_PCMO + sc->sc_sts_reg); 1030 DPRINTF(ICH_DEBUG_INTR, 1031 ("auich_intr: osts=0x%x\n", sts)); 1032 1033 if (sts & ICH_FIFOE) 1034 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1035 1036 if (sts & ICH_BCIS) { 1037 struct auich_dmalist *q; 1038 int blksize, qptr, i; 1039 1040 blksize = sc->pcmo.blksize; 1041 qptr = sc->pcmo.qptr; 1042 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1043 ICH_PCMO + ICH_CIV); 1044 1045 while (qptr != i) { 1046 q = &sc->pcmo.dmalist[qptr]; 1047 1048 q->base = sc->pcmo.p; 1049 q->len = (blksize >> sc->sc_sample_shift) | 1050 ICH_DMAF_IOC; 1051 DPRINTF(ICH_DEBUG_INTR, 1052 ("auich_intr: %p, %p = %x @ 0x%x\n", 1053 &sc->pcmo.dmalist[i], q, q->len, q->base)); 1054 1055 sc->pcmo.p += blksize; 1056 if (sc->pcmo.p >= sc->pcmo.end) 1057 sc->pcmo.p = sc->pcmo.start; 1058 1059 qptr = (qptr + 1) & ICH_LVI_MASK; 1060 if (sc->pcmo.intr) 1061 sc->pcmo.intr(sc->pcmo.arg); 1062 } 1063 1064 sc->pcmo.qptr = qptr; 1065 bus_space_write_1(sc->iot, sc->aud_ioh, 1066 ICH_PCMO + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1067 } 1068 1069 /* int ack */ 1070 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1071 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1072 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1073 ret++; 1074 } 1075 1076 if (gsts & ICH_PIINT) { 1077 int sts; 1078 1079 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1080 ICH_PCMI + sc->sc_sts_reg); 1081 DPRINTF(ICH_DEBUG_INTR, 1082 ("auich_intr: ists=0x%x\n", sts)); 1083 1084 if (sts & ICH_FIFOE) 1085 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1086 1087 if (sts & ICH_BCIS) { 1088 struct auich_dmalist *q; 1089 int blksize, qptr, i; 1090 1091 blksize = sc->pcmi.blksize; 1092 qptr = sc->pcmi.qptr; 1093 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1094 ICH_PCMI + ICH_CIV); 1095 1096 while (qptr != i) { 1097 q = &sc->pcmi.dmalist[qptr]; 1098 1099 q->base = sc->pcmi.p; 1100 q->len = (blksize >> sc->sc_sample_shift) | 1101 ICH_DMAF_IOC; 1102 DPRINTF(ICH_DEBUG_INTR, 1103 ("auich_intr: %p, %p = %x @ 0x%x\n", 1104 &sc->pcmi.dmalist[i], q, q->len, q->base)); 1105 1106 sc->pcmi.p += blksize; 1107 if (sc->pcmi.p >= sc->pcmi.end) 1108 sc->pcmi.p = sc->pcmi.start; 1109 1110 qptr = (qptr + 1) & ICH_LVI_MASK; 1111 if (sc->pcmi.intr) 1112 sc->pcmi.intr(sc->pcmi.arg); 1113 } 1114 1115 sc->pcmi.qptr = qptr; 1116 bus_space_write_1(sc->iot, sc->aud_ioh, 1117 ICH_PCMI + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1118 } 1119 1120 /* int ack */ 1121 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1122 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1123 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1124 ret++; 1125 } 1126 1127 if (gsts & ICH_MIINT) { 1128 int sts; 1129 1130 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1131 ICH_MICI + sc->sc_sts_reg); 1132 DPRINTF(ICH_DEBUG_INTR, 1133 ("auich_intr: ists=0x%x\n", sts)); 1134 1135 if (sts & ICH_FIFOE) 1136 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1137 1138 /* TODO mic input DMA */ 1139 1140 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1141 } 1142 1143 return ret; 1144 } 1145 1146 static int 1147 auich_trigger_output(void *v, void *start, void *end, int blksize, 1148 void (*intr)(void *), void *arg, const audio_params_t *param) 1149 { 1150 struct auich_softc *sc = v; 1151 struct auich_dmalist *q; 1152 struct auich_dma *p; 1153 size_t size; 1154 int qptr; 1155 #ifdef DIAGNOSTIC 1156 int csts; 1157 #endif 1158 1159 DPRINTF(ICH_DEBUG_DMA, 1160 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1161 start, end, blksize, intr, arg, param)); 1162 1163 sc->pcmo.intr = intr; 1164 sc->pcmo.arg = arg; 1165 #ifdef DIAGNOSTIC 1166 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1167 if (csts & PCI_STATUS_MASTER_ABORT) { 1168 printf("auich_trigger_output: PCI master abort\n"); 1169 } 1170 #endif 1171 1172 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1173 ; 1174 if (!p) { 1175 printf("auich_trigger_output: bad addr %p\n", start); 1176 return (EINVAL); 1177 } 1178 1179 size = (size_t)((caddr_t)end - (caddr_t)start); 1180 1181 /* 1182 * The logic behind this is: 1183 * setup one buffer to play, then LVI dump out the rest 1184 * to the scatter-gather chain. 1185 */ 1186 sc->pcmo.start = DMAADDR(p); 1187 sc->pcmo.p = sc->pcmo.start; 1188 sc->pcmo.end = sc->pcmo.start + size; 1189 sc->pcmo.blksize = blksize; 1190 1191 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1192 q = &sc->pcmo.dmalist[qptr]; 1193 1194 q->base = sc->pcmo.p; 1195 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1196 1197 sc->pcmo.p += blksize; 1198 if (sc->pcmo.p >= sc->pcmo.end) 1199 sc->pcmo.p = sc->pcmo.start; 1200 } 1201 1202 sc->pcmo.qptr = qptr = 0; 1203 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1204 (qptr - 1) & ICH_LVI_MASK); 1205 1206 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1207 sc->sc_cddma + ICH_PCMO_OFF(0)); 1208 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1209 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1210 1211 return (0); 1212 } 1213 1214 static int 1215 auich_trigger_input(void *v, void *start, void *end, int blksize, 1216 void (*intr)(void *), void *arg, const audio_params_t *param) 1217 { 1218 struct auich_softc *sc = v; 1219 struct auich_dmalist *q; 1220 struct auich_dma *p; 1221 size_t size; 1222 int qptr; 1223 #ifdef DIAGNOSTIC 1224 int csts; 1225 #endif 1226 1227 DPRINTF(ICH_DEBUG_DMA, 1228 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1229 start, end, blksize, intr, arg, param)); 1230 1231 sc->pcmi.intr = intr; 1232 sc->pcmi.arg = arg; 1233 1234 #ifdef DIAGNOSTIC 1235 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1236 if (csts & PCI_STATUS_MASTER_ABORT) { 1237 printf("auich_trigger_input: PCI master abort\n"); 1238 } 1239 #endif 1240 1241 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1242 ; 1243 if (!p) { 1244 printf("auich_trigger_input: bad addr %p\n", start); 1245 return (EINVAL); 1246 } 1247 1248 size = (size_t)((caddr_t)end - (caddr_t)start); 1249 1250 /* 1251 * The logic behind this is: 1252 * setup one buffer to play, then LVI dump out the rest 1253 * to the scatter-gather chain. 1254 */ 1255 sc->pcmi.start = DMAADDR(p); 1256 sc->pcmi.p = sc->pcmi.start; 1257 sc->pcmi.end = sc->pcmi.start + size; 1258 sc->pcmi.blksize = blksize; 1259 1260 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1261 q = &sc->pcmi.dmalist[qptr]; 1262 1263 q->base = sc->pcmi.p; 1264 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1265 1266 sc->pcmi.p += blksize; 1267 if (sc->pcmi.p >= sc->pcmi.end) 1268 sc->pcmi.p = sc->pcmi.start; 1269 } 1270 1271 sc->pcmi.qptr = qptr = 0; 1272 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1273 (qptr - 1) & ICH_LVI_MASK); 1274 1275 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1276 sc->sc_cddma + ICH_PCMI_OFF(0)); 1277 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1278 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1279 1280 return (0); 1281 } 1282 1283 static int 1284 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1285 struct auich_dma *p) 1286 { 1287 int error; 1288 1289 p->size = size; 1290 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1291 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1292 &p->nsegs, BUS_DMA_NOWAIT); 1293 if (error) 1294 return (error); 1295 1296 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1297 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1298 if (error) 1299 goto free; 1300 1301 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1302 0, BUS_DMA_NOWAIT, &p->map); 1303 if (error) 1304 goto unmap; 1305 1306 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1307 BUS_DMA_NOWAIT); 1308 if (error) 1309 goto destroy; 1310 return (0); 1311 1312 destroy: 1313 bus_dmamap_destroy(sc->dmat, p->map); 1314 unmap: 1315 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1316 free: 1317 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1318 return (error); 1319 } 1320 1321 static int 1322 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1323 { 1324 1325 bus_dmamap_unload(sc->dmat, p->map); 1326 bus_dmamap_destroy(sc->dmat, p->map); 1327 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1328 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1329 return (0); 1330 } 1331 1332 static int 1333 auich_alloc_cdata(struct auich_softc *sc) 1334 { 1335 bus_dma_segment_t seg; 1336 int error, rseg; 1337 1338 /* 1339 * Allocate the control data structure, and create and load the 1340 * DMA map for it. 1341 */ 1342 if ((error = bus_dmamem_alloc(sc->dmat, 1343 sizeof(struct auich_cdata), 1344 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1345 printf("%s: unable to allocate control data, error = %d\n", 1346 sc->sc_dev.dv_xname, error); 1347 goto fail_0; 1348 } 1349 1350 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1351 sizeof(struct auich_cdata), 1352 (caddr_t *) &sc->sc_cdata, 1353 sc->sc_dmamap_flags)) != 0) { 1354 printf("%s: unable to map control data, error = %d\n", 1355 sc->sc_dev.dv_xname, error); 1356 goto fail_1; 1357 } 1358 1359 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1360 sizeof(struct auich_cdata), 0, 0, 1361 &sc->sc_cddmamap)) != 0) { 1362 printf("%s: unable to create control data DMA map, " 1363 "error = %d\n", sc->sc_dev.dv_xname, error); 1364 goto fail_2; 1365 } 1366 1367 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1368 sc->sc_cdata, sizeof(struct auich_cdata), 1369 NULL, 0)) != 0) { 1370 printf("%s: unable tp load control data DMA map, " 1371 "error = %d\n", sc->sc_dev.dv_xname, error); 1372 goto fail_3; 1373 } 1374 1375 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1376 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1377 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1378 1379 return (0); 1380 1381 fail_3: 1382 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1383 fail_2: 1384 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1385 sizeof(struct auich_cdata)); 1386 fail_1: 1387 bus_dmamem_free(sc->dmat, &seg, rseg); 1388 fail_0: 1389 return (error); 1390 } 1391 1392 static void 1393 auich_powerhook(int why, void *addr) 1394 { 1395 struct auich_softc *sc = (struct auich_softc *)addr; 1396 1397 switch (why) { 1398 case PWR_SUSPEND: 1399 case PWR_STANDBY: 1400 /* Power down */ 1401 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1402 sc->sc_suspend = why; 1403 break; 1404 1405 case PWR_RESUME: 1406 /* Wake up */ 1407 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1408 if (sc->sc_suspend == PWR_RESUME) { 1409 printf("%s: resume without suspend.\n", 1410 sc->sc_dev.dv_xname); 1411 sc->sc_suspend = why; 1412 return; 1413 } 1414 sc->sc_suspend = why; 1415 auich_reset_codec(sc); 1416 DELAY(1000); 1417 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1418 break; 1419 1420 case PWR_SOFTSUSPEND: 1421 case PWR_SOFTSTANDBY: 1422 case PWR_SOFTRESUME: 1423 break; 1424 } 1425 } 1426 1427 /* 1428 * Calibrate card (some boards are overclocked and need scaling) 1429 */ 1430 static void 1431 auich_calibrate(struct auich_softc *sc) 1432 { 1433 struct timeval t1, t2; 1434 uint8_t ociv, nciv; 1435 uint64_t wait_us; 1436 uint32_t actual_48k_rate, bytes, ac97rate; 1437 void *temp_buffer; 1438 struct auich_dma *p; 1439 u_int rate; 1440 1441 /* 1442 * Grab audio from input for fixed interval and compare how 1443 * much we actually get with what we expect. Interval needs 1444 * to be sufficiently short that no interrupts are 1445 * generated. 1446 */ 1447 1448 /* Force the codec to a known state first. */ 1449 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1450 rate = sc->sc_ac97_clock = 48000; 1451 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1452 &rate); 1453 1454 /* Setup a buffer */ 1455 bytes = 64000; 1456 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1457 1458 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1459 ; 1460 if (p == NULL) { 1461 printf("auich_calibrate: bad address %p\n", temp_buffer); 1462 return; 1463 } 1464 sc->pcmi.dmalist[0].base = DMAADDR(p); 1465 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1466 1467 /* 1468 * our data format is stereo, 16 bit so each sample is 4 bytes. 1469 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1470 * we're going to start recording with interrupts disabled and measure 1471 * the time taken for one block to complete. we know the block size, 1472 * we know the time in microseconds, we calculate the sample rate: 1473 * 1474 * actual_rate [bps] = bytes / (time [s] * 4) 1475 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1476 * actual_rate [Hz] = (bytes * 250000) / time [us] 1477 */ 1478 1479 /* prepare */ 1480 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1481 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1482 sc->sc_cddma + ICH_PCMI_OFF(0)); 1483 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1484 (0 - 1) & ICH_LVI_MASK); 1485 1486 /* start */ 1487 microtime(&t1); 1488 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1489 1490 /* wait */ 1491 nciv = ociv; 1492 do { 1493 microtime(&t2); 1494 if (t2.tv_sec - t1.tv_sec > 1) 1495 break; 1496 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1497 ICH_PCMI + ICH_CIV); 1498 } while (nciv == ociv); 1499 microtime(&t2); 1500 1501 /* stop */ 1502 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1503 1504 /* reset */ 1505 DELAY(100); 1506 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1507 1508 /* turn time delta into us */ 1509 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1510 1511 auich_freem(sc, temp_buffer, M_DEVBUF); 1512 1513 if (nciv == ociv) { 1514 printf("%s: ac97 link rate calibration timed out after %" 1515 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1516 return; 1517 } 1518 1519 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1520 1521 if (actual_48k_rate < 50000) 1522 ac97rate = 48000; 1523 else 1524 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1525 1526 printf("%s: measured ac97 link rate at %d Hz", 1527 sc->sc_dev.dv_xname, actual_48k_rate); 1528 if (ac97rate != actual_48k_rate) 1529 printf(", will use %d Hz", ac97rate); 1530 printf("\n"); 1531 1532 sc->sc_ac97_clock = ac97rate; 1533 } 1534
Indexes created Wed Oct 22 13:09:56 GMT 2025