auich.c revision 1.85
1 /* $NetBSD: auich.c,v 1.85 2005/01/15 15:19:52 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.85 2005/01/15 15:19:52 kent Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 187 struct ac97_codec_if *codec_if; 188 struct ac97_host_if host_if; 189 190 /* DMA scatter-gather lists. */ 191 bus_dmamap_t sc_cddmamap; 192 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 193 194 struct auich_cdata *sc_cdata; 195 196 struct auich_ring { 197 int qptr; 198 struct auich_dmalist *dmalist; 199 200 uint32_t start, p, end; 201 int blksize; 202 203 void (*intr)(void *); 204 void *arg; 205 } pcmo, pcmi, mici; 206 207 struct auich_dma *sc_dmas; 208 209 /* SiS 7012 hack */ 210 int sc_sample_shift; 211 int sc_sts_reg; 212 /* 440MX workaround */ 213 int sc_dmamap_flags; 214 215 /* Power Management */ 216 void *sc_powerhook; 217 int sc_suspend; 218 219 /* sysctl */ 220 struct sysctllog *sc_log; 221 uint32_t sc_ac97_clock; 222 int sc_ac97_clock_mib; 223 224 #define AUICH_NFORMATS 3 225 struct audio_format sc_formats[AUICH_NFORMATS]; 226 struct audio_encoding_set *sc_encodings; 227 }; 228 229 /* Debug */ 230 #ifdef AUICH_DEBUG 231 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 232 int auich_debug = 0xfffe; 233 #define ICH_DEBUG_CODECIO 0x0001 234 #define ICH_DEBUG_DMA 0x0002 235 #define ICH_DEBUG_INTR 0x0004 236 #else 237 #define DPRINTF(x,y) /* nothing */ 238 #endif 239 240 static int auich_match(struct device *, struct cfdata *, void *); 241 static void auich_attach(struct device *, struct device *, void *); 242 static int auich_detach(struct device *, int); 243 static int auich_activate(struct device *, enum devact); 244 static int auich_intr(void *); 245 246 CFATTACH_DECL(auich, sizeof(struct auich_softc), 247 auich_match, auich_attach, auich_detach, auich_activate); 248 249 static int auich_query_encoding(void *, struct audio_encoding *); 250 static int auich_set_params(void *, int, int, audio_params_t *, 251 audio_params_t *, stream_filter_list_t *, 252 stream_filter_list_t *); 253 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 254 static int auich_halt_output(void *); 255 static int auich_halt_input(void *); 256 static int auich_getdev(void *, struct audio_device *); 257 static int auich_set_port(void *, mixer_ctrl_t *); 258 static int auich_get_port(void *, mixer_ctrl_t *); 259 static int auich_query_devinfo(void *, mixer_devinfo_t *); 260 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 261 static void auich_freem(void *, void *, struct malloc_type *); 262 static size_t auich_round_buffersize(void *, int, size_t); 263 static paddr_t auich_mappage(void *, void *, off_t, int); 264 static int auich_get_props(void *); 265 static int auich_trigger_output(void *, void *, void *, int, 266 void (*)(void *), void *, const audio_params_t *); 267 static int auich_trigger_input(void *, void *, void *, int, 268 void (*)(void *), void *, const audio_params_t *); 269 270 static int auich_alloc_cdata(struct auich_softc *); 271 272 static int auich_allocmem(struct auich_softc *, size_t, size_t, 273 struct auich_dma *); 274 static int auich_freemem(struct auich_softc *, struct auich_dma *); 275 276 static void auich_powerhook(int, void *); 277 static int auich_set_rate(struct auich_softc *, int, u_long); 278 static int auich_sysctl_verify(SYSCTLFN_ARGS); 279 static void auich_finish_attach(struct device *); 280 static void auich_calibrate(struct auich_softc *); 281 282 static int auich_attach_codec(void *, struct ac97_codec_if *); 283 static int auich_read_codec(void *, uint8_t, uint16_t *); 284 static int auich_write_codec(void *, uint8_t, uint16_t); 285 static int auich_reset_codec(void *); 286 287 const struct audio_hw_if auich_hw_if = { 288 NULL, /* open */ 289 NULL, /* close */ 290 NULL, /* drain */ 291 auich_query_encoding, 292 auich_set_params, 293 auich_round_blocksize, 294 NULL, /* commit_setting */ 295 NULL, /* init_output */ 296 NULL, /* init_input */ 297 NULL, /* start_output */ 298 NULL, /* start_input */ 299 auich_halt_output, 300 auich_halt_input, 301 NULL, /* speaker_ctl */ 302 auich_getdev, 303 NULL, /* getfd */ 304 auich_set_port, 305 auich_get_port, 306 auich_query_devinfo, 307 auich_allocm, 308 auich_freem, 309 auich_round_buffersize, 310 auich_mappage, 311 auich_get_props, 312 auich_trigger_output, 313 auich_trigger_input, 314 NULL, /* dev_ioctl */ 315 }; 316 317 #define AUICH_FORMATS_4CH 1 318 #define AUICH_FORMATS_6CH 2 319 static const struct audio_format auich_formats[AUICH_NFORMATS] = { 320 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 321 2, AUFMT_STEREO, 0, {8000, 48000}}, 322 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 323 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 324 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 325 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 326 }; 327 328 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 329 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 330 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 331 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 332 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 333 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 334 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 335 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 336 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 337 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 338 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 339 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 340 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 341 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 342 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 343 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 344 345 static const struct auich_devtype { 346 pcireg_t id; 347 const char *name; 348 const char *shortname; /* must be less than 11 characters */ 349 } auich_devices[] = { 350 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 351 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 352 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 353 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 354 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 355 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 356 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 357 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 358 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 359 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 360 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 361 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 362 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 363 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 364 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 365 { 0, NULL, NULL }, 366 }; 367 368 static const struct auich_devtype * 369 auich_lookup(struct pci_attach_args *pa) 370 { 371 const struct auich_devtype *d; 372 373 for (d = auich_devices; d->name != NULL; d++) { 374 if (pa->pa_id == d->id) 375 return d; 376 } 377 378 return NULL; 379 } 380 381 static int 382 auich_match(struct device *parent, struct cfdata *match, void *aux) 383 { 384 struct pci_attach_args *pa; 385 386 pa = aux; 387 if (auich_lookup(pa) != NULL) 388 return 1; 389 390 return 0; 391 } 392 393 static void 394 auich_attach(struct device *parent, struct device *self, void *aux) 395 { 396 struct auich_softc *sc; 397 struct pci_attach_args *pa; 398 pci_intr_handle_t ih; 399 pcireg_t v; 400 const char *intrstr; 401 const struct auich_devtype *d; 402 struct sysctlnode *node; 403 int err, node_mib, i; 404 405 sc = (struct auich_softc *)self; 406 pa = aux; 407 aprint_naive(": Audio controller\n"); 408 409 d = auich_lookup(pa); 410 if (d == NULL) 411 panic("auich_attach: impossible"); 412 413 sc->sc_pc = pa->pa_pc; 414 sc->sc_pt = pa->pa_tag; 415 416 aprint_normal(": %s\n", d->name); 417 418 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6) { 419 /* 420 * Use native mode for ICH4/ICH5/ICH6 421 */ 422 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 423 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 424 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 425 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 426 v | ICH_CFG_IOSE); 427 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 428 0, &sc->iot, &sc->mix_ioh, NULL, 429 &sc->mix_size)) { 430 aprint_error("%s: can't map codec i/o space\n", 431 sc->sc_dev.dv_xname); 432 return; 433 } 434 } 435 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 436 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 437 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 438 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 439 v | ICH_CFG_IOSE); 440 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 441 0, &sc->iot, &sc->aud_ioh, NULL, 442 &sc->aud_size)) { 443 aprint_error("%s: can't map device i/o space\n", 444 sc->sc_dev.dv_xname); 445 return; 446 } 447 } 448 } else { 449 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 450 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 451 aprint_error("%s: can't map codec i/o space\n", 452 sc->sc_dev.dv_xname); 453 return; 454 } 455 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 456 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 457 aprint_error("%s: can't map device i/o space\n", 458 sc->sc_dev.dv_xname); 459 return; 460 } 461 } 462 sc->dmat = pa->pa_dmat; 463 464 /* enable bus mastering */ 465 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 466 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 467 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 468 469 /* Map and establish the interrupt. */ 470 if (pci_intr_map(pa, &ih)) { 471 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 472 return; 473 } 474 intrstr = pci_intr_string(pa->pa_pc, ih); 475 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 476 auich_intr, sc); 477 if (sc->sc_ih == NULL) { 478 aprint_error("%s: can't establish interrupt", 479 sc->sc_dev.dv_xname); 480 if (intrstr != NULL) 481 aprint_normal(" at %s", intrstr); 482 aprint_normal("\n"); 483 return; 484 } 485 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 486 487 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 488 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 489 "0x%02x", PCI_REVISION(pa->pa_class)); 490 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 491 492 /* SiS 7012 needs special handling */ 493 if (d->id == PCIID_SIS7012) { 494 sc->sc_sts_reg = ICH_PICB; 495 sc->sc_sample_shift = 0; 496 /* Un-mute output. From Linux. */ 497 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 498 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 499 ICH_SIS_CTL_UNMUTE); 500 } else { 501 sc->sc_sts_reg = ICH_STS; 502 sc->sc_sample_shift = 1; 503 } 504 505 /* Workaround for a 440MX B-stepping erratum */ 506 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 507 if (d->id == PCIID_440MX) { 508 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 509 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 510 } 511 512 /* Set up DMA lists. */ 513 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 514 auich_alloc_cdata(sc); 515 516 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 517 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 518 519 sc->host_if.arg = sc; 520 sc->host_if.attach = auich_attach_codec; 521 sc->host_if.read = auich_read_codec; 522 sc->host_if.write = auich_write_codec; 523 sc->host_if.reset = auich_reset_codec; 524 525 if (ac97_attach(&sc->host_if, self) != 0) 526 return; 527 528 /* setup audio_format */ 529 memcpy(sc->sc_formats, auich_formats, sizeof(auich_formats)); 530 if (!AC97_IS_4CH(sc->codec_if)) 531 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_4CH]); 532 if (!AC97_IS_6CH(sc->codec_if)) 533 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_6CH]); 534 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 535 for (i = 0; i < AUICH_NFORMATS; i++) { 536 sc->sc_formats[i].frequency_type = 1; 537 sc->sc_formats[i].frequency[0] = 48000; 538 } 539 } 540 541 if (0 != auconv_create_encodings(sc->sc_formats, AUICH_NFORMATS, 542 &sc->sc_encodings)) { 543 return; 544 } 545 546 /* Watch for power change */ 547 sc->sc_suspend = PWR_RESUME; 548 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 549 550 config_interrupts(self, auich_finish_attach); 551 552 /* sysctl setup */ 553 if (AC97_IS_FIXED_RATE(sc->codec_if)) 554 return; 555 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 556 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 557 CTL_HW, CTL_EOL); 558 if (err != 0) 559 goto sysctl_err; 560 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 561 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 562 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 563 if (err != 0) 564 goto sysctl_err; 565 node_mib = node->sysctl_num; 566 /* passing the sc address instead of &sc->sc_ac97_clock */ 567 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 568 CTLTYPE_INT, "ac97rate", 569 SYSCTL_DESCR("AC'97 codec link rate"), 570 auich_sysctl_verify, 0, sc, 0, 571 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 572 if (err != 0) 573 goto sysctl_err; 574 sc->sc_ac97_clock_mib = node->sysctl_num; 575 576 return; 577 578 sysctl_err: 579 printf("%s: failed to add sysctl nodes. (%d)\n", 580 sc->sc_dev.dv_xname, err); 581 return; /* failure of sysctl is not fatal. */ 582 } 583 584 static int 585 auich_activate(struct device *self, enum devact act) 586 { 587 struct auich_softc *sc; 588 int ret; 589 590 sc = (struct auich_softc *)self; 591 ret = 0; 592 switch (act) { 593 case DVACT_ACTIVATE: 594 return EOPNOTSUPP; 595 case DVACT_DEACTIVATE: 596 if (sc->sc_audiodev != NULL) 597 ret = config_deactivate(sc->sc_audiodev); 598 return ret; 599 } 600 return EOPNOTSUPP; 601 } 602 603 static int 604 auich_detach(struct device *self, int flags) 605 { 606 struct auich_softc *sc; 607 608 sc = (struct auich_softc *)self; 609 610 /* audio */ 611 if (sc->sc_audiodev != NULL) 612 config_detach(sc->sc_audiodev, flags); 613 614 /* sysctl */ 615 sysctl_teardown(&sc->sc_log); 616 617 /* audio_encoding_set */ 618 auconv_delete_encodings(sc->sc_encodings); 619 620 /* ac97 */ 621 if (sc->codec_if != NULL) 622 sc->codec_if->vtbl->detach(sc->codec_if); 623 624 /* PCI */ 625 if (sc->sc_ih != NULL) 626 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 627 if (sc->mix_size != 0) 628 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 629 if (sc->aud_size != 0) 630 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 631 return 0; 632 } 633 634 static int 635 auich_sysctl_verify(SYSCTLFN_ARGS) 636 { 637 int error, tmp; 638 struct sysctlnode node; 639 struct auich_softc *sc; 640 641 node = *rnode; 642 sc = rnode->sysctl_data; 643 tmp = sc->sc_ac97_clock; 644 node.sysctl_data = &tmp; 645 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 646 if (error || newp == NULL) 647 return error; 648 649 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 650 if (tmp < 48000 || tmp > 96000) 651 return EINVAL; 652 sc->sc_ac97_clock = tmp; 653 } 654 655 return 0; 656 } 657 658 static void 659 auich_finish_attach(struct device *self) 660 { 661 struct auich_softc *sc; 662 663 sc = (void *)self; 664 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 665 auich_calibrate(sc); 666 667 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 668 } 669 670 #define ICH_CODECIO_INTERVAL 10 671 static int 672 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 673 { 674 struct auich_softc *sc; 675 int i; 676 uint32_t status; 677 678 sc = v; 679 /* wait for an access semaphore */ 680 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 681 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 682 DELAY(ICH_CODECIO_INTERVAL)); 683 684 if (i > 0) { 685 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 686 DPRINTF(ICH_DEBUG_CODECIO, 687 ("auich_read_codec(%x, %x)\n", reg, *val)); 688 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 689 if (status & ICH_RCS) { 690 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 691 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 692 *val = 0xffff; 693 DPRINTF(ICH_DEBUG_CODECIO, 694 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 695 return -1; 696 } 697 return 0; 698 } else { 699 DPRINTF(ICH_DEBUG_CODECIO, 700 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 701 return -1; 702 } 703 } 704 705 static int 706 auich_write_codec(void *v, uint8_t reg, uint16_t val) 707 { 708 struct auich_softc *sc; 709 int i; 710 711 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 712 sc = v; 713 /* wait for an access semaphore */ 714 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 715 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 716 DELAY(ICH_CODECIO_INTERVAL)); 717 718 if (i > 0) { 719 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 720 return 0; 721 } else { 722 DPRINTF(ICH_DEBUG_CODECIO, 723 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 724 return -1; 725 } 726 } 727 728 static int 729 auich_attach_codec(void *v, struct ac97_codec_if *cif) 730 { 731 struct auich_softc *sc; 732 733 sc = v; 734 sc->codec_if = cif; 735 return 0; 736 } 737 738 static int 739 auich_reset_codec(void *v) 740 { 741 struct auich_softc *sc; 742 int i; 743 uint32_t control, status; 744 745 sc = v; 746 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 747 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 748 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 749 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 750 751 for (i = 500000; i >= 0; i--) { 752 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 753 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 754 break; 755 DELAY(1); 756 } 757 if (i <= 0) { 758 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 759 return ETIMEDOUT; 760 } 761 #ifdef DEBUG 762 if (status & ICH_SCR) 763 printf("%s: The 2nd codec is ready.\n", 764 sc->sc_dev.dv_xname); 765 if (status & ICH_S2CR) 766 printf("%s: The 3rd codec is ready.\n", 767 sc->sc_dev.dv_xname); 768 #endif 769 return 0; 770 } 771 772 static int 773 auich_query_encoding(void *v, struct audio_encoding *aep) 774 { 775 struct auich_softc *sc; 776 777 sc = (struct auich_softc *)v; 778 return auconv_query_encoding(sc->sc_encodings, aep); 779 } 780 781 static int 782 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 783 { 784 int ret; 785 u_int ratetmp; 786 787 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 788 ratetmp = srate; 789 if (mode == AUMODE_RECORD) 790 return sc->codec_if->vtbl->set_rate(sc->codec_if, 791 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 792 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 793 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 794 if (ret) 795 return ret; 796 ratetmp = srate; 797 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 798 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 799 if (ret) 800 return ret; 801 ratetmp = srate; 802 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 803 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 804 return ret; 805 } 806 807 static int 808 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 809 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 810 { 811 struct auich_softc *sc; 812 audio_params_t *p; 813 stream_filter_list_t *fil; 814 int mode, index; 815 uint32_t control; 816 817 sc = v; 818 for (mode = AUMODE_RECORD; mode != -1; 819 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 820 if ((setmode & mode) == 0) 821 continue; 822 823 p = mode == AUMODE_PLAY ? play : rec; 824 fil = mode == AUMODE_PLAY ? pfil : rfil; 825 if (p == NULL) 826 continue; 827 828 if (p->sample_rate < 8000 || 829 p->sample_rate > 48000) 830 return EINVAL; 831 832 index = auconv_set_converter(sc->sc_formats, AUICH_NFORMATS, 833 mode, p, TRUE, fil); 834 if (index < 0) 835 return EINVAL; 836 if (fil->req_size > 0) 837 p = &fil->filters[0].param; 838 /* p represents HW encoding */ 839 if (sc->sc_formats[index].frequency_type != 1 840 && auich_set_rate(sc, mode, p->sample_rate)) 841 return EINVAL; 842 if (mode == AUMODE_PLAY) { 843 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 844 control &= ~ICH_PCM246_MASK; 845 if (p->channels == 4) { 846 control |= ICH_PCM4; 847 } else if (p->channels == 6) { 848 control |= ICH_PCM6; 849 } 850 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 851 } 852 } 853 854 return 0; 855 } 856 857 static int 858 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 859 { 860 861 return blk & ~0x3f; /* keep good alignment */ 862 } 863 864 static int 865 auich_halt_output(void *v) 866 { 867 struct auich_softc *sc; 868 869 sc = v; 870 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 871 872 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 873 sc->pcmo.intr = NULL; 874 875 return 0; 876 } 877 878 static int 879 auich_halt_input(void *v) 880 { 881 struct auich_softc *sc; 882 883 sc = v; 884 DPRINTF(ICH_DEBUG_DMA, 885 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 886 887 /* XXX halt both unless known otherwise */ 888 889 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 890 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 891 sc->pcmi.intr = NULL; 892 893 return 0; 894 } 895 896 static int 897 auich_getdev(void *v, struct audio_device *adp) 898 { 899 struct auich_softc *sc; 900 901 sc = v; 902 *adp = sc->sc_audev; 903 return 0; 904 } 905 906 static int 907 auich_set_port(void *v, mixer_ctrl_t *cp) 908 { 909 struct auich_softc *sc; 910 911 sc = v; 912 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 913 } 914 915 static int 916 auich_get_port(void *v, mixer_ctrl_t *cp) 917 { 918 struct auich_softc *sc; 919 920 sc = v; 921 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 922 } 923 924 static int 925 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 926 { 927 struct auich_softc *sc; 928 929 sc = v; 930 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 931 } 932 933 static void * 934 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 935 int flags) 936 { 937 struct auich_softc *sc; 938 struct auich_dma *p; 939 int error; 940 941 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 942 return NULL; 943 944 p = malloc(sizeof(*p), pool, flags|M_ZERO); 945 if (p == NULL) 946 return NULL; 947 948 sc = v; 949 error = auich_allocmem(sc, size, 0, p); 950 if (error) { 951 free(p, pool); 952 return NULL; 953 } 954 955 p->next = sc->sc_dmas; 956 sc->sc_dmas = p; 957 958 return KERNADDR(p); 959 } 960 961 static void 962 auich_freem(void *v, void *ptr, struct malloc_type *pool) 963 { 964 struct auich_softc *sc; 965 struct auich_dma *p, **pp; 966 967 sc = v; 968 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 969 if (KERNADDR(p) == ptr) { 970 auich_freemem(sc, p); 971 *pp = p->next; 972 free(p, pool); 973 return; 974 } 975 } 976 } 977 978 static size_t 979 auich_round_buffersize(void *v, int direction, size_t size) 980 { 981 982 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 983 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 984 985 return size; 986 } 987 988 static paddr_t 989 auich_mappage(void *v, void *mem, off_t off, int prot) 990 { 991 struct auich_softc *sc; 992 struct auich_dma *p; 993 994 if (off < 0) 995 return -1; 996 sc = v; 997 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 998 continue; 999 if (!p) 1000 return -1; 1001 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1002 off, prot, BUS_DMA_WAITOK); 1003 } 1004 1005 static int 1006 auich_get_props(void *v) 1007 { 1008 struct auich_softc *sc; 1009 int props; 1010 1011 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1012 sc = v; 1013 /* 1014 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1015 * rate because of aurateconv. Applications can't know what rate the 1016 * device can process in the case of mmap(). 1017 */ 1018 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 1019 props |= AUDIO_PROP_MMAP; 1020 return props; 1021 } 1022 1023 static int 1024 auich_intr(void *v) 1025 { 1026 struct auich_softc *sc; 1027 int ret, gsts; 1028 #ifdef DIAGNOSTIC 1029 int csts; 1030 #endif 1031 1032 sc = v; 1033 ret = 0; 1034 #ifdef DIAGNOSTIC 1035 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1036 if (csts & PCI_STATUS_MASTER_ABORT) { 1037 printf("auich_intr: PCI master abort\n"); 1038 } 1039 #endif 1040 1041 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 1042 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1043 1044 if (gsts & ICH_POINT) { 1045 int sts; 1046 1047 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1048 ICH_PCMO + sc->sc_sts_reg); 1049 DPRINTF(ICH_DEBUG_INTR, 1050 ("auich_intr: osts=0x%x\n", sts)); 1051 1052 if (sts & ICH_FIFOE) 1053 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1054 1055 if (sts & ICH_BCIS) { 1056 struct auich_dmalist *q; 1057 int blksize, qptr, i; 1058 1059 blksize = sc->pcmo.blksize; 1060 qptr = sc->pcmo.qptr; 1061 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1062 ICH_PCMO + ICH_CIV); 1063 1064 while (qptr != i) { 1065 q = &sc->pcmo.dmalist[qptr]; 1066 1067 q->base = sc->pcmo.p; 1068 q->len = (blksize >> sc->sc_sample_shift) | 1069 ICH_DMAF_IOC; 1070 DPRINTF(ICH_DEBUG_INTR, 1071 ("auich_intr: %p, %p = %x @ 0x%x\n", 1072 &sc->pcmo.dmalist[i], q, q->len, q->base)); 1073 1074 sc->pcmo.p += blksize; 1075 if (sc->pcmo.p >= sc->pcmo.end) 1076 sc->pcmo.p = sc->pcmo.start; 1077 1078 qptr = (qptr + 1) & ICH_LVI_MASK; 1079 if (sc->pcmo.intr) 1080 sc->pcmo.intr(sc->pcmo.arg); 1081 } 1082 1083 sc->pcmo.qptr = qptr; 1084 bus_space_write_1(sc->iot, sc->aud_ioh, 1085 ICH_PCMO + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1086 } 1087 1088 /* int ack */ 1089 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1090 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1091 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1092 ret++; 1093 } 1094 1095 if (gsts & ICH_PIINT) { 1096 int sts; 1097 1098 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1099 ICH_PCMI + sc->sc_sts_reg); 1100 DPRINTF(ICH_DEBUG_INTR, 1101 ("auich_intr: ists=0x%x\n", sts)); 1102 1103 if (sts & ICH_FIFOE) 1104 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1105 1106 if (sts & ICH_BCIS) { 1107 struct auich_dmalist *q; 1108 int blksize, qptr, i; 1109 1110 blksize = sc->pcmi.blksize; 1111 qptr = sc->pcmi.qptr; 1112 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1113 ICH_PCMI + ICH_CIV); 1114 1115 while (qptr != i) { 1116 q = &sc->pcmi.dmalist[qptr]; 1117 1118 q->base = sc->pcmi.p; 1119 q->len = (blksize >> sc->sc_sample_shift) | 1120 ICH_DMAF_IOC; 1121 DPRINTF(ICH_DEBUG_INTR, 1122 ("auich_intr: %p, %p = %x @ 0x%x\n", 1123 &sc->pcmi.dmalist[i], q, q->len, q->base)); 1124 1125 sc->pcmi.p += blksize; 1126 if (sc->pcmi.p >= sc->pcmi.end) 1127 sc->pcmi.p = sc->pcmi.start; 1128 1129 qptr = (qptr + 1) & ICH_LVI_MASK; 1130 if (sc->pcmi.intr) 1131 sc->pcmi.intr(sc->pcmi.arg); 1132 } 1133 1134 sc->pcmi.qptr = qptr; 1135 bus_space_write_1(sc->iot, sc->aud_ioh, 1136 ICH_PCMI + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1137 } 1138 1139 /* int ack */ 1140 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1141 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1142 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1143 ret++; 1144 } 1145 1146 if (gsts & ICH_MIINT) { 1147 int sts; 1148 1149 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1150 ICH_MICI + sc->sc_sts_reg); 1151 DPRINTF(ICH_DEBUG_INTR, 1152 ("auich_intr: ists=0x%x\n", sts)); 1153 1154 if (sts & ICH_FIFOE) 1155 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1156 1157 /* TODO mic input DMA */ 1158 1159 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1160 } 1161 1162 return ret; 1163 } 1164 1165 static int 1166 auich_trigger_output(void *v, void *start, void *end, int blksize, 1167 void (*intr)(void *), void *arg, const audio_params_t *param) 1168 { 1169 struct auich_softc *sc; 1170 struct auich_dmalist *q; 1171 struct auich_dma *p; 1172 size_t size; 1173 int qptr; 1174 #ifdef DIAGNOSTIC 1175 int csts; 1176 #endif 1177 1178 DPRINTF(ICH_DEBUG_DMA, 1179 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1180 start, end, blksize, intr, arg, param)); 1181 sc = v; 1182 sc->pcmo.intr = intr; 1183 sc->pcmo.arg = arg; 1184 #ifdef DIAGNOSTIC 1185 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1186 if (csts & PCI_STATUS_MASTER_ABORT) { 1187 printf("auich_trigger_output: PCI master abort\n"); 1188 } 1189 #endif 1190 1191 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1192 continue; 1193 if (!p) { 1194 printf("auich_trigger_output: bad addr %p\n", start); 1195 return EINVAL; 1196 } 1197 1198 size = (size_t)((caddr_t)end - (caddr_t)start); 1199 1200 /* 1201 * The logic behind this is: 1202 * setup one buffer to play, then LVI dump out the rest 1203 * to the scatter-gather chain. 1204 */ 1205 sc->pcmo.start = DMAADDR(p); 1206 sc->pcmo.p = sc->pcmo.start; 1207 sc->pcmo.end = sc->pcmo.start + size; 1208 sc->pcmo.blksize = blksize; 1209 1210 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1211 q = &sc->pcmo.dmalist[qptr]; 1212 1213 q->base = sc->pcmo.p; 1214 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1215 1216 sc->pcmo.p += blksize; 1217 if (sc->pcmo.p >= sc->pcmo.end) 1218 sc->pcmo.p = sc->pcmo.start; 1219 } 1220 1221 sc->pcmo.qptr = qptr = 0; 1222 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1223 (qptr - 1) & ICH_LVI_MASK); 1224 1225 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1226 sc->sc_cddma + ICH_PCMO_OFF(0)); 1227 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1228 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1229 1230 return 0; 1231 } 1232 1233 static int 1234 auich_trigger_input(void *v, void *start, void *end, int blksize, 1235 void (*intr)(void *), void *arg, const audio_params_t *param) 1236 { 1237 struct auich_softc *sc; 1238 struct auich_dmalist *q; 1239 struct auich_dma *p; 1240 size_t size; 1241 int qptr; 1242 #ifdef DIAGNOSTIC 1243 int csts; 1244 #endif 1245 1246 DPRINTF(ICH_DEBUG_DMA, 1247 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1248 start, end, blksize, intr, arg, param)); 1249 sc = v; 1250 sc->pcmi.intr = intr; 1251 sc->pcmi.arg = arg; 1252 1253 #ifdef DIAGNOSTIC 1254 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1255 if (csts & PCI_STATUS_MASTER_ABORT) { 1256 printf("auich_trigger_input: PCI master abort\n"); 1257 } 1258 #endif 1259 1260 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1261 continue; 1262 if (!p) { 1263 printf("auich_trigger_input: bad addr %p\n", start); 1264 return EINVAL; 1265 } 1266 1267 size = (size_t)((caddr_t)end - (caddr_t)start); 1268 1269 /* 1270 * The logic behind this is: 1271 * setup one buffer to play, then LVI dump out the rest 1272 * to the scatter-gather chain. 1273 */ 1274 sc->pcmi.start = DMAADDR(p); 1275 sc->pcmi.p = sc->pcmi.start; 1276 sc->pcmi.end = sc->pcmi.start + size; 1277 sc->pcmi.blksize = blksize; 1278 1279 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1280 q = &sc->pcmi.dmalist[qptr]; 1281 1282 q->base = sc->pcmi.p; 1283 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1284 1285 sc->pcmi.p += blksize; 1286 if (sc->pcmi.p >= sc->pcmi.end) 1287 sc->pcmi.p = sc->pcmi.start; 1288 } 1289 1290 sc->pcmi.qptr = qptr = 0; 1291 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1292 (qptr - 1) & ICH_LVI_MASK); 1293 1294 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1295 sc->sc_cddma + ICH_PCMI_OFF(0)); 1296 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1297 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1298 1299 return 0; 1300 } 1301 1302 static int 1303 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1304 struct auich_dma *p) 1305 { 1306 int error; 1307 1308 p->size = size; 1309 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1310 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1311 &p->nsegs, BUS_DMA_NOWAIT); 1312 if (error) 1313 return error; 1314 1315 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1316 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1317 if (error) 1318 goto free; 1319 1320 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1321 0, BUS_DMA_NOWAIT, &p->map); 1322 if (error) 1323 goto unmap; 1324 1325 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1326 BUS_DMA_NOWAIT); 1327 if (error) 1328 goto destroy; 1329 return 0; 1330 1331 destroy: 1332 bus_dmamap_destroy(sc->dmat, p->map); 1333 unmap: 1334 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1335 free: 1336 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1337 return error; 1338 } 1339 1340 static int 1341 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1342 { 1343 1344 bus_dmamap_unload(sc->dmat, p->map); 1345 bus_dmamap_destroy(sc->dmat, p->map); 1346 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1347 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1348 return 0; 1349 } 1350 1351 static int 1352 auich_alloc_cdata(struct auich_softc *sc) 1353 { 1354 bus_dma_segment_t seg; 1355 int error, rseg; 1356 1357 /* 1358 * Allocate the control data structure, and create and load the 1359 * DMA map for it. 1360 */ 1361 if ((error = bus_dmamem_alloc(sc->dmat, 1362 sizeof(struct auich_cdata), 1363 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1364 printf("%s: unable to allocate control data, error = %d\n", 1365 sc->sc_dev.dv_xname, error); 1366 goto fail_0; 1367 } 1368 1369 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1370 sizeof(struct auich_cdata), 1371 (caddr_t *) &sc->sc_cdata, 1372 sc->sc_dmamap_flags)) != 0) { 1373 printf("%s: unable to map control data, error = %d\n", 1374 sc->sc_dev.dv_xname, error); 1375 goto fail_1; 1376 } 1377 1378 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1379 sizeof(struct auich_cdata), 0, 0, 1380 &sc->sc_cddmamap)) != 0) { 1381 printf("%s: unable to create control data DMA map, " 1382 "error = %d\n", sc->sc_dev.dv_xname, error); 1383 goto fail_2; 1384 } 1385 1386 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1387 sc->sc_cdata, sizeof(struct auich_cdata), 1388 NULL, 0)) != 0) { 1389 printf("%s: unable tp load control data DMA map, " 1390 "error = %d\n", sc->sc_dev.dv_xname, error); 1391 goto fail_3; 1392 } 1393 1394 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1395 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1396 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1397 1398 return 0; 1399 1400 fail_3: 1401 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1402 fail_2: 1403 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1404 sizeof(struct auich_cdata)); 1405 fail_1: 1406 bus_dmamem_free(sc->dmat, &seg, rseg); 1407 fail_0: 1408 return error; 1409 } 1410 1411 static void 1412 auich_powerhook(int why, void *addr) 1413 { 1414 struct auich_softc *sc; 1415 1416 sc = (struct auich_softc *)addr; 1417 switch (why) { 1418 case PWR_SUSPEND: 1419 case PWR_STANDBY: 1420 /* Power down */ 1421 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1422 sc->sc_suspend = why; 1423 break; 1424 1425 case PWR_RESUME: 1426 /* Wake up */ 1427 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1428 if (sc->sc_suspend == PWR_RESUME) { 1429 printf("%s: resume without suspend.\n", 1430 sc->sc_dev.dv_xname); 1431 sc->sc_suspend = why; 1432 return; 1433 } 1434 sc->sc_suspend = why; 1435 auich_reset_codec(sc); 1436 DELAY(1000); 1437 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1438 break; 1439 1440 case PWR_SOFTSUSPEND: 1441 case PWR_SOFTSTANDBY: 1442 case PWR_SOFTRESUME: 1443 break; 1444 } 1445 } 1446 1447 /* 1448 * Calibrate card (some boards are overclocked and need scaling) 1449 */ 1450 static void 1451 auich_calibrate(struct auich_softc *sc) 1452 { 1453 struct timeval t1, t2; 1454 uint8_t ociv, nciv; 1455 uint64_t wait_us; 1456 uint32_t actual_48k_rate, bytes, ac97rate; 1457 void *temp_buffer; 1458 struct auich_dma *p; 1459 u_int rate; 1460 1461 /* 1462 * Grab audio from input for fixed interval and compare how 1463 * much we actually get with what we expect. Interval needs 1464 * to be sufficiently short that no interrupts are 1465 * generated. 1466 */ 1467 1468 /* Force the codec to a known state first. */ 1469 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1470 rate = sc->sc_ac97_clock = 48000; 1471 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1472 &rate); 1473 1474 /* Setup a buffer */ 1475 bytes = 64000; 1476 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1477 1478 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1479 continue; 1480 if (p == NULL) { 1481 printf("auich_calibrate: bad address %p\n", temp_buffer); 1482 return; 1483 } 1484 sc->pcmi.dmalist[0].base = DMAADDR(p); 1485 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1486 1487 /* 1488 * our data format is stereo, 16 bit so each sample is 4 bytes. 1489 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1490 * we're going to start recording with interrupts disabled and measure 1491 * the time taken for one block to complete. we know the block size, 1492 * we know the time in microseconds, we calculate the sample rate: 1493 * 1494 * actual_rate [bps] = bytes / (time [s] * 4) 1495 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1496 * actual_rate [Hz] = (bytes * 250000) / time [us] 1497 */ 1498 1499 /* prepare */ 1500 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1501 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1502 sc->sc_cddma + ICH_PCMI_OFF(0)); 1503 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1504 (0 - 1) & ICH_LVI_MASK); 1505 1506 /* start */ 1507 microtime(&t1); 1508 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1509 1510 /* wait */ 1511 nciv = ociv; 1512 do { 1513 microtime(&t2); 1514 if (t2.tv_sec - t1.tv_sec > 1) 1515 break; 1516 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1517 ICH_PCMI + ICH_CIV); 1518 } while (nciv == ociv); 1519 microtime(&t2); 1520 1521 /* stop */ 1522 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1523 1524 /* reset */ 1525 DELAY(100); 1526 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1527 1528 /* turn time delta into us */ 1529 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1530 1531 auich_freem(sc, temp_buffer, M_DEVBUF); 1532 1533 if (nciv == ociv) { 1534 printf("%s: ac97 link rate calibration timed out after %" 1535 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1536 return; 1537 } 1538 1539 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1540 1541 if (actual_48k_rate < 50000) 1542 ac97rate = 48000; 1543 else 1544 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1545 1546 printf("%s: measured ac97 link rate at %d Hz", 1547 sc->sc_dev.dv_xname, actual_48k_rate); 1548 if (ac97rate != actual_48k_rate) 1549 printf(", will use %d Hz", ac97rate); 1550 printf("\n"); 1551 1552 sc->sc_ac97_clock = ac97rate; 1553 } 1554
Indexes created Thu Oct 23 18:09:57 GMT 2025