auich.c revision 1.85.2.1
1 /* $NetBSD: auich.c,v 1.85.2.1 2005/04/29 11:29:05 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.85.2.1 2005/04/29 11:29:05 kent Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 187 struct ac97_codec_if *codec_if; 188 struct ac97_host_if host_if; 189 int sc_codecnum; 190 int sc_codectype; 191 192 /* DMA scatter-gather lists. */ 193 bus_dmamap_t sc_cddmamap; 194 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 195 196 struct auich_cdata *sc_cdata; 197 198 struct auich_ring { 199 int qptr; 200 struct auich_dmalist *dmalist; 201 202 uint32_t start, p, end; 203 int blksize; 204 205 void (*intr)(void *); 206 void *arg; 207 } pcmo, pcmi, mici; 208 209 struct auich_dma *sc_dmas; 210 211 /* SiS 7012 hack */ 212 int sc_sample_shift; 213 int sc_sts_reg; 214 /* 440MX workaround */ 215 int sc_dmamap_flags; 216 217 /* Power Management */ 218 void *sc_powerhook; 219 int sc_suspend; 220 struct pci_conf_state sc_pciconf; 221 222 /* sysctl */ 223 struct sysctllog *sc_log; 224 uint32_t sc_ac97_clock; 225 int sc_ac97_clock_mib; 226 227 int sc_modem_offset; 228 229 #define AUICH_AUDIO_NFORMATS 3 230 #define AUICH_MODEM_NFORMATS 1 231 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 232 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 233 struct audio_encoding_set *sc_encodings; 234 }; 235 236 /* Debug */ 237 #ifdef AUICH_DEBUG 238 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 239 int auich_debug = 0xfffe; 240 #define ICH_DEBUG_CODECIO 0x0001 241 #define ICH_DEBUG_DMA 0x0002 242 #define ICH_DEBUG_INTR 0x0004 243 #else 244 #define DPRINTF(x,y) /* nothing */ 245 #endif 246 247 static int auich_match(struct device *, struct cfdata *, void *); 248 static void auich_attach(struct device *, struct device *, void *); 249 static int auich_detach(struct device *, int); 250 static int auich_activate(struct device *, enum devact); 251 static int auich_intr(void *); 252 253 CFATTACH_DECL(auich, sizeof(struct auich_softc), 254 auich_match, auich_attach, auich_detach, auich_activate); 255 256 static int auich_query_encoding(void *, struct audio_encoding *); 257 static int auich_set_params(void *, int, int, audio_params_t *, 258 audio_params_t *, stream_filter_list_t *, 259 stream_filter_list_t *); 260 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 261 static void auich_halt_pipe(struct auich_softc *, int); 262 static int auich_halt_output(void *); 263 static int auich_halt_input(void *); 264 static int auich_getdev(void *, struct audio_device *); 265 static int auich_set_port(void *, mixer_ctrl_t *); 266 static int auich_get_port(void *, mixer_ctrl_t *); 267 static int auich_query_devinfo(void *, mixer_devinfo_t *); 268 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 269 static void auich_freem(void *, void *, struct malloc_type *); 270 static size_t auich_round_buffersize(void *, int, size_t); 271 static paddr_t auich_mappage(void *, void *, off_t, int); 272 static int auich_get_props(void *); 273 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 274 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 275 static int auich_trigger_output(void *, void *, void *, int, 276 void (*)(void *), void *, const audio_params_t *); 277 static int auich_trigger_input(void *, void *, void *, int, 278 void (*)(void *), void *, const audio_params_t *); 279 280 static int auich_alloc_cdata(struct auich_softc *); 281 282 static int auich_allocmem(struct auich_softc *, size_t, size_t, 283 struct auich_dma *); 284 static int auich_freemem(struct auich_softc *, struct auich_dma *); 285 286 static void auich_powerhook(int, void *); 287 static int auich_set_rate(struct auich_softc *, int, u_long); 288 static int auich_sysctl_verify(SYSCTLFN_ARGS); 289 static void auich_finish_attach(struct device *); 290 static void auich_calibrate(struct auich_softc *); 291 static void auich_clear_cas(struct auich_softc *); 292 293 static int auich_attach_codec(void *, struct ac97_codec_if *); 294 static int auich_read_codec(void *, uint8_t, uint16_t *); 295 static int auich_write_codec(void *, uint8_t, uint16_t); 296 static int auich_reset_codec(void *); 297 298 const struct audio_hw_if auich_hw_if = { 299 NULL, /* open */ 300 NULL, /* close */ 301 NULL, /* drain */ 302 auich_query_encoding, 303 auich_set_params, 304 auich_round_blocksize, 305 NULL, /* commit_setting */ 306 NULL, /* init_output */ 307 NULL, /* init_input */ 308 NULL, /* start_output */ 309 NULL, /* start_input */ 310 auich_halt_output, 311 auich_halt_input, 312 NULL, /* speaker_ctl */ 313 auich_getdev, 314 NULL, /* getfd */ 315 auich_set_port, 316 auich_get_port, 317 auich_query_devinfo, 318 auich_allocm, 319 auich_freem, 320 auich_round_buffersize, 321 auich_mappage, 322 auich_get_props, 323 auich_trigger_output, 324 auich_trigger_input, 325 NULL, /* dev_ioctl */ 326 }; 327 328 #define AUICH_FORMATS_1CH 0 329 #define AUICH_FORMATS_4CH 1 330 #define AUICH_FORMATS_6CH 2 331 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 332 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 333 2, AUFMT_STEREO, 0, {8000, 48000}}, 334 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 335 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 336 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 337 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 338 }; 339 340 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 341 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 342 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 343 }; 344 345 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 346 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 347 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 348 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 349 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 350 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 351 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 352 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 353 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 354 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 355 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 356 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 357 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 358 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 359 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 360 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 361 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 362 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 363 364 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 365 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 366 367 struct auich_devtype { 368 pcireg_t id; 369 const char *name; 370 const char *shortname; /* must be less than 11 characters */ 371 }; 372 373 static const struct auich_devtype auich_audio_devices[] = { 374 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 375 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 376 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 377 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 378 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 379 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 380 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 381 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 382 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 383 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 384 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 385 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 386 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 387 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 388 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 389 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 390 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 391 { 0, NULL, NULL }, 392 }; 393 394 static const struct auich_devtype auich_modem_devices[] = { 395 #ifdef AUICH_ATTACH_MODEM 396 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 397 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 398 #endif 399 { 0, NULL, NULL }, 400 }; 401 402 static const struct auich_devtype * 403 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 404 { 405 const struct auich_devtype *d; 406 407 for (d = auich_devices; d->name != NULL; d++) { 408 if (pa->pa_id == d->id) 409 return d; 410 } 411 412 return NULL; 413 } 414 415 static int 416 auich_match(struct device *parent, struct cfdata *match, void *aux) 417 { 418 struct pci_attach_args *pa; 419 420 pa = aux; 421 if (auich_lookup(pa, auich_audio_devices) != NULL) 422 return 1; 423 if (auich_lookup(pa, auich_modem_devices) != NULL) 424 return 1; 425 426 return 0; 427 } 428 429 static void 430 auich_attach(struct device *parent, struct device *self, void *aux) 431 { 432 struct auich_softc *sc; 433 struct pci_attach_args *pa; 434 pci_intr_handle_t ih; 435 pcireg_t v; 436 const char *intrstr; 437 const struct auich_devtype *d; 438 struct sysctlnode *node, *node_ac97clock; 439 int err, node_mib, i; 440 441 sc = (struct auich_softc *)self; 442 pa = aux; 443 444 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 445 sc->sc_modem_offset = 0x10; 446 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 447 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 448 sc->sc_modem_offset = 0; 449 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 450 } else 451 panic("auich_attach: impossible"); 452 453 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 454 aprint_naive(": Audio controller\n"); 455 else 456 aprint_naive(": Modem controller\n"); 457 458 sc->sc_pc = pa->pa_pc; 459 sc->sc_pt = pa->pa_tag; 460 461 aprint_normal(": %s\n", d->name); 462 463 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 464 || d->id == PCIID_ICH4MODEM) { 465 /* 466 * Use native mode for ICH4/ICH5/ICH6 467 */ 468 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 469 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 470 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 471 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 472 v | ICH_CFG_IOSE); 473 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 474 0, &sc->iot, &sc->mix_ioh, NULL, 475 &sc->mix_size)) { 476 aprint_error("%s: can't map codec i/o space\n", 477 sc->sc_dev.dv_xname); 478 return; 479 } 480 } 481 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 482 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 483 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 484 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 485 v | ICH_CFG_IOSE); 486 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 487 0, &sc->iot, &sc->aud_ioh, NULL, 488 &sc->aud_size)) { 489 aprint_error("%s: can't map device i/o space\n", 490 sc->sc_dev.dv_xname); 491 return; 492 } 493 } 494 } else { 495 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 496 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 497 aprint_error("%s: can't map codec i/o space\n", 498 sc->sc_dev.dv_xname); 499 return; 500 } 501 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 502 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 503 aprint_error("%s: can't map device i/o space\n", 504 sc->sc_dev.dv_xname); 505 return; 506 } 507 } 508 sc->dmat = pa->pa_dmat; 509 510 /* enable bus mastering */ 511 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 512 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 513 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 514 515 /* Map and establish the interrupt. */ 516 if (pci_intr_map(pa, &ih)) { 517 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 518 return; 519 } 520 intrstr = pci_intr_string(pa->pa_pc, ih); 521 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 522 auich_intr, sc); 523 if (sc->sc_ih == NULL) { 524 aprint_error("%s: can't establish interrupt", 525 sc->sc_dev.dv_xname); 526 if (intrstr != NULL) 527 aprint_normal(" at %s", intrstr); 528 aprint_normal("\n"); 529 return; 530 } 531 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 532 533 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 534 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 535 "0x%02x", PCI_REVISION(pa->pa_class)); 536 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 537 538 /* SiS 7012 needs special handling */ 539 if (d->id == PCIID_SIS7012) { 540 sc->sc_sts_reg = ICH_PICB; 541 sc->sc_sample_shift = 0; 542 /* Un-mute output. From Linux. */ 543 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 544 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 545 ICH_SIS_CTL_UNMUTE); 546 } else { 547 sc->sc_sts_reg = ICH_STS; 548 sc->sc_sample_shift = 1; 549 } 550 551 /* Workaround for a 440MX B-stepping erratum */ 552 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 553 if (d->id == PCIID_440MX) { 554 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 555 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 556 } 557 558 /* Set up DMA lists. */ 559 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 560 auich_alloc_cdata(sc); 561 562 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 563 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 564 565 /* Modem codecs are always the secondary codec on ICH */ 566 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 567 568 sc->host_if.arg = sc; 569 sc->host_if.attach = auich_attach_codec; 570 sc->host_if.read = auich_read_codec; 571 sc->host_if.write = auich_write_codec; 572 sc->host_if.reset = auich_reset_codec; 573 574 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 575 return; 576 577 /* setup audio_format */ 578 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 579 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 580 if (!AC97_IS_4CH(sc->codec_if)) 581 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 582 if (!AC97_IS_6CH(sc->codec_if)) 583 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 584 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 585 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 586 sc->sc_audio_formats[i].frequency_type = 1; 587 sc->sc_audio_formats[i].frequency[0] = 48000; 588 } 589 } 590 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 591 &sc->sc_encodings)) 592 return; 593 } else { 594 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 595 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 596 &sc->sc_encodings)) 597 return; 598 } 599 600 601 /* Watch for power change */ 602 sc->sc_suspend = PWR_RESUME; 603 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 604 605 config_interrupts(self, auich_finish_attach); 606 607 /* sysctl setup */ 608 if (AC97_IS_FIXED_RATE(sc->codec_if) && 609 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 610 return; 611 612 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 613 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 614 CTL_HW, CTL_EOL); 615 if (err != 0) 616 goto sysctl_err; 617 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 618 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 619 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 620 if (err != 0) 621 goto sysctl_err; 622 node_mib = node->sysctl_num; 623 624 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 625 /* passing the sc address instead of &sc->sc_ac97_clock */ 626 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 627 CTLFLAG_READWRITE, 628 CTLTYPE_INT, "ac97rate", 629 SYSCTL_DESCR("AC'97 codec link rate"), 630 auich_sysctl_verify, 0, sc, 0, 631 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 632 if (err != 0) 633 goto sysctl_err; 634 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 635 } 636 637 return; 638 639 sysctl_err: 640 printf("%s: failed to add sysctl nodes. (%d)\n", 641 sc->sc_dev.dv_xname, err); 642 return; /* failure of sysctl is not fatal. */ 643 } 644 645 static int 646 auich_activate(struct device *self, enum devact act) 647 { 648 struct auich_softc *sc; 649 int ret; 650 651 sc = (struct auich_softc *)self; 652 ret = 0; 653 switch (act) { 654 case DVACT_ACTIVATE: 655 return EOPNOTSUPP; 656 case DVACT_DEACTIVATE: 657 if (sc->sc_audiodev != NULL) 658 ret = config_deactivate(sc->sc_audiodev); 659 return ret; 660 } 661 return EOPNOTSUPP; 662 } 663 664 static int 665 auich_detach(struct device *self, int flags) 666 { 667 struct auich_softc *sc; 668 669 sc = (struct auich_softc *)self; 670 671 /* audio */ 672 if (sc->sc_audiodev != NULL) 673 config_detach(sc->sc_audiodev, flags); 674 675 /* sysctl */ 676 sysctl_teardown(&sc->sc_log); 677 678 /* audio_encoding_set */ 679 auconv_delete_encodings(sc->sc_encodings); 680 681 /* ac97 */ 682 if (sc->codec_if != NULL) 683 sc->codec_if->vtbl->detach(sc->codec_if); 684 685 /* PCI */ 686 if (sc->sc_ih != NULL) 687 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 688 if (sc->mix_size != 0) 689 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 690 if (sc->aud_size != 0) 691 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 692 return 0; 693 } 694 695 static int 696 auich_sysctl_verify(SYSCTLFN_ARGS) 697 { 698 int error, tmp; 699 struct sysctlnode node; 700 struct auich_softc *sc; 701 702 node = *rnode; 703 sc = rnode->sysctl_data; 704 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 705 tmp = sc->sc_ac97_clock; 706 node.sysctl_data = &tmp; 707 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 708 if (error || newp == NULL) 709 return error; 710 711 if (tmp < 48000 || tmp > 96000) 712 return EINVAL; 713 sc->sc_ac97_clock = tmp; 714 } 715 716 return 0; 717 } 718 719 static void 720 auich_finish_attach(struct device *self) 721 { 722 struct auich_softc *sc; 723 724 sc = (void *)self; 725 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 726 auich_calibrate(sc); 727 728 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 729 } 730 731 #define ICH_CODECIO_INTERVAL 10 732 static int 733 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 734 { 735 struct auich_softc *sc; 736 int i; 737 uint32_t status; 738 739 sc = v; 740 /* wait for an access semaphore */ 741 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 742 bus_space_read_1(sc->iot, sc->aud_ioh, 743 ICH_CAS + sc->sc_modem_offset) & 1; 744 DELAY(ICH_CODECIO_INTERVAL)); 745 746 if (i > 0) { 747 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 748 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 749 DPRINTF(ICH_DEBUG_CODECIO, 750 ("auich_read_codec(%x, %x)\n", reg, *val)); 751 status = bus_space_read_4(sc->iot, sc->aud_ioh, 752 ICH_GSTS + sc->sc_modem_offset); 753 if (status & ICH_RCS) { 754 bus_space_write_4(sc->iot, sc->aud_ioh, 755 ICH_GSTS + sc->sc_modem_offset, 756 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 757 *val = 0xffff; 758 DPRINTF(ICH_DEBUG_CODECIO, 759 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 760 if (reg == AC97_REG_GPIO_STATUS) 761 auich_clear_cas(sc); 762 return -1; 763 } 764 if (reg == AC97_REG_GPIO_STATUS) 765 auich_clear_cas(sc); 766 return 0; 767 } else { 768 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 769 if (reg == AC97_REG_GPIO_STATUS) 770 auich_clear_cas(sc); 771 return -1; 772 } 773 } 774 775 static int 776 auich_write_codec(void *v, uint8_t reg, uint16_t val) 777 { 778 struct auich_softc *sc; 779 int i; 780 781 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 782 sc = v; 783 /* wait for an access semaphore */ 784 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 785 bus_space_read_1(sc->iot, sc->aud_ioh, 786 ICH_CAS + sc->sc_modem_offset) & 1; 787 DELAY(ICH_CODECIO_INTERVAL)); 788 789 if (i > 0) { 790 bus_space_write_2(sc->iot, sc->mix_ioh, 791 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 792 return 0; 793 } else { 794 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 795 return -1; 796 } 797 } 798 799 static int 800 auich_attach_codec(void *v, struct ac97_codec_if *cif) 801 { 802 struct auich_softc *sc; 803 804 sc = v; 805 sc->codec_if = cif; 806 807 return 0; 808 } 809 810 static int 811 auich_reset_codec(void *v) 812 { 813 struct auich_softc *sc; 814 int i; 815 uint32_t control, status; 816 817 sc = v; 818 control = bus_space_read_4(sc->iot, sc->aud_ioh, 819 ICH_GCTRL + sc->sc_modem_offset); 820 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 821 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 822 } else { 823 control &= ~ICH_ACLSO; 824 control |= ICH_GIE; 825 } 826 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 827 bus_space_write_4(sc->iot, sc->aud_ioh, 828 ICH_GCTRL + sc->sc_modem_offset, control); 829 830 for (i = 500000; i >= 0; i--) { 831 status = bus_space_read_4(sc->iot, sc->aud_ioh, 832 ICH_GSTS + sc->sc_modem_offset); 833 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 834 break; 835 DELAY(1); 836 } 837 if (i <= 0) { 838 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 839 return ETIMEDOUT; 840 } 841 #ifdef DEBUG 842 if (status & ICH_SCR) 843 printf("%s: The 2nd codec is ready.\n", 844 sc->sc_dev.dv_xname); 845 if (status & ICH_S2CR) 846 printf("%s: The 3rd codec is ready.\n", 847 sc->sc_dev.dv_xname); 848 #endif 849 return 0; 850 } 851 852 static int 853 auich_query_encoding(void *v, struct audio_encoding *aep) 854 { 855 struct auich_softc *sc; 856 857 sc = (struct auich_softc *)v; 858 return auconv_query_encoding(sc->sc_encodings, aep); 859 } 860 861 static int 862 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 863 { 864 int ret; 865 u_int ratetmp; 866 867 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 868 ratetmp = srate; 869 if (mode == AUMODE_RECORD) 870 return sc->codec_if->vtbl->set_rate(sc->codec_if, 871 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 872 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 873 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 874 if (ret) 875 return ret; 876 ratetmp = srate; 877 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 878 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 879 if (ret) 880 return ret; 881 ratetmp = srate; 882 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 883 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 884 return ret; 885 } 886 887 static int 888 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 889 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 890 { 891 struct auich_softc *sc; 892 audio_params_t *p; 893 stream_filter_list_t *fil; 894 int mode, index; 895 uint32_t control; 896 897 sc = v; 898 for (mode = AUMODE_RECORD; mode != -1; 899 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 900 if ((setmode & mode) == 0) 901 continue; 902 903 p = mode == AUMODE_PLAY ? play : rec; 904 fil = mode == AUMODE_PLAY ? pfil : rfil; 905 if (p == NULL) 906 continue; 907 908 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 909 if (p->sample_rate < 8000 || 910 p->sample_rate > 48000) 911 return EINVAL; 912 913 index = auconv_set_converter(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 914 mode, p, TRUE, fil); 915 } else { 916 if (p->sample_rate != 8000 && p->sample_rate != 16000) 917 return EINVAL; 918 index = auconv_set_converter(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 919 mode, p, TRUE, fil); 920 } 921 if (index < 0) 922 return EINVAL; 923 if (fil->req_size > 0) 924 p = &fil->filters[0].param; 925 /* p represents HW encoding */ 926 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 927 if (sc->sc_audio_formats[index].frequency_type != 1 928 && auich_set_rate(sc, mode, p->sample_rate)) 929 return EINVAL; 930 } else { 931 if (sc->sc_modem_formats[index].frequency_type != 1 932 && auich_set_rate(sc, mode, p->sample_rate)) 933 return EINVAL; 934 auich_write_codec(sc, AC97_REG_LINE1_RATE, 935 p->sample_rate); 936 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 937 } 938 if (mode == AUMODE_PLAY && 939 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 940 control = bus_space_read_4(sc->iot, sc->aud_ioh, 941 ICH_GCTRL + sc->sc_modem_offset); 942 control &= ~ICH_PCM246_MASK; 943 if (p->channels == 4) { 944 control |= ICH_PCM4; 945 } else if (p->channels == 6) { 946 control |= ICH_PCM6; 947 } 948 bus_space_write_4(sc->iot, sc->aud_ioh, 949 ICH_GCTRL + sc->sc_modem_offset, control); 950 } 951 } 952 953 return 0; 954 } 955 956 static int 957 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 958 { 959 960 return blk & ~0x3f; /* keep good alignment */ 961 } 962 963 static void 964 auich_halt_pipe(struct auich_softc *sc, int pipe) 965 { 966 int i; 967 uint32_t status; 968 969 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 970 for (i = 0; i < 100; i++) { 971 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 972 if (status & ICH_DCH) 973 break; 974 DELAY(1); 975 } 976 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 977 978 #if 1 979 if (i > 0) 980 printf("auich_halt_pipe: halt took %d cycles\n", i); 981 #endif 982 } 983 984 static int 985 auich_halt_output(void *v) 986 { 987 struct auich_softc *sc; 988 989 sc = v; 990 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 991 992 auich_halt_pipe(sc, ICH_PCMO); 993 sc->pcmo.intr = NULL; 994 995 return 0; 996 } 997 998 static int 999 auich_halt_input(void *v) 1000 { 1001 struct auich_softc *sc; 1002 1003 sc = v; 1004 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1005 1006 auich_halt_pipe(sc, ICH_PCMI); 1007 sc->pcmi.intr = NULL; 1008 1009 return 0; 1010 } 1011 1012 static int 1013 auich_getdev(void *v, struct audio_device *adp) 1014 { 1015 struct auich_softc *sc; 1016 1017 sc = v; 1018 *adp = sc->sc_audev; 1019 return 0; 1020 } 1021 1022 static int 1023 auich_set_port(void *v, mixer_ctrl_t *cp) 1024 { 1025 struct auich_softc *sc; 1026 1027 sc = v; 1028 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1029 } 1030 1031 static int 1032 auich_get_port(void *v, mixer_ctrl_t *cp) 1033 { 1034 struct auich_softc *sc; 1035 1036 sc = v; 1037 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1038 } 1039 1040 static int 1041 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1042 { 1043 struct auich_softc *sc; 1044 1045 sc = v; 1046 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1047 } 1048 1049 static void * 1050 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 1051 int flags) 1052 { 1053 struct auich_softc *sc; 1054 struct auich_dma *p; 1055 int error; 1056 1057 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1058 return NULL; 1059 1060 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1061 if (p == NULL) 1062 return NULL; 1063 1064 sc = v; 1065 error = auich_allocmem(sc, size, 0, p); 1066 if (error) { 1067 free(p, pool); 1068 return NULL; 1069 } 1070 1071 p->next = sc->sc_dmas; 1072 sc->sc_dmas = p; 1073 1074 return KERNADDR(p); 1075 } 1076 1077 static void 1078 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1079 { 1080 struct auich_softc *sc; 1081 struct auich_dma *p, **pp; 1082 1083 sc = v; 1084 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1085 if (KERNADDR(p) == ptr) { 1086 auich_freemem(sc, p); 1087 *pp = p->next; 1088 free(p, pool); 1089 return; 1090 } 1091 } 1092 } 1093 1094 static size_t 1095 auich_round_buffersize(void *v, int direction, size_t size) 1096 { 1097 1098 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1099 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1100 1101 return size; 1102 } 1103 1104 static paddr_t 1105 auich_mappage(void *v, void *mem, off_t off, int prot) 1106 { 1107 struct auich_softc *sc; 1108 struct auich_dma *p; 1109 1110 if (off < 0) 1111 return -1; 1112 sc = v; 1113 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1114 continue; 1115 if (!p) 1116 return -1; 1117 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1118 off, prot, BUS_DMA_WAITOK); 1119 } 1120 1121 static int 1122 auich_get_props(void *v) 1123 { 1124 struct auich_softc *sc; 1125 int props; 1126 1127 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1128 sc = v; 1129 /* 1130 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1131 * rate because of aurateconv. Applications can't know what rate the 1132 * device can process in the case of mmap(). 1133 */ 1134 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1135 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1136 props |= AUDIO_PROP_MMAP; 1137 return props; 1138 } 1139 1140 static int 1141 auich_intr(void *v) 1142 { 1143 struct auich_softc *sc; 1144 int ret, gsts; 1145 #ifdef DIAGNOSTIC 1146 int csts; 1147 #endif 1148 1149 sc = v; 1150 ret = 0; 1151 #ifdef DIAGNOSTIC 1152 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1153 if (csts & PCI_STATUS_MASTER_ABORT) { 1154 printf("auich_intr: PCI master abort\n"); 1155 } 1156 #endif 1157 1158 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1159 ICH_GSTS + sc->sc_modem_offset); 1160 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1161 1162 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1163 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1164 int sts; 1165 1166 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1167 ICH_PCMO + sc->sc_sts_reg); 1168 DPRINTF(ICH_DEBUG_INTR, 1169 ("auich_intr: osts=0x%x\n", sts)); 1170 1171 if (sts & ICH_FIFOE) 1172 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1173 1174 if (sts & ICH_BCIS) 1175 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1176 1177 /* int ack */ 1178 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1179 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1180 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1181 bus_space_write_4(sc->iot, sc->aud_ioh, 1182 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1183 else 1184 bus_space_write_4(sc->iot, sc->aud_ioh, 1185 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1186 ret++; 1187 } 1188 1189 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1190 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1191 int sts; 1192 1193 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1194 ICH_PCMI + sc->sc_sts_reg); 1195 DPRINTF(ICH_DEBUG_INTR, 1196 ("auich_intr: ists=0x%x\n", sts)); 1197 1198 if (sts & ICH_FIFOE) 1199 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1200 1201 if (sts & ICH_BCIS) 1202 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1203 1204 /* int ack */ 1205 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1206 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1207 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1208 bus_space_write_4(sc->iot, sc->aud_ioh, 1209 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1210 else 1211 bus_space_write_4(sc->iot, sc->aud_ioh, 1212 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1213 ret++; 1214 } 1215 1216 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1217 int sts; 1218 1219 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1220 ICH_MICI + sc->sc_sts_reg); 1221 DPRINTF(ICH_DEBUG_INTR, 1222 ("auich_intr: ists=0x%x\n", sts)); 1223 1224 if (sts & ICH_FIFOE) 1225 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1226 1227 if (sts & ICH_BCIS) 1228 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1229 1230 /* int ack */ 1231 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1232 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1233 bus_space_write_4(sc->iot, sc->aud_ioh, 1234 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1235 ret++; 1236 } 1237 1238 #ifdef AUICH_MODEM_DEBUG 1239 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1240 printf("%s: gsts=0x%x\n", sc->sc_dev.dv_xname, gsts); 1241 /* int ack */ 1242 bus_space_write_4(sc->iot, sc->aud_ioh, 1243 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1244 ret++; 1245 } 1246 #endif 1247 1248 return ret; 1249 } 1250 1251 static void 1252 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1253 { 1254 int blksize, qptr; 1255 struct auich_dmalist *q; 1256 1257 blksize = ring->blksize; 1258 1259 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1260 q = &ring->dmalist[qptr]; 1261 q->base = ring->p; 1262 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1263 1264 ring->p += blksize; 1265 if (ring->p >= ring->end) 1266 ring->p = ring->start; 1267 } 1268 ring->qptr = 0; 1269 1270 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1271 (qptr - 1) & ICH_LVI_MASK); 1272 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1273 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1274 } 1275 1276 static void 1277 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1278 { 1279 int blksize, qptr, nqptr; 1280 struct auich_dmalist *q; 1281 1282 blksize = ring->blksize; 1283 qptr = ring->qptr; 1284 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1285 1286 while (qptr != nqptr) { 1287 q = &ring->dmalist[qptr]; 1288 q->base = ring->p; 1289 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1290 1291 DPRINTF(ICH_DEBUG_INTR, 1292 ("auich_intr: %p, %p = %x @ 0x%x\n", 1293 &ring->dmalist[qptr], q, q->len, q->base)); 1294 1295 ring->p += blksize; 1296 if (ring->p >= ring->end) 1297 ring->p = ring->start; 1298 1299 qptr = (qptr + 1) & ICH_LVI_MASK; 1300 if (ring->intr) 1301 ring->intr(ring->arg); 1302 } 1303 ring->qptr = qptr; 1304 1305 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1306 (qptr - 1) & ICH_LVI_MASK); 1307 } 1308 1309 static int 1310 auich_trigger_output(void *v, void *start, void *end, int blksize, 1311 void (*intr)(void *), void *arg, const audio_params_t *param) 1312 { 1313 struct auich_softc *sc; 1314 struct auich_dma *p; 1315 size_t size; 1316 1317 DPRINTF(ICH_DEBUG_DMA, 1318 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1319 start, end, blksize, intr, arg, param)); 1320 sc = v; 1321 1322 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1323 continue; 1324 if (!p) { 1325 printf("auich_trigger_output: bad addr %p\n", start); 1326 return EINVAL; 1327 } 1328 1329 size = (size_t)((caddr_t)end - (caddr_t)start); 1330 1331 sc->pcmo.intr = intr; 1332 sc->pcmo.arg = arg; 1333 sc->pcmo.start = DMAADDR(p); 1334 sc->pcmo.p = sc->pcmo.start; 1335 sc->pcmo.end = sc->pcmo.start + size; 1336 sc->pcmo.blksize = blksize; 1337 1338 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1339 sc->sc_cddma + ICH_PCMO_OFF(0)); 1340 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1341 1342 return 0; 1343 } 1344 1345 static int 1346 auich_trigger_input(void *v, void *start, void *end, int blksize, 1347 void (*intr)(void *), void *arg, const audio_params_t *param) 1348 { 1349 struct auich_softc *sc; 1350 struct auich_dma *p; 1351 size_t size; 1352 1353 DPRINTF(ICH_DEBUG_DMA, 1354 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1355 start, end, blksize, intr, arg, param)); 1356 sc = v; 1357 1358 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1359 continue; 1360 if (!p) { 1361 printf("auich_trigger_input: bad addr %p\n", start); 1362 return EINVAL; 1363 } 1364 1365 size = (size_t)((caddr_t)end - (caddr_t)start); 1366 1367 sc->pcmi.intr = intr; 1368 sc->pcmi.arg = arg; 1369 sc->pcmi.start = DMAADDR(p); 1370 sc->pcmi.p = sc->pcmi.start; 1371 sc->pcmi.end = sc->pcmi.start + size; 1372 sc->pcmi.blksize = blksize; 1373 1374 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1375 sc->sc_cddma + ICH_PCMI_OFF(0)); 1376 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1377 1378 return 0; 1379 } 1380 1381 static int 1382 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1383 struct auich_dma *p) 1384 { 1385 int error; 1386 1387 p->size = size; 1388 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1389 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1390 &p->nsegs, BUS_DMA_NOWAIT); 1391 if (error) 1392 return error; 1393 1394 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1395 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1396 if (error) 1397 goto free; 1398 1399 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1400 0, BUS_DMA_NOWAIT, &p->map); 1401 if (error) 1402 goto unmap; 1403 1404 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1405 BUS_DMA_NOWAIT); 1406 if (error) 1407 goto destroy; 1408 return 0; 1409 1410 destroy: 1411 bus_dmamap_destroy(sc->dmat, p->map); 1412 unmap: 1413 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1414 free: 1415 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1416 return error; 1417 } 1418 1419 static int 1420 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1421 { 1422 1423 bus_dmamap_unload(sc->dmat, p->map); 1424 bus_dmamap_destroy(sc->dmat, p->map); 1425 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1426 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1427 return 0; 1428 } 1429 1430 static int 1431 auich_alloc_cdata(struct auich_softc *sc) 1432 { 1433 bus_dma_segment_t seg; 1434 int error, rseg; 1435 1436 /* 1437 * Allocate the control data structure, and create and load the 1438 * DMA map for it. 1439 */ 1440 if ((error = bus_dmamem_alloc(sc->dmat, 1441 sizeof(struct auich_cdata), 1442 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1443 printf("%s: unable to allocate control data, error = %d\n", 1444 sc->sc_dev.dv_xname, error); 1445 goto fail_0; 1446 } 1447 1448 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1449 sizeof(struct auich_cdata), 1450 (caddr_t *) &sc->sc_cdata, 1451 sc->sc_dmamap_flags)) != 0) { 1452 printf("%s: unable to map control data, error = %d\n", 1453 sc->sc_dev.dv_xname, error); 1454 goto fail_1; 1455 } 1456 1457 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1458 sizeof(struct auich_cdata), 0, 0, 1459 &sc->sc_cddmamap)) != 0) { 1460 printf("%s: unable to create control data DMA map, " 1461 "error = %d\n", sc->sc_dev.dv_xname, error); 1462 goto fail_2; 1463 } 1464 1465 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1466 sc->sc_cdata, sizeof(struct auich_cdata), 1467 NULL, 0)) != 0) { 1468 printf("%s: unable tp load control data DMA map, " 1469 "error = %d\n", sc->sc_dev.dv_xname, error); 1470 goto fail_3; 1471 } 1472 1473 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1474 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1475 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1476 1477 return 0; 1478 1479 fail_3: 1480 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1481 fail_2: 1482 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1483 sizeof(struct auich_cdata)); 1484 fail_1: 1485 bus_dmamem_free(sc->dmat, &seg, rseg); 1486 fail_0: 1487 return error; 1488 } 1489 1490 static void 1491 auich_powerhook(int why, void *addr) 1492 { 1493 struct auich_softc *sc; 1494 1495 sc = (struct auich_softc *)addr; 1496 switch (why) { 1497 case PWR_SUSPEND: 1498 case PWR_STANDBY: 1499 /* Power down */ 1500 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1501 sc->sc_suspend = why; 1502 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1503 break; 1504 1505 case PWR_RESUME: 1506 /* Wake up */ 1507 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1508 if (sc->sc_suspend == PWR_RESUME) { 1509 printf("%s: resume without suspend.\n", 1510 sc->sc_dev.dv_xname); 1511 sc->sc_suspend = why; 1512 return; 1513 } 1514 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1515 sc->sc_suspend = why; 1516 auich_reset_codec(sc); 1517 DELAY(1000); 1518 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1519 break; 1520 1521 case PWR_SOFTSUSPEND: 1522 case PWR_SOFTSTANDBY: 1523 case PWR_SOFTRESUME: 1524 break; 1525 } 1526 } 1527 1528 /* 1529 * Calibrate card (some boards are overclocked and need scaling) 1530 */ 1531 static void 1532 auich_calibrate(struct auich_softc *sc) 1533 { 1534 struct timeval t1, t2; 1535 uint8_t ociv, nciv; 1536 uint64_t wait_us; 1537 uint32_t actual_48k_rate, bytes, ac97rate; 1538 void *temp_buffer; 1539 struct auich_dma *p; 1540 u_int rate; 1541 1542 /* 1543 * Grab audio from input for fixed interval and compare how 1544 * much we actually get with what we expect. Interval needs 1545 * to be sufficiently short that no interrupts are 1546 * generated. 1547 */ 1548 1549 /* Force the codec to a known state first. */ 1550 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1551 rate = sc->sc_ac97_clock = 48000; 1552 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1553 &rate); 1554 1555 /* Setup a buffer */ 1556 bytes = 64000; 1557 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1558 1559 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1560 continue; 1561 if (p == NULL) { 1562 printf("auich_calibrate: bad address %p\n", temp_buffer); 1563 return; 1564 } 1565 sc->pcmi.dmalist[0].base = DMAADDR(p); 1566 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1567 1568 /* 1569 * our data format is stereo, 16 bit so each sample is 4 bytes. 1570 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1571 * we're going to start recording with interrupts disabled and measure 1572 * the time taken for one block to complete. we know the block size, 1573 * we know the time in microseconds, we calculate the sample rate: 1574 * 1575 * actual_rate [bps] = bytes / (time [s] * 4) 1576 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1577 * actual_rate [Hz] = (bytes * 250000) / time [us] 1578 */ 1579 1580 /* prepare */ 1581 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1582 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1583 sc->sc_cddma + ICH_PCMI_OFF(0)); 1584 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1585 (0 - 1) & ICH_LVI_MASK); 1586 1587 /* start */ 1588 microtime(&t1); 1589 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1590 1591 /* wait */ 1592 nciv = ociv; 1593 do { 1594 microtime(&t2); 1595 if (t2.tv_sec - t1.tv_sec > 1) 1596 break; 1597 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1598 ICH_PCMI + ICH_CIV); 1599 } while (nciv == ociv); 1600 microtime(&t2); 1601 1602 /* stop */ 1603 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1604 1605 /* reset */ 1606 DELAY(100); 1607 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1608 1609 /* turn time delta into us */ 1610 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1611 1612 auich_freem(sc, temp_buffer, M_DEVBUF); 1613 1614 if (nciv == ociv) { 1615 printf("%s: ac97 link rate calibration timed out after %" 1616 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1617 return; 1618 } 1619 1620 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1621 1622 if (actual_48k_rate < 50000) 1623 ac97rate = 48000; 1624 else 1625 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1626 1627 printf("%s: measured ac97 link rate at %d Hz", 1628 sc->sc_dev.dv_xname, actual_48k_rate); 1629 if (ac97rate != actual_48k_rate) 1630 printf(", will use %d Hz", ac97rate); 1631 printf("\n"); 1632 1633 sc->sc_ac97_clock = ac97rate; 1634 } 1635 1636 static void 1637 auich_clear_cas(struct auich_softc *sc) 1638 { 1639 /* Clear the codec access semaphore */ 1640 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1641 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1642 1643 return; 1644 } 1645
Indexes created Wed Oct 22 13:09:56 GMT 2025