auich.c revision 1.85.4.2
1 /* $NetBSD: auich.c,v 1.85.4.2 2005/03/19 08:35:10 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.85.4.2 2005/03/19 08:35:10 yamt Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 187 struct ac97_codec_if *codec_if; 188 struct ac97_host_if host_if; 189 190 /* DMA scatter-gather lists. */ 191 bus_dmamap_t sc_cddmamap; 192 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 193 194 struct auich_cdata *sc_cdata; 195 196 struct auich_ring { 197 int qptr; 198 struct auich_dmalist *dmalist; 199 200 uint32_t start, p, end; 201 int blksize; 202 203 void (*intr)(void *); 204 void *arg; 205 } pcmo, pcmi, mici; 206 207 struct auich_dma *sc_dmas; 208 209 /* SiS 7012 hack */ 210 int sc_sample_shift; 211 int sc_sts_reg; 212 /* 440MX workaround */ 213 int sc_dmamap_flags; 214 215 /* Power Management */ 216 void *sc_powerhook; 217 int sc_suspend; 218 struct pci_conf_state sc_pciconf; 219 220 /* sysctl */ 221 struct sysctllog *sc_log; 222 uint32_t sc_ac97_clock; 223 int sc_ac97_clock_mib; 224 225 #define AUICH_NFORMATS 3 226 struct audio_format sc_formats[AUICH_NFORMATS]; 227 struct audio_encoding_set *sc_encodings; 228 }; 229 230 /* Debug */ 231 #ifdef AUICH_DEBUG 232 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 233 int auich_debug = 0xfffe; 234 #define ICH_DEBUG_CODECIO 0x0001 235 #define ICH_DEBUG_DMA 0x0002 236 #define ICH_DEBUG_INTR 0x0004 237 #else 238 #define DPRINTF(x,y) /* nothing */ 239 #endif 240 241 static int auich_match(struct device *, struct cfdata *, void *); 242 static void auich_attach(struct device *, struct device *, void *); 243 static int auich_detach(struct device *, int); 244 static int auich_activate(struct device *, enum devact); 245 static int auich_intr(void *); 246 247 CFATTACH_DECL(auich, sizeof(struct auich_softc), 248 auich_match, auich_attach, auich_detach, auich_activate); 249 250 static int auich_query_encoding(void *, struct audio_encoding *); 251 static int auich_set_params(void *, int, int, audio_params_t *, 252 audio_params_t *, stream_filter_list_t *, 253 stream_filter_list_t *); 254 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 255 static void auich_halt_pipe(struct auich_softc *, int); 256 static int auich_halt_output(void *); 257 static int auich_halt_input(void *); 258 static int auich_getdev(void *, struct audio_device *); 259 static int auich_set_port(void *, mixer_ctrl_t *); 260 static int auich_get_port(void *, mixer_ctrl_t *); 261 static int auich_query_devinfo(void *, mixer_devinfo_t *); 262 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 263 static void auich_freem(void *, void *, struct malloc_type *); 264 static size_t auich_round_buffersize(void *, int, size_t); 265 static paddr_t auich_mappage(void *, void *, off_t, int); 266 static int auich_get_props(void *); 267 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 268 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 269 static int auich_trigger_output(void *, void *, void *, int, 270 void (*)(void *), void *, const audio_params_t *); 271 static int auich_trigger_input(void *, void *, void *, int, 272 void (*)(void *), void *, const audio_params_t *); 273 274 static int auich_alloc_cdata(struct auich_softc *); 275 276 static int auich_allocmem(struct auich_softc *, size_t, size_t, 277 struct auich_dma *); 278 static int auich_freemem(struct auich_softc *, struct auich_dma *); 279 280 static void auich_powerhook(int, void *); 281 static int auich_set_rate(struct auich_softc *, int, u_long); 282 static int auich_sysctl_verify(SYSCTLFN_ARGS); 283 static void auich_finish_attach(struct device *); 284 static void auich_calibrate(struct auich_softc *); 285 286 static int auich_attach_codec(void *, struct ac97_codec_if *); 287 static int auich_read_codec(void *, uint8_t, uint16_t *); 288 static int auich_write_codec(void *, uint8_t, uint16_t); 289 static int auich_reset_codec(void *); 290 291 const struct audio_hw_if auich_hw_if = { 292 NULL, /* open */ 293 NULL, /* close */ 294 NULL, /* drain */ 295 auich_query_encoding, 296 auich_set_params, 297 auich_round_blocksize, 298 NULL, /* commit_setting */ 299 NULL, /* init_output */ 300 NULL, /* init_input */ 301 NULL, /* start_output */ 302 NULL, /* start_input */ 303 auich_halt_output, 304 auich_halt_input, 305 NULL, /* speaker_ctl */ 306 auich_getdev, 307 NULL, /* getfd */ 308 auich_set_port, 309 auich_get_port, 310 auich_query_devinfo, 311 auich_allocm, 312 auich_freem, 313 auich_round_buffersize, 314 auich_mappage, 315 auich_get_props, 316 auich_trigger_output, 317 auich_trigger_input, 318 NULL, /* dev_ioctl */ 319 }; 320 321 #define AUICH_FORMATS_4CH 1 322 #define AUICH_FORMATS_6CH 2 323 static const struct audio_format auich_formats[AUICH_NFORMATS] = { 324 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 325 2, AUFMT_STEREO, 0, {8000, 48000}}, 326 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 327 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 328 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 329 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 330 }; 331 332 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 333 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 334 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 335 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 336 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 337 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 338 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 339 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 340 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 341 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 342 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 343 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 344 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 345 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 346 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 347 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 348 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 349 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 350 351 static const struct auich_devtype { 352 pcireg_t id; 353 const char *name; 354 const char *shortname; /* must be less than 11 characters */ 355 } auich_devices[] = { 356 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 357 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 358 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 359 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 360 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 361 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 362 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 363 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 364 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 365 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 366 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 367 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 368 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 369 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 370 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 371 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 372 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 373 { 0, NULL, NULL }, 374 }; 375 376 static const struct auich_devtype * 377 auich_lookup(struct pci_attach_args *pa) 378 { 379 const struct auich_devtype *d; 380 381 for (d = auich_devices; d->name != NULL; d++) { 382 if (pa->pa_id == d->id) 383 return d; 384 } 385 386 return NULL; 387 } 388 389 static int 390 auich_match(struct device *parent, struct cfdata *match, void *aux) 391 { 392 struct pci_attach_args *pa; 393 394 pa = aux; 395 if (auich_lookup(pa) != NULL) 396 return 1; 397 398 return 0; 399 } 400 401 static void 402 auich_attach(struct device *parent, struct device *self, void *aux) 403 { 404 struct auich_softc *sc; 405 struct pci_attach_args *pa; 406 pci_intr_handle_t ih; 407 pcireg_t v; 408 const char *intrstr; 409 const struct auich_devtype *d; 410 struct sysctlnode *node; 411 int err, node_mib, i; 412 413 sc = (struct auich_softc *)self; 414 pa = aux; 415 aprint_naive(": Audio controller\n"); 416 417 d = auich_lookup(pa); 418 if (d == NULL) 419 panic("auich_attach: impossible"); 420 421 sc->sc_pc = pa->pa_pc; 422 sc->sc_pt = pa->pa_tag; 423 424 aprint_normal(": %s\n", d->name); 425 426 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6) { 427 /* 428 * Use native mode for ICH4/ICH5/ICH6 429 */ 430 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 431 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 432 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 433 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 434 v | ICH_CFG_IOSE); 435 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 436 0, &sc->iot, &sc->mix_ioh, NULL, 437 &sc->mix_size)) { 438 aprint_error("%s: can't map codec i/o space\n", 439 sc->sc_dev.dv_xname); 440 return; 441 } 442 } 443 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 444 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 445 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 446 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 447 v | ICH_CFG_IOSE); 448 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 449 0, &sc->iot, &sc->aud_ioh, NULL, 450 &sc->aud_size)) { 451 aprint_error("%s: can't map device i/o space\n", 452 sc->sc_dev.dv_xname); 453 return; 454 } 455 } 456 } else { 457 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 458 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 459 aprint_error("%s: can't map codec i/o space\n", 460 sc->sc_dev.dv_xname); 461 return; 462 } 463 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 464 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 465 aprint_error("%s: can't map device i/o space\n", 466 sc->sc_dev.dv_xname); 467 return; 468 } 469 } 470 sc->dmat = pa->pa_dmat; 471 472 /* enable bus mastering */ 473 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 474 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 475 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 476 477 /* Map and establish the interrupt. */ 478 if (pci_intr_map(pa, &ih)) { 479 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 480 return; 481 } 482 intrstr = pci_intr_string(pa->pa_pc, ih); 483 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 484 auich_intr, sc); 485 if (sc->sc_ih == NULL) { 486 aprint_error("%s: can't establish interrupt", 487 sc->sc_dev.dv_xname); 488 if (intrstr != NULL) 489 aprint_normal(" at %s", intrstr); 490 aprint_normal("\n"); 491 return; 492 } 493 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 494 495 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 496 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 497 "0x%02x", PCI_REVISION(pa->pa_class)); 498 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 499 500 /* SiS 7012 needs special handling */ 501 if (d->id == PCIID_SIS7012) { 502 sc->sc_sts_reg = ICH_PICB; 503 sc->sc_sample_shift = 0; 504 /* Un-mute output. From Linux. */ 505 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 506 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 507 ICH_SIS_CTL_UNMUTE); 508 } else { 509 sc->sc_sts_reg = ICH_STS; 510 sc->sc_sample_shift = 1; 511 } 512 513 /* Workaround for a 440MX B-stepping erratum */ 514 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 515 if (d->id == PCIID_440MX) { 516 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 517 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 518 } 519 520 /* Set up DMA lists. */ 521 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 522 auich_alloc_cdata(sc); 523 524 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 525 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 526 527 sc->host_if.arg = sc; 528 sc->host_if.attach = auich_attach_codec; 529 sc->host_if.read = auich_read_codec; 530 sc->host_if.write = auich_write_codec; 531 sc->host_if.reset = auich_reset_codec; 532 533 if (ac97_attach(&sc->host_if, self) != 0) 534 return; 535 536 /* setup audio_format */ 537 memcpy(sc->sc_formats, auich_formats, sizeof(auich_formats)); 538 if (!AC97_IS_4CH(sc->codec_if)) 539 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_4CH]); 540 if (!AC97_IS_6CH(sc->codec_if)) 541 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_6CH]); 542 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 543 for (i = 0; i < AUICH_NFORMATS; i++) { 544 sc->sc_formats[i].frequency_type = 1; 545 sc->sc_formats[i].frequency[0] = 48000; 546 } 547 } 548 549 if (0 != auconv_create_encodings(sc->sc_formats, AUICH_NFORMATS, 550 &sc->sc_encodings)) { 551 return; 552 } 553 554 /* Watch for power change */ 555 sc->sc_suspend = PWR_RESUME; 556 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 557 558 config_interrupts(self, auich_finish_attach); 559 560 /* sysctl setup */ 561 if (AC97_IS_FIXED_RATE(sc->codec_if)) 562 return; 563 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 564 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 565 CTL_HW, CTL_EOL); 566 if (err != 0) 567 goto sysctl_err; 568 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 569 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 570 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 571 if (err != 0) 572 goto sysctl_err; 573 node_mib = node->sysctl_num; 574 /* passing the sc address instead of &sc->sc_ac97_clock */ 575 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 576 CTLTYPE_INT, "ac97rate", 577 SYSCTL_DESCR("AC'97 codec link rate"), 578 auich_sysctl_verify, 0, sc, 0, 579 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 580 if (err != 0) 581 goto sysctl_err; 582 sc->sc_ac97_clock_mib = node->sysctl_num; 583 584 return; 585 586 sysctl_err: 587 printf("%s: failed to add sysctl nodes. (%d)\n", 588 sc->sc_dev.dv_xname, err); 589 return; /* failure of sysctl is not fatal. */ 590 } 591 592 static int 593 auich_activate(struct device *self, enum devact act) 594 { 595 struct auich_softc *sc; 596 int ret; 597 598 sc = (struct auich_softc *)self; 599 ret = 0; 600 switch (act) { 601 case DVACT_ACTIVATE: 602 return EOPNOTSUPP; 603 case DVACT_DEACTIVATE: 604 if (sc->sc_audiodev != NULL) 605 ret = config_deactivate(sc->sc_audiodev); 606 return ret; 607 } 608 return EOPNOTSUPP; 609 } 610 611 static int 612 auich_detach(struct device *self, int flags) 613 { 614 struct auich_softc *sc; 615 616 sc = (struct auich_softc *)self; 617 618 /* audio */ 619 if (sc->sc_audiodev != NULL) 620 config_detach(sc->sc_audiodev, flags); 621 622 /* sysctl */ 623 sysctl_teardown(&sc->sc_log); 624 625 /* audio_encoding_set */ 626 auconv_delete_encodings(sc->sc_encodings); 627 628 /* ac97 */ 629 if (sc->codec_if != NULL) 630 sc->codec_if->vtbl->detach(sc->codec_if); 631 632 /* PCI */ 633 if (sc->sc_ih != NULL) 634 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 635 if (sc->mix_size != 0) 636 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 637 if (sc->aud_size != 0) 638 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 639 return 0; 640 } 641 642 static int 643 auich_sysctl_verify(SYSCTLFN_ARGS) 644 { 645 int error, tmp; 646 struct sysctlnode node; 647 struct auich_softc *sc; 648 649 node = *rnode; 650 sc = rnode->sysctl_data; 651 tmp = sc->sc_ac97_clock; 652 node.sysctl_data = &tmp; 653 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 654 if (error || newp == NULL) 655 return error; 656 657 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 658 if (tmp < 48000 || tmp > 96000) 659 return EINVAL; 660 sc->sc_ac97_clock = tmp; 661 } 662 663 return 0; 664 } 665 666 static void 667 auich_finish_attach(struct device *self) 668 { 669 struct auich_softc *sc; 670 671 sc = (void *)self; 672 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 673 auich_calibrate(sc); 674 675 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 676 } 677 678 #define ICH_CODECIO_INTERVAL 10 679 static int 680 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 681 { 682 struct auich_softc *sc; 683 int i; 684 uint32_t status; 685 686 sc = v; 687 /* wait for an access semaphore */ 688 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 689 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 690 DELAY(ICH_CODECIO_INTERVAL)); 691 692 if (i > 0) { 693 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 694 DPRINTF(ICH_DEBUG_CODECIO, 695 ("auich_read_codec(%x, %x)\n", reg, *val)); 696 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 697 if (status & ICH_RCS) { 698 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 699 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 700 *val = 0xffff; 701 DPRINTF(ICH_DEBUG_CODECIO, 702 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 703 return -1; 704 } 705 return 0; 706 } else { 707 DPRINTF(ICH_DEBUG_CODECIO, 708 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 709 return -1; 710 } 711 } 712 713 static int 714 auich_write_codec(void *v, uint8_t reg, uint16_t val) 715 { 716 struct auich_softc *sc; 717 int i; 718 719 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 720 sc = v; 721 /* wait for an access semaphore */ 722 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 723 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 724 DELAY(ICH_CODECIO_INTERVAL)); 725 726 if (i > 0) { 727 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 728 return 0; 729 } else { 730 DPRINTF(ICH_DEBUG_CODECIO, 731 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 732 return -1; 733 } 734 } 735 736 static int 737 auich_attach_codec(void *v, struct ac97_codec_if *cif) 738 { 739 struct auich_softc *sc; 740 741 sc = v; 742 sc->codec_if = cif; 743 return 0; 744 } 745 746 static int 747 auich_reset_codec(void *v) 748 { 749 struct auich_softc *sc; 750 int i; 751 uint32_t control, status; 752 753 sc = v; 754 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 755 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 756 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 757 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 758 759 for (i = 500000; i >= 0; i--) { 760 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 761 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 762 break; 763 DELAY(1); 764 } 765 if (i <= 0) { 766 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 767 return ETIMEDOUT; 768 } 769 #ifdef DEBUG 770 if (status & ICH_SCR) 771 printf("%s: The 2nd codec is ready.\n", 772 sc->sc_dev.dv_xname); 773 if (status & ICH_S2CR) 774 printf("%s: The 3rd codec is ready.\n", 775 sc->sc_dev.dv_xname); 776 #endif 777 return 0; 778 } 779 780 static int 781 auich_query_encoding(void *v, struct audio_encoding *aep) 782 { 783 struct auich_softc *sc; 784 785 sc = (struct auich_softc *)v; 786 return auconv_query_encoding(sc->sc_encodings, aep); 787 } 788 789 static int 790 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 791 { 792 int ret; 793 u_int ratetmp; 794 795 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 796 ratetmp = srate; 797 if (mode == AUMODE_RECORD) 798 return sc->codec_if->vtbl->set_rate(sc->codec_if, 799 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 800 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 801 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 802 if (ret) 803 return ret; 804 ratetmp = srate; 805 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 806 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 807 if (ret) 808 return ret; 809 ratetmp = srate; 810 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 811 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 812 return ret; 813 } 814 815 static int 816 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 817 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 818 { 819 struct auich_softc *sc; 820 audio_params_t *p; 821 stream_filter_list_t *fil; 822 int mode, index; 823 uint32_t control; 824 825 sc = v; 826 for (mode = AUMODE_RECORD; mode != -1; 827 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 828 if ((setmode & mode) == 0) 829 continue; 830 831 p = mode == AUMODE_PLAY ? play : rec; 832 fil = mode == AUMODE_PLAY ? pfil : rfil; 833 if (p == NULL) 834 continue; 835 836 if (p->sample_rate < 8000 || 837 p->sample_rate > 48000) 838 return EINVAL; 839 840 index = auconv_set_converter(sc->sc_formats, AUICH_NFORMATS, 841 mode, p, TRUE, fil); 842 if (index < 0) 843 return EINVAL; 844 if (fil->req_size > 0) 845 p = &fil->filters[0].param; 846 /* p represents HW encoding */ 847 if (sc->sc_formats[index].frequency_type != 1 848 && auich_set_rate(sc, mode, p->sample_rate)) 849 return EINVAL; 850 if (mode == AUMODE_PLAY) { 851 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 852 control &= ~ICH_PCM246_MASK; 853 if (p->channels == 4) { 854 control |= ICH_PCM4; 855 } else if (p->channels == 6) { 856 control |= ICH_PCM6; 857 } 858 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 859 } 860 } 861 862 return 0; 863 } 864 865 static int 866 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 867 { 868 869 return blk & ~0x3f; /* keep good alignment */ 870 } 871 872 static void 873 auich_halt_pipe(struct auich_softc *sc, int pipe) 874 { 875 int i; 876 uint32_t status; 877 878 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 879 for (i = 0; i < 100; i++) { 880 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 881 if (status & ICH_DCH) 882 break; 883 DELAY(1); 884 } 885 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 886 887 #if 1 888 if (i > 0) 889 printf("auich_halt_pipe: halt took %d cycles\n", i); 890 #endif 891 } 892 893 static int 894 auich_halt_output(void *v) 895 { 896 struct auich_softc *sc; 897 898 sc = v; 899 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 900 901 auich_halt_pipe(sc, ICH_PCMO); 902 sc->pcmo.intr = NULL; 903 904 return 0; 905 } 906 907 static int 908 auich_halt_input(void *v) 909 { 910 struct auich_softc *sc; 911 912 sc = v; 913 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 914 915 auich_halt_pipe(sc, ICH_PCMI); 916 sc->pcmi.intr = NULL; 917 918 return 0; 919 } 920 921 static int 922 auich_getdev(void *v, struct audio_device *adp) 923 { 924 struct auich_softc *sc; 925 926 sc = v; 927 *adp = sc->sc_audev; 928 return 0; 929 } 930 931 static int 932 auich_set_port(void *v, mixer_ctrl_t *cp) 933 { 934 struct auich_softc *sc; 935 936 sc = v; 937 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 938 } 939 940 static int 941 auich_get_port(void *v, mixer_ctrl_t *cp) 942 { 943 struct auich_softc *sc; 944 945 sc = v; 946 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 947 } 948 949 static int 950 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 951 { 952 struct auich_softc *sc; 953 954 sc = v; 955 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 956 } 957 958 static void * 959 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 960 int flags) 961 { 962 struct auich_softc *sc; 963 struct auich_dma *p; 964 int error; 965 966 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 967 return NULL; 968 969 p = malloc(sizeof(*p), pool, flags|M_ZERO); 970 if (p == NULL) 971 return NULL; 972 973 sc = v; 974 error = auich_allocmem(sc, size, 0, p); 975 if (error) { 976 free(p, pool); 977 return NULL; 978 } 979 980 p->next = sc->sc_dmas; 981 sc->sc_dmas = p; 982 983 return KERNADDR(p); 984 } 985 986 static void 987 auich_freem(void *v, void *ptr, struct malloc_type *pool) 988 { 989 struct auich_softc *sc; 990 struct auich_dma *p, **pp; 991 992 sc = v; 993 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 994 if (KERNADDR(p) == ptr) { 995 auich_freemem(sc, p); 996 *pp = p->next; 997 free(p, pool); 998 return; 999 } 1000 } 1001 } 1002 1003 static size_t 1004 auich_round_buffersize(void *v, int direction, size_t size) 1005 { 1006 1007 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1008 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1009 1010 return size; 1011 } 1012 1013 static paddr_t 1014 auich_mappage(void *v, void *mem, off_t off, int prot) 1015 { 1016 struct auich_softc *sc; 1017 struct auich_dma *p; 1018 1019 if (off < 0) 1020 return -1; 1021 sc = v; 1022 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1023 continue; 1024 if (!p) 1025 return -1; 1026 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1027 off, prot, BUS_DMA_WAITOK); 1028 } 1029 1030 static int 1031 auich_get_props(void *v) 1032 { 1033 struct auich_softc *sc; 1034 int props; 1035 1036 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1037 sc = v; 1038 /* 1039 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1040 * rate because of aurateconv. Applications can't know what rate the 1041 * device can process in the case of mmap(). 1042 */ 1043 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 1044 props |= AUDIO_PROP_MMAP; 1045 return props; 1046 } 1047 1048 static int 1049 auich_intr(void *v) 1050 { 1051 struct auich_softc *sc; 1052 int ret, gsts; 1053 #ifdef DIAGNOSTIC 1054 int csts; 1055 #endif 1056 1057 sc = v; 1058 ret = 0; 1059 #ifdef DIAGNOSTIC 1060 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1061 if (csts & PCI_STATUS_MASTER_ABORT) { 1062 printf("auich_intr: PCI master abort\n"); 1063 } 1064 #endif 1065 1066 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 1067 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1068 1069 if (gsts & ICH_POINT) { 1070 int sts; 1071 1072 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1073 ICH_PCMO + sc->sc_sts_reg); 1074 DPRINTF(ICH_DEBUG_INTR, 1075 ("auich_intr: osts=0x%x\n", sts)); 1076 1077 if (sts & ICH_FIFOE) 1078 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1079 1080 if (sts & ICH_BCIS) 1081 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1082 1083 /* int ack */ 1084 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1085 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1086 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1087 ret++; 1088 } 1089 1090 if (gsts & ICH_PIINT) { 1091 int sts; 1092 1093 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1094 ICH_PCMI + sc->sc_sts_reg); 1095 DPRINTF(ICH_DEBUG_INTR, 1096 ("auich_intr: ists=0x%x\n", sts)); 1097 1098 if (sts & ICH_FIFOE) 1099 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1100 1101 if (sts & ICH_BCIS) 1102 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1103 1104 /* int ack */ 1105 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1106 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1107 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1108 ret++; 1109 } 1110 1111 if (gsts & ICH_MINT) { 1112 int sts; 1113 1114 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1115 ICH_MICI + sc->sc_sts_reg); 1116 DPRINTF(ICH_DEBUG_INTR, 1117 ("auich_intr: ists=0x%x\n", sts)); 1118 1119 if (sts & ICH_FIFOE) 1120 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1121 1122 if (sts & ICH_BCIS) 1123 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1124 1125 /* int ack */ 1126 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1127 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1128 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MINT); 1129 ret++; 1130 } 1131 1132 return ret; 1133 } 1134 1135 static void 1136 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1137 { 1138 int blksize, qptr; 1139 struct auich_dmalist *q; 1140 1141 blksize = ring->blksize; 1142 1143 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1144 q = &ring->dmalist[qptr]; 1145 q->base = ring->p; 1146 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1147 1148 ring->p += blksize; 1149 if (ring->p >= ring->end) 1150 ring->p = ring->start; 1151 } 1152 ring->qptr = 0; 1153 1154 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1155 (qptr - 1) & ICH_LVI_MASK); 1156 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1157 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1158 } 1159 1160 static void 1161 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1162 { 1163 int blksize, qptr, nqptr; 1164 struct auich_dmalist *q; 1165 1166 blksize = ring->blksize; 1167 qptr = ring->qptr; 1168 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1169 1170 while (qptr != nqptr) { 1171 q = &ring->dmalist[qptr]; 1172 q->base = ring->p; 1173 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1174 1175 DPRINTF(ICH_DEBUG_INTR, 1176 ("auich_intr: %p, %p = %x @ 0x%x\n", 1177 &ring->dmalist[qptr], q, q->len, q->base)); 1178 1179 ring->p += blksize; 1180 if (ring->p >= ring->end) 1181 ring->p = ring->start; 1182 1183 qptr = (qptr + 1) & ICH_LVI_MASK; 1184 if (ring->intr) 1185 ring->intr(ring->arg); 1186 } 1187 ring->qptr = qptr; 1188 1189 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1190 (qptr - 1) & ICH_LVI_MASK); 1191 } 1192 1193 static int 1194 auich_trigger_output(void *v, void *start, void *end, int blksize, 1195 void (*intr)(void *), void *arg, const audio_params_t *param) 1196 { 1197 struct auich_softc *sc; 1198 struct auich_dma *p; 1199 size_t size; 1200 1201 DPRINTF(ICH_DEBUG_DMA, 1202 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1203 start, end, blksize, intr, arg, param)); 1204 sc = v; 1205 1206 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1207 continue; 1208 if (!p) { 1209 printf("auich_trigger_output: bad addr %p\n", start); 1210 return EINVAL; 1211 } 1212 1213 size = (size_t)((caddr_t)end - (caddr_t)start); 1214 1215 sc->pcmo.intr = intr; 1216 sc->pcmo.arg = arg; 1217 sc->pcmo.start = DMAADDR(p); 1218 sc->pcmo.p = sc->pcmo.start; 1219 sc->pcmo.end = sc->pcmo.start + size; 1220 sc->pcmo.blksize = blksize; 1221 1222 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1223 sc->sc_cddma + ICH_PCMO_OFF(0)); 1224 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1225 1226 return 0; 1227 } 1228 1229 static int 1230 auich_trigger_input(void *v, void *start, void *end, int blksize, 1231 void (*intr)(void *), void *arg, const audio_params_t *param) 1232 { 1233 struct auich_softc *sc; 1234 struct auich_dma *p; 1235 size_t size; 1236 1237 DPRINTF(ICH_DEBUG_DMA, 1238 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1239 start, end, blksize, intr, arg, param)); 1240 sc = v; 1241 1242 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1243 continue; 1244 if (!p) { 1245 printf("auich_trigger_input: bad addr %p\n", start); 1246 return EINVAL; 1247 } 1248 1249 size = (size_t)((caddr_t)end - (caddr_t)start); 1250 1251 sc->pcmi.intr = intr; 1252 sc->pcmi.arg = arg; 1253 sc->pcmi.start = DMAADDR(p); 1254 sc->pcmi.p = sc->pcmi.start; 1255 sc->pcmi.end = sc->pcmi.start + size; 1256 sc->pcmi.blksize = blksize; 1257 1258 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1259 sc->sc_cddma + ICH_PCMI_OFF(0)); 1260 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1261 1262 return 0; 1263 } 1264 1265 static int 1266 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1267 struct auich_dma *p) 1268 { 1269 int error; 1270 1271 p->size = size; 1272 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1273 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1274 &p->nsegs, BUS_DMA_NOWAIT); 1275 if (error) 1276 return error; 1277 1278 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1279 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1280 if (error) 1281 goto free; 1282 1283 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1284 0, BUS_DMA_NOWAIT, &p->map); 1285 if (error) 1286 goto unmap; 1287 1288 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1289 BUS_DMA_NOWAIT); 1290 if (error) 1291 goto destroy; 1292 return 0; 1293 1294 destroy: 1295 bus_dmamap_destroy(sc->dmat, p->map); 1296 unmap: 1297 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1298 free: 1299 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1300 return error; 1301 } 1302 1303 static int 1304 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1305 { 1306 1307 bus_dmamap_unload(sc->dmat, p->map); 1308 bus_dmamap_destroy(sc->dmat, p->map); 1309 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1310 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1311 return 0; 1312 } 1313 1314 static int 1315 auich_alloc_cdata(struct auich_softc *sc) 1316 { 1317 bus_dma_segment_t seg; 1318 int error, rseg; 1319 1320 /* 1321 * Allocate the control data structure, and create and load the 1322 * DMA map for it. 1323 */ 1324 if ((error = bus_dmamem_alloc(sc->dmat, 1325 sizeof(struct auich_cdata), 1326 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1327 printf("%s: unable to allocate control data, error = %d\n", 1328 sc->sc_dev.dv_xname, error); 1329 goto fail_0; 1330 } 1331 1332 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1333 sizeof(struct auich_cdata), 1334 (caddr_t *) &sc->sc_cdata, 1335 sc->sc_dmamap_flags)) != 0) { 1336 printf("%s: unable to map control data, error = %d\n", 1337 sc->sc_dev.dv_xname, error); 1338 goto fail_1; 1339 } 1340 1341 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1342 sizeof(struct auich_cdata), 0, 0, 1343 &sc->sc_cddmamap)) != 0) { 1344 printf("%s: unable to create control data DMA map, " 1345 "error = %d\n", sc->sc_dev.dv_xname, error); 1346 goto fail_2; 1347 } 1348 1349 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1350 sc->sc_cdata, sizeof(struct auich_cdata), 1351 NULL, 0)) != 0) { 1352 printf("%s: unable tp load control data DMA map, " 1353 "error = %d\n", sc->sc_dev.dv_xname, error); 1354 goto fail_3; 1355 } 1356 1357 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1358 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1359 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1360 1361 return 0; 1362 1363 fail_3: 1364 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1365 fail_2: 1366 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1367 sizeof(struct auich_cdata)); 1368 fail_1: 1369 bus_dmamem_free(sc->dmat, &seg, rseg); 1370 fail_0: 1371 return error; 1372 } 1373 1374 static void 1375 auich_powerhook(int why, void *addr) 1376 { 1377 struct auich_softc *sc; 1378 1379 sc = (struct auich_softc *)addr; 1380 switch (why) { 1381 case PWR_SUSPEND: 1382 case PWR_STANDBY: 1383 /* Power down */ 1384 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1385 sc->sc_suspend = why; 1386 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1387 break; 1388 1389 case PWR_RESUME: 1390 /* Wake up */ 1391 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1392 if (sc->sc_suspend == PWR_RESUME) { 1393 printf("%s: resume without suspend.\n", 1394 sc->sc_dev.dv_xname); 1395 sc->sc_suspend = why; 1396 return; 1397 } 1398 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1399 sc->sc_suspend = why; 1400 auich_reset_codec(sc); 1401 DELAY(1000); 1402 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1403 break; 1404 1405 case PWR_SOFTSUSPEND: 1406 case PWR_SOFTSTANDBY: 1407 case PWR_SOFTRESUME: 1408 break; 1409 } 1410 } 1411 1412 /* 1413 * Calibrate card (some boards are overclocked and need scaling) 1414 */ 1415 static void 1416 auich_calibrate(struct auich_softc *sc) 1417 { 1418 struct timeval t1, t2; 1419 uint8_t ociv, nciv; 1420 uint64_t wait_us; 1421 uint32_t actual_48k_rate, bytes, ac97rate; 1422 void *temp_buffer; 1423 struct auich_dma *p; 1424 u_int rate; 1425 1426 /* 1427 * Grab audio from input for fixed interval and compare how 1428 * much we actually get with what we expect. Interval needs 1429 * to be sufficiently short that no interrupts are 1430 * generated. 1431 */ 1432 1433 /* Force the codec to a known state first. */ 1434 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1435 rate = sc->sc_ac97_clock = 48000; 1436 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1437 &rate); 1438 1439 /* Setup a buffer */ 1440 bytes = 64000; 1441 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1442 1443 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1444 continue; 1445 if (p == NULL) { 1446 printf("auich_calibrate: bad address %p\n", temp_buffer); 1447 return; 1448 } 1449 sc->pcmi.dmalist[0].base = DMAADDR(p); 1450 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1451 1452 /* 1453 * our data format is stereo, 16 bit so each sample is 4 bytes. 1454 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1455 * we're going to start recording with interrupts disabled and measure 1456 * the time taken for one block to complete. we know the block size, 1457 * we know the time in microseconds, we calculate the sample rate: 1458 * 1459 * actual_rate [bps] = bytes / (time [s] * 4) 1460 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1461 * actual_rate [Hz] = (bytes * 250000) / time [us] 1462 */ 1463 1464 /* prepare */ 1465 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1466 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1467 sc->sc_cddma + ICH_PCMI_OFF(0)); 1468 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1469 (0 - 1) & ICH_LVI_MASK); 1470 1471 /* start */ 1472 microtime(&t1); 1473 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1474 1475 /* wait */ 1476 nciv = ociv; 1477 do { 1478 microtime(&t2); 1479 if (t2.tv_sec - t1.tv_sec > 1) 1480 break; 1481 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1482 ICH_PCMI + ICH_CIV); 1483 } while (nciv == ociv); 1484 microtime(&t2); 1485 1486 /* stop */ 1487 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1488 1489 /* reset */ 1490 DELAY(100); 1491 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1492 1493 /* turn time delta into us */ 1494 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1495 1496 auich_freem(sc, temp_buffer, M_DEVBUF); 1497 1498 if (nciv == ociv) { 1499 printf("%s: ac97 link rate calibration timed out after %" 1500 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1501 return; 1502 } 1503 1504 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1505 1506 if (actual_48k_rate < 50000) 1507 ac97rate = 48000; 1508 else 1509 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1510 1511 printf("%s: measured ac97 link rate at %d Hz", 1512 sc->sc_dev.dv_xname, actual_48k_rate); 1513 if (ac97rate != actual_48k_rate) 1514 printf(", will use %d Hz", ac97rate); 1515 printf("\n"); 1516 1517 sc->sc_ac97_clock = ac97rate; 1518 } 1519
Indexes created Wed Oct 22 13:09:56 GMT 2025