auich.c revision 1.86
1 /* $NetBSD: auich.c,v 1.86 2005/01/26 21:53:42 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.86 2005/01/26 21:53:42 jmcneill Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 187 struct ac97_codec_if *codec_if; 188 struct ac97_host_if host_if; 189 190 /* DMA scatter-gather lists. */ 191 bus_dmamap_t sc_cddmamap; 192 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 193 194 struct auich_cdata *sc_cdata; 195 196 struct auich_ring { 197 int qptr; 198 struct auich_dmalist *dmalist; 199 200 uint32_t start, p, end; 201 int blksize; 202 203 void (*intr)(void *); 204 void *arg; 205 } pcmo, pcmi, mici; 206 207 struct auich_dma *sc_dmas; 208 209 /* SiS 7012 hack */ 210 int sc_sample_shift; 211 int sc_sts_reg; 212 /* 440MX workaround */ 213 int sc_dmamap_flags; 214 215 /* Power Management */ 216 void *sc_powerhook; 217 int sc_suspend; 218 struct pci_conf_state sc_pciconf; 219 220 /* sysctl */ 221 struct sysctllog *sc_log; 222 uint32_t sc_ac97_clock; 223 int sc_ac97_clock_mib; 224 225 #define AUICH_NFORMATS 3 226 struct audio_format sc_formats[AUICH_NFORMATS]; 227 struct audio_encoding_set *sc_encodings; 228 }; 229 230 /* Debug */ 231 #ifdef AUICH_DEBUG 232 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 233 int auich_debug = 0xfffe; 234 #define ICH_DEBUG_CODECIO 0x0001 235 #define ICH_DEBUG_DMA 0x0002 236 #define ICH_DEBUG_INTR 0x0004 237 #else 238 #define DPRINTF(x,y) /* nothing */ 239 #endif 240 241 static int auich_match(struct device *, struct cfdata *, void *); 242 static void auich_attach(struct device *, struct device *, void *); 243 static int auich_detach(struct device *, int); 244 static int auich_activate(struct device *, enum devact); 245 static int auich_intr(void *); 246 247 CFATTACH_DECL(auich, sizeof(struct auich_softc), 248 auich_match, auich_attach, auich_detach, auich_activate); 249 250 static int auich_query_encoding(void *, struct audio_encoding *); 251 static int auich_set_params(void *, int, int, audio_params_t *, 252 audio_params_t *, stream_filter_list_t *, 253 stream_filter_list_t *); 254 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 255 static int auich_halt_output(void *); 256 static int auich_halt_input(void *); 257 static int auich_getdev(void *, struct audio_device *); 258 static int auich_set_port(void *, mixer_ctrl_t *); 259 static int auich_get_port(void *, mixer_ctrl_t *); 260 static int auich_query_devinfo(void *, mixer_devinfo_t *); 261 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 262 static void auich_freem(void *, void *, struct malloc_type *); 263 static size_t auich_round_buffersize(void *, int, size_t); 264 static paddr_t auich_mappage(void *, void *, off_t, int); 265 static int auich_get_props(void *); 266 static int auich_trigger_output(void *, void *, void *, int, 267 void (*)(void *), void *, const audio_params_t *); 268 static int auich_trigger_input(void *, void *, void *, int, 269 void (*)(void *), void *, const audio_params_t *); 270 271 static int auich_alloc_cdata(struct auich_softc *); 272 273 static int auich_allocmem(struct auich_softc *, size_t, size_t, 274 struct auich_dma *); 275 static int auich_freemem(struct auich_softc *, struct auich_dma *); 276 277 static void auich_powerhook(int, void *); 278 static int auich_set_rate(struct auich_softc *, int, u_long); 279 static int auich_sysctl_verify(SYSCTLFN_ARGS); 280 static void auich_finish_attach(struct device *); 281 static void auich_calibrate(struct auich_softc *); 282 283 static int auich_attach_codec(void *, struct ac97_codec_if *); 284 static int auich_read_codec(void *, uint8_t, uint16_t *); 285 static int auich_write_codec(void *, uint8_t, uint16_t); 286 static int auich_reset_codec(void *); 287 288 const struct audio_hw_if auich_hw_if = { 289 NULL, /* open */ 290 NULL, /* close */ 291 NULL, /* drain */ 292 auich_query_encoding, 293 auich_set_params, 294 auich_round_blocksize, 295 NULL, /* commit_setting */ 296 NULL, /* init_output */ 297 NULL, /* init_input */ 298 NULL, /* start_output */ 299 NULL, /* start_input */ 300 auich_halt_output, 301 auich_halt_input, 302 NULL, /* speaker_ctl */ 303 auich_getdev, 304 NULL, /* getfd */ 305 auich_set_port, 306 auich_get_port, 307 auich_query_devinfo, 308 auich_allocm, 309 auich_freem, 310 auich_round_buffersize, 311 auich_mappage, 312 auich_get_props, 313 auich_trigger_output, 314 auich_trigger_input, 315 NULL, /* dev_ioctl */ 316 }; 317 318 #define AUICH_FORMATS_4CH 1 319 #define AUICH_FORMATS_6CH 2 320 static const struct audio_format auich_formats[AUICH_NFORMATS] = { 321 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 322 2, AUFMT_STEREO, 0, {8000, 48000}}, 323 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 324 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 325 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 326 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 327 }; 328 329 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 330 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 331 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 332 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 333 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 334 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 335 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 336 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 337 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 338 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 339 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 340 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 341 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 342 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 343 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 344 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 345 346 static const struct auich_devtype { 347 pcireg_t id; 348 const char *name; 349 const char *shortname; /* must be less than 11 characters */ 350 } auich_devices[] = { 351 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 352 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 353 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 354 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 355 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 356 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 357 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 358 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 359 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 360 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 361 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 362 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 363 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 364 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 365 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 366 { 0, NULL, NULL }, 367 }; 368 369 static const struct auich_devtype * 370 auich_lookup(struct pci_attach_args *pa) 371 { 372 const struct auich_devtype *d; 373 374 for (d = auich_devices; d->name != NULL; d++) { 375 if (pa->pa_id == d->id) 376 return d; 377 } 378 379 return NULL; 380 } 381 382 static int 383 auich_match(struct device *parent, struct cfdata *match, void *aux) 384 { 385 struct pci_attach_args *pa; 386 387 pa = aux; 388 if (auich_lookup(pa) != NULL) 389 return 1; 390 391 return 0; 392 } 393 394 static void 395 auich_attach(struct device *parent, struct device *self, void *aux) 396 { 397 struct auich_softc *sc; 398 struct pci_attach_args *pa; 399 pci_intr_handle_t ih; 400 pcireg_t v; 401 const char *intrstr; 402 const struct auich_devtype *d; 403 struct sysctlnode *node; 404 int err, node_mib, i; 405 406 sc = (struct auich_softc *)self; 407 pa = aux; 408 aprint_naive(": Audio controller\n"); 409 410 d = auich_lookup(pa); 411 if (d == NULL) 412 panic("auich_attach: impossible"); 413 414 sc->sc_pc = pa->pa_pc; 415 sc->sc_pt = pa->pa_tag; 416 417 aprint_normal(": %s\n", d->name); 418 419 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6) { 420 /* 421 * Use native mode for ICH4/ICH5/ICH6 422 */ 423 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 424 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 425 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 426 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 427 v | ICH_CFG_IOSE); 428 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 429 0, &sc->iot, &sc->mix_ioh, NULL, 430 &sc->mix_size)) { 431 aprint_error("%s: can't map codec i/o space\n", 432 sc->sc_dev.dv_xname); 433 return; 434 } 435 } 436 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 437 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 438 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 439 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 440 v | ICH_CFG_IOSE); 441 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 442 0, &sc->iot, &sc->aud_ioh, NULL, 443 &sc->aud_size)) { 444 aprint_error("%s: can't map device i/o space\n", 445 sc->sc_dev.dv_xname); 446 return; 447 } 448 } 449 } else { 450 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 451 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 452 aprint_error("%s: can't map codec i/o space\n", 453 sc->sc_dev.dv_xname); 454 return; 455 } 456 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 457 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 458 aprint_error("%s: can't map device i/o space\n", 459 sc->sc_dev.dv_xname); 460 return; 461 } 462 } 463 sc->dmat = pa->pa_dmat; 464 465 /* enable bus mastering */ 466 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 467 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 468 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 469 470 /* Map and establish the interrupt. */ 471 if (pci_intr_map(pa, &ih)) { 472 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 473 return; 474 } 475 intrstr = pci_intr_string(pa->pa_pc, ih); 476 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 477 auich_intr, sc); 478 if (sc->sc_ih == NULL) { 479 aprint_error("%s: can't establish interrupt", 480 sc->sc_dev.dv_xname); 481 if (intrstr != NULL) 482 aprint_normal(" at %s", intrstr); 483 aprint_normal("\n"); 484 return; 485 } 486 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 487 488 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 489 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 490 "0x%02x", PCI_REVISION(pa->pa_class)); 491 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 492 493 /* SiS 7012 needs special handling */ 494 if (d->id == PCIID_SIS7012) { 495 sc->sc_sts_reg = ICH_PICB; 496 sc->sc_sample_shift = 0; 497 /* Un-mute output. From Linux. */ 498 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 499 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 500 ICH_SIS_CTL_UNMUTE); 501 } else { 502 sc->sc_sts_reg = ICH_STS; 503 sc->sc_sample_shift = 1; 504 } 505 506 /* Workaround for a 440MX B-stepping erratum */ 507 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 508 if (d->id == PCIID_440MX) { 509 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 510 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 511 } 512 513 /* Set up DMA lists. */ 514 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 515 auich_alloc_cdata(sc); 516 517 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 518 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 519 520 sc->host_if.arg = sc; 521 sc->host_if.attach = auich_attach_codec; 522 sc->host_if.read = auich_read_codec; 523 sc->host_if.write = auich_write_codec; 524 sc->host_if.reset = auich_reset_codec; 525 526 if (ac97_attach(&sc->host_if, self) != 0) 527 return; 528 529 /* setup audio_format */ 530 memcpy(sc->sc_formats, auich_formats, sizeof(auich_formats)); 531 if (!AC97_IS_4CH(sc->codec_if)) 532 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_4CH]); 533 if (!AC97_IS_6CH(sc->codec_if)) 534 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_6CH]); 535 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 536 for (i = 0; i < AUICH_NFORMATS; i++) { 537 sc->sc_formats[i].frequency_type = 1; 538 sc->sc_formats[i].frequency[0] = 48000; 539 } 540 } 541 542 if (0 != auconv_create_encodings(sc->sc_formats, AUICH_NFORMATS, 543 &sc->sc_encodings)) { 544 return; 545 } 546 547 /* Watch for power change */ 548 sc->sc_suspend = PWR_RESUME; 549 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 550 551 config_interrupts(self, auich_finish_attach); 552 553 /* sysctl setup */ 554 if (AC97_IS_FIXED_RATE(sc->codec_if)) 555 return; 556 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 557 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 558 CTL_HW, CTL_EOL); 559 if (err != 0) 560 goto sysctl_err; 561 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 562 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 563 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 564 if (err != 0) 565 goto sysctl_err; 566 node_mib = node->sysctl_num; 567 /* passing the sc address instead of &sc->sc_ac97_clock */ 568 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 569 CTLTYPE_INT, "ac97rate", 570 SYSCTL_DESCR("AC'97 codec link rate"), 571 auich_sysctl_verify, 0, sc, 0, 572 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 573 if (err != 0) 574 goto sysctl_err; 575 sc->sc_ac97_clock_mib = node->sysctl_num; 576 577 return; 578 579 sysctl_err: 580 printf("%s: failed to add sysctl nodes. (%d)\n", 581 sc->sc_dev.dv_xname, err); 582 return; /* failure of sysctl is not fatal. */ 583 } 584 585 static int 586 auich_activate(struct device *self, enum devact act) 587 { 588 struct auich_softc *sc; 589 int ret; 590 591 sc = (struct auich_softc *)self; 592 ret = 0; 593 switch (act) { 594 case DVACT_ACTIVATE: 595 return EOPNOTSUPP; 596 case DVACT_DEACTIVATE: 597 if (sc->sc_audiodev != NULL) 598 ret = config_deactivate(sc->sc_audiodev); 599 return ret; 600 } 601 return EOPNOTSUPP; 602 } 603 604 static int 605 auich_detach(struct device *self, int flags) 606 { 607 struct auich_softc *sc; 608 609 sc = (struct auich_softc *)self; 610 611 /* audio */ 612 if (sc->sc_audiodev != NULL) 613 config_detach(sc->sc_audiodev, flags); 614 615 /* sysctl */ 616 sysctl_teardown(&sc->sc_log); 617 618 /* audio_encoding_set */ 619 auconv_delete_encodings(sc->sc_encodings); 620 621 /* ac97 */ 622 if (sc->codec_if != NULL) 623 sc->codec_if->vtbl->detach(sc->codec_if); 624 625 /* PCI */ 626 if (sc->sc_ih != NULL) 627 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 628 if (sc->mix_size != 0) 629 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 630 if (sc->aud_size != 0) 631 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 632 return 0; 633 } 634 635 static int 636 auich_sysctl_verify(SYSCTLFN_ARGS) 637 { 638 int error, tmp; 639 struct sysctlnode node; 640 struct auich_softc *sc; 641 642 node = *rnode; 643 sc = rnode->sysctl_data; 644 tmp = sc->sc_ac97_clock; 645 node.sysctl_data = &tmp; 646 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 647 if (error || newp == NULL) 648 return error; 649 650 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 651 if (tmp < 48000 || tmp > 96000) 652 return EINVAL; 653 sc->sc_ac97_clock = tmp; 654 } 655 656 return 0; 657 } 658 659 static void 660 auich_finish_attach(struct device *self) 661 { 662 struct auich_softc *sc; 663 664 sc = (void *)self; 665 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 666 auich_calibrate(sc); 667 668 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 669 } 670 671 #define ICH_CODECIO_INTERVAL 10 672 static int 673 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 674 { 675 struct auich_softc *sc; 676 int i; 677 uint32_t status; 678 679 sc = v; 680 /* wait for an access semaphore */ 681 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 682 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 683 DELAY(ICH_CODECIO_INTERVAL)); 684 685 if (i > 0) { 686 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 687 DPRINTF(ICH_DEBUG_CODECIO, 688 ("auich_read_codec(%x, %x)\n", reg, *val)); 689 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 690 if (status & ICH_RCS) { 691 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 692 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 693 *val = 0xffff; 694 DPRINTF(ICH_DEBUG_CODECIO, 695 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 696 return -1; 697 } 698 return 0; 699 } else { 700 DPRINTF(ICH_DEBUG_CODECIO, 701 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 702 return -1; 703 } 704 } 705 706 static int 707 auich_write_codec(void *v, uint8_t reg, uint16_t val) 708 { 709 struct auich_softc *sc; 710 int i; 711 712 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 713 sc = v; 714 /* wait for an access semaphore */ 715 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 716 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 717 DELAY(ICH_CODECIO_INTERVAL)); 718 719 if (i > 0) { 720 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 721 return 0; 722 } else { 723 DPRINTF(ICH_DEBUG_CODECIO, 724 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 725 return -1; 726 } 727 } 728 729 static int 730 auich_attach_codec(void *v, struct ac97_codec_if *cif) 731 { 732 struct auich_softc *sc; 733 734 sc = v; 735 sc->codec_if = cif; 736 return 0; 737 } 738 739 static int 740 auich_reset_codec(void *v) 741 { 742 struct auich_softc *sc; 743 int i; 744 uint32_t control, status; 745 746 sc = v; 747 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 748 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 749 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 750 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 751 752 for (i = 500000; i >= 0; i--) { 753 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 754 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 755 break; 756 DELAY(1); 757 } 758 if (i <= 0) { 759 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 760 return ETIMEDOUT; 761 } 762 #ifdef DEBUG 763 if (status & ICH_SCR) 764 printf("%s: The 2nd codec is ready.\n", 765 sc->sc_dev.dv_xname); 766 if (status & ICH_S2CR) 767 printf("%s: The 3rd codec is ready.\n", 768 sc->sc_dev.dv_xname); 769 #endif 770 return 0; 771 } 772 773 static int 774 auich_query_encoding(void *v, struct audio_encoding *aep) 775 { 776 struct auich_softc *sc; 777 778 sc = (struct auich_softc *)v; 779 return auconv_query_encoding(sc->sc_encodings, aep); 780 } 781 782 static int 783 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 784 { 785 int ret; 786 u_int ratetmp; 787 788 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 789 ratetmp = srate; 790 if (mode == AUMODE_RECORD) 791 return sc->codec_if->vtbl->set_rate(sc->codec_if, 792 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 793 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 794 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 795 if (ret) 796 return ret; 797 ratetmp = srate; 798 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 799 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 800 if (ret) 801 return ret; 802 ratetmp = srate; 803 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 804 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 805 return ret; 806 } 807 808 static int 809 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 810 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 811 { 812 struct auich_softc *sc; 813 audio_params_t *p; 814 stream_filter_list_t *fil; 815 int mode, index; 816 uint32_t control; 817 818 sc = v; 819 for (mode = AUMODE_RECORD; mode != -1; 820 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 821 if ((setmode & mode) == 0) 822 continue; 823 824 p = mode == AUMODE_PLAY ? play : rec; 825 fil = mode == AUMODE_PLAY ? pfil : rfil; 826 if (p == NULL) 827 continue; 828 829 if (p->sample_rate < 8000 || 830 p->sample_rate > 48000) 831 return EINVAL; 832 833 index = auconv_set_converter(sc->sc_formats, AUICH_NFORMATS, 834 mode, p, TRUE, fil); 835 if (index < 0) 836 return EINVAL; 837 if (fil->req_size > 0) 838 p = &fil->filters[0].param; 839 /* p represents HW encoding */ 840 if (sc->sc_formats[index].frequency_type != 1 841 && auich_set_rate(sc, mode, p->sample_rate)) 842 return EINVAL; 843 if (mode == AUMODE_PLAY) { 844 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 845 control &= ~ICH_PCM246_MASK; 846 if (p->channels == 4) { 847 control |= ICH_PCM4; 848 } else if (p->channels == 6) { 849 control |= ICH_PCM6; 850 } 851 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 852 } 853 } 854 855 return 0; 856 } 857 858 static int 859 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 860 { 861 862 return blk & ~0x3f; /* keep good alignment */ 863 } 864 865 static int 866 auich_halt_output(void *v) 867 { 868 struct auich_softc *sc; 869 870 sc = v; 871 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 872 873 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 874 sc->pcmo.intr = NULL; 875 876 return 0; 877 } 878 879 static int 880 auich_halt_input(void *v) 881 { 882 struct auich_softc *sc; 883 884 sc = v; 885 DPRINTF(ICH_DEBUG_DMA, 886 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 887 888 /* XXX halt both unless known otherwise */ 889 890 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 891 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 892 sc->pcmi.intr = NULL; 893 894 return 0; 895 } 896 897 static int 898 auich_getdev(void *v, struct audio_device *adp) 899 { 900 struct auich_softc *sc; 901 902 sc = v; 903 *adp = sc->sc_audev; 904 return 0; 905 } 906 907 static int 908 auich_set_port(void *v, mixer_ctrl_t *cp) 909 { 910 struct auich_softc *sc; 911 912 sc = v; 913 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 914 } 915 916 static int 917 auich_get_port(void *v, mixer_ctrl_t *cp) 918 { 919 struct auich_softc *sc; 920 921 sc = v; 922 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 923 } 924 925 static int 926 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 927 { 928 struct auich_softc *sc; 929 930 sc = v; 931 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 932 } 933 934 static void * 935 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 936 int flags) 937 { 938 struct auich_softc *sc; 939 struct auich_dma *p; 940 int error; 941 942 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 943 return NULL; 944 945 p = malloc(sizeof(*p), pool, flags|M_ZERO); 946 if (p == NULL) 947 return NULL; 948 949 sc = v; 950 error = auich_allocmem(sc, size, 0, p); 951 if (error) { 952 free(p, pool); 953 return NULL; 954 } 955 956 p->next = sc->sc_dmas; 957 sc->sc_dmas = p; 958 959 return KERNADDR(p); 960 } 961 962 static void 963 auich_freem(void *v, void *ptr, struct malloc_type *pool) 964 { 965 struct auich_softc *sc; 966 struct auich_dma *p, **pp; 967 968 sc = v; 969 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 970 if (KERNADDR(p) == ptr) { 971 auich_freemem(sc, p); 972 *pp = p->next; 973 free(p, pool); 974 return; 975 } 976 } 977 } 978 979 static size_t 980 auich_round_buffersize(void *v, int direction, size_t size) 981 { 982 983 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 984 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 985 986 return size; 987 } 988 989 static paddr_t 990 auich_mappage(void *v, void *mem, off_t off, int prot) 991 { 992 struct auich_softc *sc; 993 struct auich_dma *p; 994 995 if (off < 0) 996 return -1; 997 sc = v; 998 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 999 continue; 1000 if (!p) 1001 return -1; 1002 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1003 off, prot, BUS_DMA_WAITOK); 1004 } 1005 1006 static int 1007 auich_get_props(void *v) 1008 { 1009 struct auich_softc *sc; 1010 int props; 1011 1012 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1013 sc = v; 1014 /* 1015 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1016 * rate because of aurateconv. Applications can't know what rate the 1017 * device can process in the case of mmap(). 1018 */ 1019 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 1020 props |= AUDIO_PROP_MMAP; 1021 return props; 1022 } 1023 1024 static int 1025 auich_intr(void *v) 1026 { 1027 struct auich_softc *sc; 1028 int ret, gsts; 1029 #ifdef DIAGNOSTIC 1030 int csts; 1031 #endif 1032 1033 sc = v; 1034 ret = 0; 1035 #ifdef DIAGNOSTIC 1036 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1037 if (csts & PCI_STATUS_MASTER_ABORT) { 1038 printf("auich_intr: PCI master abort\n"); 1039 } 1040 #endif 1041 1042 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 1043 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1044 1045 if (gsts & ICH_POINT) { 1046 int sts; 1047 1048 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1049 ICH_PCMO + sc->sc_sts_reg); 1050 DPRINTF(ICH_DEBUG_INTR, 1051 ("auich_intr: osts=0x%x\n", sts)); 1052 1053 if (sts & ICH_FIFOE) 1054 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1055 1056 if (sts & ICH_BCIS) { 1057 struct auich_dmalist *q; 1058 int blksize, qptr, i; 1059 1060 blksize = sc->pcmo.blksize; 1061 qptr = sc->pcmo.qptr; 1062 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1063 ICH_PCMO + ICH_CIV); 1064 1065 while (qptr != i) { 1066 q = &sc->pcmo.dmalist[qptr]; 1067 1068 q->base = sc->pcmo.p; 1069 q->len = (blksize >> sc->sc_sample_shift) | 1070 ICH_DMAF_IOC; 1071 DPRINTF(ICH_DEBUG_INTR, 1072 ("auich_intr: %p, %p = %x @ 0x%x\n", 1073 &sc->pcmo.dmalist[i], q, q->len, q->base)); 1074 1075 sc->pcmo.p += blksize; 1076 if (sc->pcmo.p >= sc->pcmo.end) 1077 sc->pcmo.p = sc->pcmo.start; 1078 1079 qptr = (qptr + 1) & ICH_LVI_MASK; 1080 if (sc->pcmo.intr) 1081 sc->pcmo.intr(sc->pcmo.arg); 1082 } 1083 1084 sc->pcmo.qptr = qptr; 1085 bus_space_write_1(sc->iot, sc->aud_ioh, 1086 ICH_PCMO + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1087 } 1088 1089 /* int ack */ 1090 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1091 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1092 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1093 ret++; 1094 } 1095 1096 if (gsts & ICH_PIINT) { 1097 int sts; 1098 1099 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1100 ICH_PCMI + sc->sc_sts_reg); 1101 DPRINTF(ICH_DEBUG_INTR, 1102 ("auich_intr: ists=0x%x\n", sts)); 1103 1104 if (sts & ICH_FIFOE) 1105 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1106 1107 if (sts & ICH_BCIS) { 1108 struct auich_dmalist *q; 1109 int blksize, qptr, i; 1110 1111 blksize = sc->pcmi.blksize; 1112 qptr = sc->pcmi.qptr; 1113 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1114 ICH_PCMI + ICH_CIV); 1115 1116 while (qptr != i) { 1117 q = &sc->pcmi.dmalist[qptr]; 1118 1119 q->base = sc->pcmi.p; 1120 q->len = (blksize >> sc->sc_sample_shift) | 1121 ICH_DMAF_IOC; 1122 DPRINTF(ICH_DEBUG_INTR, 1123 ("auich_intr: %p, %p = %x @ 0x%x\n", 1124 &sc->pcmi.dmalist[i], q, q->len, q->base)); 1125 1126 sc->pcmi.p += blksize; 1127 if (sc->pcmi.p >= sc->pcmi.end) 1128 sc->pcmi.p = sc->pcmi.start; 1129 1130 qptr = (qptr + 1) & ICH_LVI_MASK; 1131 if (sc->pcmi.intr) 1132 sc->pcmi.intr(sc->pcmi.arg); 1133 } 1134 1135 sc->pcmi.qptr = qptr; 1136 bus_space_write_1(sc->iot, sc->aud_ioh, 1137 ICH_PCMI + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1138 } 1139 1140 /* int ack */ 1141 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1142 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1143 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1144 ret++; 1145 } 1146 1147 if (gsts & ICH_MIINT) { 1148 int sts; 1149 1150 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1151 ICH_MICI + sc->sc_sts_reg); 1152 DPRINTF(ICH_DEBUG_INTR, 1153 ("auich_intr: ists=0x%x\n", sts)); 1154 1155 if (sts & ICH_FIFOE) 1156 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1157 1158 /* TODO mic input DMA */ 1159 1160 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1161 } 1162 1163 return ret; 1164 } 1165 1166 static int 1167 auich_trigger_output(void *v, void *start, void *end, int blksize, 1168 void (*intr)(void *), void *arg, const audio_params_t *param) 1169 { 1170 struct auich_softc *sc; 1171 struct auich_dmalist *q; 1172 struct auich_dma *p; 1173 size_t size; 1174 int qptr; 1175 #ifdef DIAGNOSTIC 1176 int csts; 1177 #endif 1178 1179 DPRINTF(ICH_DEBUG_DMA, 1180 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1181 start, end, blksize, intr, arg, param)); 1182 sc = v; 1183 sc->pcmo.intr = intr; 1184 sc->pcmo.arg = arg; 1185 #ifdef DIAGNOSTIC 1186 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1187 if (csts & PCI_STATUS_MASTER_ABORT) { 1188 printf("auich_trigger_output: PCI master abort\n"); 1189 } 1190 #endif 1191 1192 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1193 continue; 1194 if (!p) { 1195 printf("auich_trigger_output: bad addr %p\n", start); 1196 return EINVAL; 1197 } 1198 1199 size = (size_t)((caddr_t)end - (caddr_t)start); 1200 1201 /* 1202 * The logic behind this is: 1203 * setup one buffer to play, then LVI dump out the rest 1204 * to the scatter-gather chain. 1205 */ 1206 sc->pcmo.start = DMAADDR(p); 1207 sc->pcmo.p = sc->pcmo.start; 1208 sc->pcmo.end = sc->pcmo.start + size; 1209 sc->pcmo.blksize = blksize; 1210 1211 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1212 q = &sc->pcmo.dmalist[qptr]; 1213 1214 q->base = sc->pcmo.p; 1215 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1216 1217 sc->pcmo.p += blksize; 1218 if (sc->pcmo.p >= sc->pcmo.end) 1219 sc->pcmo.p = sc->pcmo.start; 1220 } 1221 1222 sc->pcmo.qptr = qptr = 0; 1223 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1224 (qptr - 1) & ICH_LVI_MASK); 1225 1226 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1227 sc->sc_cddma + ICH_PCMO_OFF(0)); 1228 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1229 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1230 1231 return 0; 1232 } 1233 1234 static int 1235 auich_trigger_input(void *v, void *start, void *end, int blksize, 1236 void (*intr)(void *), void *arg, const audio_params_t *param) 1237 { 1238 struct auich_softc *sc; 1239 struct auich_dmalist *q; 1240 struct auich_dma *p; 1241 size_t size; 1242 int qptr; 1243 #ifdef DIAGNOSTIC 1244 int csts; 1245 #endif 1246 1247 DPRINTF(ICH_DEBUG_DMA, 1248 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1249 start, end, blksize, intr, arg, param)); 1250 sc = v; 1251 sc->pcmi.intr = intr; 1252 sc->pcmi.arg = arg; 1253 1254 #ifdef DIAGNOSTIC 1255 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1256 if (csts & PCI_STATUS_MASTER_ABORT) { 1257 printf("auich_trigger_input: PCI master abort\n"); 1258 } 1259 #endif 1260 1261 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1262 continue; 1263 if (!p) { 1264 printf("auich_trigger_input: bad addr %p\n", start); 1265 return EINVAL; 1266 } 1267 1268 size = (size_t)((caddr_t)end - (caddr_t)start); 1269 1270 /* 1271 * The logic behind this is: 1272 * setup one buffer to play, then LVI dump out the rest 1273 * to the scatter-gather chain. 1274 */ 1275 sc->pcmi.start = DMAADDR(p); 1276 sc->pcmi.p = sc->pcmi.start; 1277 sc->pcmi.end = sc->pcmi.start + size; 1278 sc->pcmi.blksize = blksize; 1279 1280 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1281 q = &sc->pcmi.dmalist[qptr]; 1282 1283 q->base = sc->pcmi.p; 1284 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1285 1286 sc->pcmi.p += blksize; 1287 if (sc->pcmi.p >= sc->pcmi.end) 1288 sc->pcmi.p = sc->pcmi.start; 1289 } 1290 1291 sc->pcmi.qptr = qptr = 0; 1292 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1293 (qptr - 1) & ICH_LVI_MASK); 1294 1295 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1296 sc->sc_cddma + ICH_PCMI_OFF(0)); 1297 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1298 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1299 1300 return 0; 1301 } 1302 1303 static int 1304 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1305 struct auich_dma *p) 1306 { 1307 int error; 1308 1309 p->size = size; 1310 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1311 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1312 &p->nsegs, BUS_DMA_NOWAIT); 1313 if (error) 1314 return error; 1315 1316 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1317 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1318 if (error) 1319 goto free; 1320 1321 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1322 0, BUS_DMA_NOWAIT, &p->map); 1323 if (error) 1324 goto unmap; 1325 1326 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1327 BUS_DMA_NOWAIT); 1328 if (error) 1329 goto destroy; 1330 return 0; 1331 1332 destroy: 1333 bus_dmamap_destroy(sc->dmat, p->map); 1334 unmap: 1335 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1336 free: 1337 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1338 return error; 1339 } 1340 1341 static int 1342 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1343 { 1344 1345 bus_dmamap_unload(sc->dmat, p->map); 1346 bus_dmamap_destroy(sc->dmat, p->map); 1347 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1348 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1349 return 0; 1350 } 1351 1352 static int 1353 auich_alloc_cdata(struct auich_softc *sc) 1354 { 1355 bus_dma_segment_t seg; 1356 int error, rseg; 1357 1358 /* 1359 * Allocate the control data structure, and create and load the 1360 * DMA map for it. 1361 */ 1362 if ((error = bus_dmamem_alloc(sc->dmat, 1363 sizeof(struct auich_cdata), 1364 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1365 printf("%s: unable to allocate control data, error = %d\n", 1366 sc->sc_dev.dv_xname, error); 1367 goto fail_0; 1368 } 1369 1370 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1371 sizeof(struct auich_cdata), 1372 (caddr_t *) &sc->sc_cdata, 1373 sc->sc_dmamap_flags)) != 0) { 1374 printf("%s: unable to map control data, error = %d\n", 1375 sc->sc_dev.dv_xname, error); 1376 goto fail_1; 1377 } 1378 1379 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1380 sizeof(struct auich_cdata), 0, 0, 1381 &sc->sc_cddmamap)) != 0) { 1382 printf("%s: unable to create control data DMA map, " 1383 "error = %d\n", sc->sc_dev.dv_xname, error); 1384 goto fail_2; 1385 } 1386 1387 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1388 sc->sc_cdata, sizeof(struct auich_cdata), 1389 NULL, 0)) != 0) { 1390 printf("%s: unable tp load control data DMA map, " 1391 "error = %d\n", sc->sc_dev.dv_xname, error); 1392 goto fail_3; 1393 } 1394 1395 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1396 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1397 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1398 1399 return 0; 1400 1401 fail_3: 1402 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1403 fail_2: 1404 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1405 sizeof(struct auich_cdata)); 1406 fail_1: 1407 bus_dmamem_free(sc->dmat, &seg, rseg); 1408 fail_0: 1409 return error; 1410 } 1411 1412 static void 1413 auich_powerhook(int why, void *addr) 1414 { 1415 struct auich_softc *sc; 1416 1417 sc = (struct auich_softc *)addr; 1418 switch (why) { 1419 case PWR_SUSPEND: 1420 case PWR_STANDBY: 1421 /* Power down */ 1422 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1423 sc->sc_suspend = why; 1424 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1425 break; 1426 1427 case PWR_RESUME: 1428 /* Wake up */ 1429 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1430 if (sc->sc_suspend == PWR_RESUME) { 1431 printf("%s: resume without suspend.\n", 1432 sc->sc_dev.dv_xname); 1433 sc->sc_suspend = why; 1434 return; 1435 } 1436 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1437 sc->sc_suspend = why; 1438 auich_reset_codec(sc); 1439 DELAY(1000); 1440 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1441 break; 1442 1443 case PWR_SOFTSUSPEND: 1444 case PWR_SOFTSTANDBY: 1445 case PWR_SOFTRESUME: 1446 break; 1447 } 1448 } 1449 1450 /* 1451 * Calibrate card (some boards are overclocked and need scaling) 1452 */ 1453 static void 1454 auich_calibrate(struct auich_softc *sc) 1455 { 1456 struct timeval t1, t2; 1457 uint8_t ociv, nciv; 1458 uint64_t wait_us; 1459 uint32_t actual_48k_rate, bytes, ac97rate; 1460 void *temp_buffer; 1461 struct auich_dma *p; 1462 u_int rate; 1463 1464 /* 1465 * Grab audio from input for fixed interval and compare how 1466 * much we actually get with what we expect. Interval needs 1467 * to be sufficiently short that no interrupts are 1468 * generated. 1469 */ 1470 1471 /* Force the codec to a known state first. */ 1472 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1473 rate = sc->sc_ac97_clock = 48000; 1474 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1475 &rate); 1476 1477 /* Setup a buffer */ 1478 bytes = 64000; 1479 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1480 1481 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1482 continue; 1483 if (p == NULL) { 1484 printf("auich_calibrate: bad address %p\n", temp_buffer); 1485 return; 1486 } 1487 sc->pcmi.dmalist[0].base = DMAADDR(p); 1488 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1489 1490 /* 1491 * our data format is stereo, 16 bit so each sample is 4 bytes. 1492 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1493 * we're going to start recording with interrupts disabled and measure 1494 * the time taken for one block to complete. we know the block size, 1495 * we know the time in microseconds, we calculate the sample rate: 1496 * 1497 * actual_rate [bps] = bytes / (time [s] * 4) 1498 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1499 * actual_rate [Hz] = (bytes * 250000) / time [us] 1500 */ 1501 1502 /* prepare */ 1503 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1504 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1505 sc->sc_cddma + ICH_PCMI_OFF(0)); 1506 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1507 (0 - 1) & ICH_LVI_MASK); 1508 1509 /* start */ 1510 microtime(&t1); 1511 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1512 1513 /* wait */ 1514 nciv = ociv; 1515 do { 1516 microtime(&t2); 1517 if (t2.tv_sec - t1.tv_sec > 1) 1518 break; 1519 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1520 ICH_PCMI + ICH_CIV); 1521 } while (nciv == ociv); 1522 microtime(&t2); 1523 1524 /* stop */ 1525 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1526 1527 /* reset */ 1528 DELAY(100); 1529 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1530 1531 /* turn time delta into us */ 1532 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1533 1534 auich_freem(sc, temp_buffer, M_DEVBUF); 1535 1536 if (nciv == ociv) { 1537 printf("%s: ac97 link rate calibration timed out after %" 1538 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1539 return; 1540 } 1541 1542 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1543 1544 if (actual_48k_rate < 50000) 1545 ac97rate = 48000; 1546 else 1547 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1548 1549 printf("%s: measured ac97 link rate at %d Hz", 1550 sc->sc_dev.dv_xname, actual_48k_rate); 1551 if (ac97rate != actual_48k_rate) 1552 printf(", will use %d Hz", ac97rate); 1553 printf("\n"); 1554 1555 sc->sc_ac97_clock = ac97rate; 1556 } 1557
Indexes created Thu Oct 23 22:10:10 GMT 2025