auich.c revision 1.89
1 /* $NetBSD: auich.c,v 1.89 2005/02/27 00:27:32 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.89 2005/02/27 00:27:32 perry Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 187 struct ac97_codec_if *codec_if; 188 struct ac97_host_if host_if; 189 190 /* DMA scatter-gather lists. */ 191 bus_dmamap_t sc_cddmamap; 192 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 193 194 struct auich_cdata *sc_cdata; 195 196 struct auich_ring { 197 int qptr; 198 struct auich_dmalist *dmalist; 199 200 uint32_t start, p, end; 201 int blksize; 202 203 void (*intr)(void *); 204 void *arg; 205 } pcmo, pcmi, mici; 206 207 struct auich_dma *sc_dmas; 208 209 /* SiS 7012 hack */ 210 int sc_sample_shift; 211 int sc_sts_reg; 212 /* 440MX workaround */ 213 int sc_dmamap_flags; 214 215 /* Power Management */ 216 void *sc_powerhook; 217 int sc_suspend; 218 struct pci_conf_state sc_pciconf; 219 220 /* sysctl */ 221 struct sysctllog *sc_log; 222 uint32_t sc_ac97_clock; 223 int sc_ac97_clock_mib; 224 225 #define AUICH_NFORMATS 3 226 struct audio_format sc_formats[AUICH_NFORMATS]; 227 struct audio_encoding_set *sc_encodings; 228 }; 229 230 /* Debug */ 231 #ifdef AUICH_DEBUG 232 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 233 int auich_debug = 0xfffe; 234 #define ICH_DEBUG_CODECIO 0x0001 235 #define ICH_DEBUG_DMA 0x0002 236 #define ICH_DEBUG_INTR 0x0004 237 #else 238 #define DPRINTF(x,y) /* nothing */ 239 #endif 240 241 static int auich_match(struct device *, struct cfdata *, void *); 242 static void auich_attach(struct device *, struct device *, void *); 243 static int auich_detach(struct device *, int); 244 static int auich_activate(struct device *, enum devact); 245 static int auich_intr(void *); 246 247 CFATTACH_DECL(auich, sizeof(struct auich_softc), 248 auich_match, auich_attach, auich_detach, auich_activate); 249 250 static int auich_query_encoding(void *, struct audio_encoding *); 251 static int auich_set_params(void *, int, int, audio_params_t *, 252 audio_params_t *, stream_filter_list_t *, 253 stream_filter_list_t *); 254 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 255 static int auich_halt_output(void *); 256 static int auich_halt_input(void *); 257 static int auich_getdev(void *, struct audio_device *); 258 static int auich_set_port(void *, mixer_ctrl_t *); 259 static int auich_get_port(void *, mixer_ctrl_t *); 260 static int auich_query_devinfo(void *, mixer_devinfo_t *); 261 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 262 static void auich_freem(void *, void *, struct malloc_type *); 263 static size_t auich_round_buffersize(void *, int, size_t); 264 static paddr_t auich_mappage(void *, void *, off_t, int); 265 static int auich_get_props(void *); 266 static int auich_trigger_output(void *, void *, void *, int, 267 void (*)(void *), void *, const audio_params_t *); 268 static int auich_trigger_input(void *, void *, void *, int, 269 void (*)(void *), void *, const audio_params_t *); 270 271 static int auich_alloc_cdata(struct auich_softc *); 272 273 static int auich_allocmem(struct auich_softc *, size_t, size_t, 274 struct auich_dma *); 275 static int auich_freemem(struct auich_softc *, struct auich_dma *); 276 277 static void auich_powerhook(int, void *); 278 static int auich_set_rate(struct auich_softc *, int, u_long); 279 static int auich_sysctl_verify(SYSCTLFN_ARGS); 280 static void auich_finish_attach(struct device *); 281 static void auich_calibrate(struct auich_softc *); 282 283 static int auich_attach_codec(void *, struct ac97_codec_if *); 284 static int auich_read_codec(void *, uint8_t, uint16_t *); 285 static int auich_write_codec(void *, uint8_t, uint16_t); 286 static int auich_reset_codec(void *); 287 288 const struct audio_hw_if auich_hw_if = { 289 NULL, /* open */ 290 NULL, /* close */ 291 NULL, /* drain */ 292 auich_query_encoding, 293 auich_set_params, 294 auich_round_blocksize, 295 NULL, /* commit_setting */ 296 NULL, /* init_output */ 297 NULL, /* init_input */ 298 NULL, /* start_output */ 299 NULL, /* start_input */ 300 auich_halt_output, 301 auich_halt_input, 302 NULL, /* speaker_ctl */ 303 auich_getdev, 304 NULL, /* getfd */ 305 auich_set_port, 306 auich_get_port, 307 auich_query_devinfo, 308 auich_allocm, 309 auich_freem, 310 auich_round_buffersize, 311 auich_mappage, 312 auich_get_props, 313 auich_trigger_output, 314 auich_trigger_input, 315 NULL, /* dev_ioctl */ 316 }; 317 318 #define AUICH_FORMATS_4CH 1 319 #define AUICH_FORMATS_6CH 2 320 static const struct audio_format auich_formats[AUICH_NFORMATS] = { 321 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 322 2, AUFMT_STEREO, 0, {8000, 48000}}, 323 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 324 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 325 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 326 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 327 }; 328 329 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 330 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 331 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 332 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 333 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 334 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 335 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 336 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 337 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 338 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 339 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 340 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 341 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 342 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 343 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 344 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 345 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 346 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 347 348 static const struct auich_devtype { 349 pcireg_t id; 350 const char *name; 351 const char *shortname; /* must be less than 11 characters */ 352 } auich_devices[] = { 353 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 354 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 355 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 356 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 357 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 358 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 359 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 360 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 361 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 362 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 363 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 364 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 365 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 366 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 367 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 368 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 369 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 370 { 0, NULL, NULL }, 371 }; 372 373 static const struct auich_devtype * 374 auich_lookup(struct pci_attach_args *pa) 375 { 376 const struct auich_devtype *d; 377 378 for (d = auich_devices; d->name != NULL; d++) { 379 if (pa->pa_id == d->id) 380 return d; 381 } 382 383 return NULL; 384 } 385 386 static int 387 auich_match(struct device *parent, struct cfdata *match, void *aux) 388 { 389 struct pci_attach_args *pa; 390 391 pa = aux; 392 if (auich_lookup(pa) != NULL) 393 return 1; 394 395 return 0; 396 } 397 398 static void 399 auich_attach(struct device *parent, struct device *self, void *aux) 400 { 401 struct auich_softc *sc; 402 struct pci_attach_args *pa; 403 pci_intr_handle_t ih; 404 pcireg_t v; 405 const char *intrstr; 406 const struct auich_devtype *d; 407 struct sysctlnode *node; 408 int err, node_mib, i; 409 410 sc = (struct auich_softc *)self; 411 pa = aux; 412 aprint_naive(": Audio controller\n"); 413 414 d = auich_lookup(pa); 415 if (d == NULL) 416 panic("auich_attach: impossible"); 417 418 sc->sc_pc = pa->pa_pc; 419 sc->sc_pt = pa->pa_tag; 420 421 aprint_normal(": %s\n", d->name); 422 423 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6) { 424 /* 425 * Use native mode for ICH4/ICH5/ICH6 426 */ 427 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 428 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 429 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 430 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 431 v | ICH_CFG_IOSE); 432 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 433 0, &sc->iot, &sc->mix_ioh, NULL, 434 &sc->mix_size)) { 435 aprint_error("%s: can't map codec i/o space\n", 436 sc->sc_dev.dv_xname); 437 return; 438 } 439 } 440 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 441 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 442 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 443 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 444 v | ICH_CFG_IOSE); 445 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 446 0, &sc->iot, &sc->aud_ioh, NULL, 447 &sc->aud_size)) { 448 aprint_error("%s: can't map device i/o space\n", 449 sc->sc_dev.dv_xname); 450 return; 451 } 452 } 453 } else { 454 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 455 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 456 aprint_error("%s: can't map codec i/o space\n", 457 sc->sc_dev.dv_xname); 458 return; 459 } 460 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 461 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 462 aprint_error("%s: can't map device i/o space\n", 463 sc->sc_dev.dv_xname); 464 return; 465 } 466 } 467 sc->dmat = pa->pa_dmat; 468 469 /* enable bus mastering */ 470 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 471 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 472 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 473 474 /* Map and establish the interrupt. */ 475 if (pci_intr_map(pa, &ih)) { 476 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 477 return; 478 } 479 intrstr = pci_intr_string(pa->pa_pc, ih); 480 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 481 auich_intr, sc); 482 if (sc->sc_ih == NULL) { 483 aprint_error("%s: can't establish interrupt", 484 sc->sc_dev.dv_xname); 485 if (intrstr != NULL) 486 aprint_normal(" at %s", intrstr); 487 aprint_normal("\n"); 488 return; 489 } 490 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 491 492 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 493 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 494 "0x%02x", PCI_REVISION(pa->pa_class)); 495 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 496 497 /* SiS 7012 needs special handling */ 498 if (d->id == PCIID_SIS7012) { 499 sc->sc_sts_reg = ICH_PICB; 500 sc->sc_sample_shift = 0; 501 /* Un-mute output. From Linux. */ 502 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 503 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 504 ICH_SIS_CTL_UNMUTE); 505 } else { 506 sc->sc_sts_reg = ICH_STS; 507 sc->sc_sample_shift = 1; 508 } 509 510 /* Workaround for a 440MX B-stepping erratum */ 511 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 512 if (d->id == PCIID_440MX) { 513 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 514 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 515 } 516 517 /* Set up DMA lists. */ 518 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 519 auich_alloc_cdata(sc); 520 521 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 522 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 523 524 sc->host_if.arg = sc; 525 sc->host_if.attach = auich_attach_codec; 526 sc->host_if.read = auich_read_codec; 527 sc->host_if.write = auich_write_codec; 528 sc->host_if.reset = auich_reset_codec; 529 530 if (ac97_attach(&sc->host_if, self) != 0) 531 return; 532 533 /* setup audio_format */ 534 memcpy(sc->sc_formats, auich_formats, sizeof(auich_formats)); 535 if (!AC97_IS_4CH(sc->codec_if)) 536 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_4CH]); 537 if (!AC97_IS_6CH(sc->codec_if)) 538 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_6CH]); 539 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 540 for (i = 0; i < AUICH_NFORMATS; i++) { 541 sc->sc_formats[i].frequency_type = 1; 542 sc->sc_formats[i].frequency[0] = 48000; 543 } 544 } 545 546 if (0 != auconv_create_encodings(sc->sc_formats, AUICH_NFORMATS, 547 &sc->sc_encodings)) { 548 return; 549 } 550 551 /* Watch for power change */ 552 sc->sc_suspend = PWR_RESUME; 553 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 554 555 config_interrupts(self, auich_finish_attach); 556 557 /* sysctl setup */ 558 if (AC97_IS_FIXED_RATE(sc->codec_if)) 559 return; 560 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 561 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 562 CTL_HW, CTL_EOL); 563 if (err != 0) 564 goto sysctl_err; 565 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 566 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 567 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 568 if (err != 0) 569 goto sysctl_err; 570 node_mib = node->sysctl_num; 571 /* passing the sc address instead of &sc->sc_ac97_clock */ 572 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 573 CTLTYPE_INT, "ac97rate", 574 SYSCTL_DESCR("AC'97 codec link rate"), 575 auich_sysctl_verify, 0, sc, 0, 576 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 577 if (err != 0) 578 goto sysctl_err; 579 sc->sc_ac97_clock_mib = node->sysctl_num; 580 581 return; 582 583 sysctl_err: 584 printf("%s: failed to add sysctl nodes. (%d)\n", 585 sc->sc_dev.dv_xname, err); 586 return; /* failure of sysctl is not fatal. */ 587 } 588 589 static int 590 auich_activate(struct device *self, enum devact act) 591 { 592 struct auich_softc *sc; 593 int ret; 594 595 sc = (struct auich_softc *)self; 596 ret = 0; 597 switch (act) { 598 case DVACT_ACTIVATE: 599 return EOPNOTSUPP; 600 case DVACT_DEACTIVATE: 601 if (sc->sc_audiodev != NULL) 602 ret = config_deactivate(sc->sc_audiodev); 603 return ret; 604 } 605 return EOPNOTSUPP; 606 } 607 608 static int 609 auich_detach(struct device *self, int flags) 610 { 611 struct auich_softc *sc; 612 613 sc = (struct auich_softc *)self; 614 615 /* audio */ 616 if (sc->sc_audiodev != NULL) 617 config_detach(sc->sc_audiodev, flags); 618 619 /* sysctl */ 620 sysctl_teardown(&sc->sc_log); 621 622 /* audio_encoding_set */ 623 auconv_delete_encodings(sc->sc_encodings); 624 625 /* ac97 */ 626 if (sc->codec_if != NULL) 627 sc->codec_if->vtbl->detach(sc->codec_if); 628 629 /* PCI */ 630 if (sc->sc_ih != NULL) 631 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 632 if (sc->mix_size != 0) 633 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 634 if (sc->aud_size != 0) 635 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 636 return 0; 637 } 638 639 static int 640 auich_sysctl_verify(SYSCTLFN_ARGS) 641 { 642 int error, tmp; 643 struct sysctlnode node; 644 struct auich_softc *sc; 645 646 node = *rnode; 647 sc = rnode->sysctl_data; 648 tmp = sc->sc_ac97_clock; 649 node.sysctl_data = &tmp; 650 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 651 if (error || newp == NULL) 652 return error; 653 654 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 655 if (tmp < 48000 || tmp > 96000) 656 return EINVAL; 657 sc->sc_ac97_clock = tmp; 658 } 659 660 return 0; 661 } 662 663 static void 664 auich_finish_attach(struct device *self) 665 { 666 struct auich_softc *sc; 667 668 sc = (void *)self; 669 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 670 auich_calibrate(sc); 671 672 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 673 } 674 675 #define ICH_CODECIO_INTERVAL 10 676 static int 677 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 678 { 679 struct auich_softc *sc; 680 int i; 681 uint32_t status; 682 683 sc = v; 684 /* wait for an access semaphore */ 685 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 686 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 687 DELAY(ICH_CODECIO_INTERVAL)); 688 689 if (i > 0) { 690 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 691 DPRINTF(ICH_DEBUG_CODECIO, 692 ("auich_read_codec(%x, %x)\n", reg, *val)); 693 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 694 if (status & ICH_RCS) { 695 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 696 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 697 *val = 0xffff; 698 DPRINTF(ICH_DEBUG_CODECIO, 699 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 700 return -1; 701 } 702 return 0; 703 } else { 704 DPRINTF(ICH_DEBUG_CODECIO, 705 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 706 return -1; 707 } 708 } 709 710 static int 711 auich_write_codec(void *v, uint8_t reg, uint16_t val) 712 { 713 struct auich_softc *sc; 714 int i; 715 716 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 717 sc = v; 718 /* wait for an access semaphore */ 719 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 720 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 721 DELAY(ICH_CODECIO_INTERVAL)); 722 723 if (i > 0) { 724 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 725 return 0; 726 } else { 727 DPRINTF(ICH_DEBUG_CODECIO, 728 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 729 return -1; 730 } 731 } 732 733 static int 734 auich_attach_codec(void *v, struct ac97_codec_if *cif) 735 { 736 struct auich_softc *sc; 737 738 sc = v; 739 sc->codec_if = cif; 740 return 0; 741 } 742 743 static int 744 auich_reset_codec(void *v) 745 { 746 struct auich_softc *sc; 747 int i; 748 uint32_t control, status; 749 750 sc = v; 751 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 752 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 753 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 754 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 755 756 for (i = 500000; i >= 0; i--) { 757 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 758 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 759 break; 760 DELAY(1); 761 } 762 if (i <= 0) { 763 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 764 return ETIMEDOUT; 765 } 766 #ifdef DEBUG 767 if (status & ICH_SCR) 768 printf("%s: The 2nd codec is ready.\n", 769 sc->sc_dev.dv_xname); 770 if (status & ICH_S2CR) 771 printf("%s: The 3rd codec is ready.\n", 772 sc->sc_dev.dv_xname); 773 #endif 774 return 0; 775 } 776 777 static int 778 auich_query_encoding(void *v, struct audio_encoding *aep) 779 { 780 struct auich_softc *sc; 781 782 sc = (struct auich_softc *)v; 783 return auconv_query_encoding(sc->sc_encodings, aep); 784 } 785 786 static int 787 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 788 { 789 int ret; 790 u_int ratetmp; 791 792 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 793 ratetmp = srate; 794 if (mode == AUMODE_RECORD) 795 return sc->codec_if->vtbl->set_rate(sc->codec_if, 796 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 797 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 798 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 799 if (ret) 800 return ret; 801 ratetmp = srate; 802 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 803 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 804 if (ret) 805 return ret; 806 ratetmp = srate; 807 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 808 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 809 return ret; 810 } 811 812 static int 813 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 814 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 815 { 816 struct auich_softc *sc; 817 audio_params_t *p; 818 stream_filter_list_t *fil; 819 int mode, index; 820 uint32_t control; 821 822 sc = v; 823 for (mode = AUMODE_RECORD; mode != -1; 824 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 825 if ((setmode & mode) == 0) 826 continue; 827 828 p = mode == AUMODE_PLAY ? play : rec; 829 fil = mode == AUMODE_PLAY ? pfil : rfil; 830 if (p == NULL) 831 continue; 832 833 if (p->sample_rate < 8000 || 834 p->sample_rate > 48000) 835 return EINVAL; 836 837 index = auconv_set_converter(sc->sc_formats, AUICH_NFORMATS, 838 mode, p, TRUE, fil); 839 if (index < 0) 840 return EINVAL; 841 if (fil->req_size > 0) 842 p = &fil->filters[0].param; 843 /* p represents HW encoding */ 844 if (sc->sc_formats[index].frequency_type != 1 845 && auich_set_rate(sc, mode, p->sample_rate)) 846 return EINVAL; 847 if (mode == AUMODE_PLAY) { 848 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 849 control &= ~ICH_PCM246_MASK; 850 if (p->channels == 4) { 851 control |= ICH_PCM4; 852 } else if (p->channels == 6) { 853 control |= ICH_PCM6; 854 } 855 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 856 } 857 } 858 859 return 0; 860 } 861 862 static int 863 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 864 { 865 866 return blk & ~0x3f; /* keep good alignment */ 867 } 868 869 static int 870 auich_halt_output(void *v) 871 { 872 struct auich_softc *sc; 873 874 sc = v; 875 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 876 877 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 878 sc->pcmo.intr = NULL; 879 880 return 0; 881 } 882 883 static int 884 auich_halt_input(void *v) 885 { 886 struct auich_softc *sc; 887 888 sc = v; 889 DPRINTF(ICH_DEBUG_DMA, 890 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 891 892 /* XXX halt both unless known otherwise */ 893 894 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 895 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 896 sc->pcmi.intr = NULL; 897 898 return 0; 899 } 900 901 static int 902 auich_getdev(void *v, struct audio_device *adp) 903 { 904 struct auich_softc *sc; 905 906 sc = v; 907 *adp = sc->sc_audev; 908 return 0; 909 } 910 911 static int 912 auich_set_port(void *v, mixer_ctrl_t *cp) 913 { 914 struct auich_softc *sc; 915 916 sc = v; 917 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 918 } 919 920 static int 921 auich_get_port(void *v, mixer_ctrl_t *cp) 922 { 923 struct auich_softc *sc; 924 925 sc = v; 926 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 927 } 928 929 static int 930 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 931 { 932 struct auich_softc *sc; 933 934 sc = v; 935 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 936 } 937 938 static void * 939 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 940 int flags) 941 { 942 struct auich_softc *sc; 943 struct auich_dma *p; 944 int error; 945 946 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 947 return NULL; 948 949 p = malloc(sizeof(*p), pool, flags|M_ZERO); 950 if (p == NULL) 951 return NULL; 952 953 sc = v; 954 error = auich_allocmem(sc, size, 0, p); 955 if (error) { 956 free(p, pool); 957 return NULL; 958 } 959 960 p->next = sc->sc_dmas; 961 sc->sc_dmas = p; 962 963 return KERNADDR(p); 964 } 965 966 static void 967 auich_freem(void *v, void *ptr, struct malloc_type *pool) 968 { 969 struct auich_softc *sc; 970 struct auich_dma *p, **pp; 971 972 sc = v; 973 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 974 if (KERNADDR(p) == ptr) { 975 auich_freemem(sc, p); 976 *pp = p->next; 977 free(p, pool); 978 return; 979 } 980 } 981 } 982 983 static size_t 984 auich_round_buffersize(void *v, int direction, size_t size) 985 { 986 987 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 988 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 989 990 return size; 991 } 992 993 static paddr_t 994 auich_mappage(void *v, void *mem, off_t off, int prot) 995 { 996 struct auich_softc *sc; 997 struct auich_dma *p; 998 999 if (off < 0) 1000 return -1; 1001 sc = v; 1002 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1003 continue; 1004 if (!p) 1005 return -1; 1006 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1007 off, prot, BUS_DMA_WAITOK); 1008 } 1009 1010 static int 1011 auich_get_props(void *v) 1012 { 1013 struct auich_softc *sc; 1014 int props; 1015 1016 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1017 sc = v; 1018 /* 1019 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1020 * rate because of aurateconv. Applications can't know what rate the 1021 * device can process in the case of mmap(). 1022 */ 1023 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 1024 props |= AUDIO_PROP_MMAP; 1025 return props; 1026 } 1027 1028 static int 1029 auich_intr(void *v) 1030 { 1031 struct auich_softc *sc; 1032 int ret, gsts; 1033 #ifdef DIAGNOSTIC 1034 int csts; 1035 #endif 1036 1037 sc = v; 1038 ret = 0; 1039 #ifdef DIAGNOSTIC 1040 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1041 if (csts & PCI_STATUS_MASTER_ABORT) { 1042 printf("auich_intr: PCI master abort\n"); 1043 } 1044 #endif 1045 1046 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 1047 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1048 1049 if (gsts & ICH_POINT) { 1050 int sts; 1051 1052 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1053 ICH_PCMO + sc->sc_sts_reg); 1054 DPRINTF(ICH_DEBUG_INTR, 1055 ("auich_intr: osts=0x%x\n", sts)); 1056 1057 if (sts & ICH_FIFOE) 1058 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1059 1060 if (sts & ICH_BCIS) { 1061 struct auich_dmalist *q; 1062 int blksize, qptr, i; 1063 1064 blksize = sc->pcmo.blksize; 1065 qptr = sc->pcmo.qptr; 1066 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1067 ICH_PCMO + ICH_CIV); 1068 1069 while (qptr != i) { 1070 q = &sc->pcmo.dmalist[qptr]; 1071 1072 q->base = sc->pcmo.p; 1073 q->len = (blksize >> sc->sc_sample_shift) | 1074 ICH_DMAF_IOC; 1075 DPRINTF(ICH_DEBUG_INTR, 1076 ("auich_intr: %p, %p = %x @ 0x%x\n", 1077 &sc->pcmo.dmalist[i], q, q->len, q->base)); 1078 1079 sc->pcmo.p += blksize; 1080 if (sc->pcmo.p >= sc->pcmo.end) 1081 sc->pcmo.p = sc->pcmo.start; 1082 1083 qptr = (qptr + 1) & ICH_LVI_MASK; 1084 if (sc->pcmo.intr) 1085 sc->pcmo.intr(sc->pcmo.arg); 1086 } 1087 1088 sc->pcmo.qptr = qptr; 1089 bus_space_write_1(sc->iot, sc->aud_ioh, 1090 ICH_PCMO + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1091 } 1092 1093 /* int ack */ 1094 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1095 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1096 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1097 ret++; 1098 } 1099 1100 if (gsts & ICH_PIINT) { 1101 int sts; 1102 1103 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1104 ICH_PCMI + sc->sc_sts_reg); 1105 DPRINTF(ICH_DEBUG_INTR, 1106 ("auich_intr: ists=0x%x\n", sts)); 1107 1108 if (sts & ICH_FIFOE) 1109 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1110 1111 if (sts & ICH_BCIS) { 1112 struct auich_dmalist *q; 1113 int blksize, qptr, i; 1114 1115 blksize = sc->pcmi.blksize; 1116 qptr = sc->pcmi.qptr; 1117 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1118 ICH_PCMI + ICH_CIV); 1119 1120 while (qptr != i) { 1121 q = &sc->pcmi.dmalist[qptr]; 1122 1123 q->base = sc->pcmi.p; 1124 q->len = (blksize >> sc->sc_sample_shift) | 1125 ICH_DMAF_IOC; 1126 DPRINTF(ICH_DEBUG_INTR, 1127 ("auich_intr: %p, %p = %x @ 0x%x\n", 1128 &sc->pcmi.dmalist[i], q, q->len, q->base)); 1129 1130 sc->pcmi.p += blksize; 1131 if (sc->pcmi.p >= sc->pcmi.end) 1132 sc->pcmi.p = sc->pcmi.start; 1133 1134 qptr = (qptr + 1) & ICH_LVI_MASK; 1135 if (sc->pcmi.intr) 1136 sc->pcmi.intr(sc->pcmi.arg); 1137 } 1138 1139 sc->pcmi.qptr = qptr; 1140 bus_space_write_1(sc->iot, sc->aud_ioh, 1141 ICH_PCMI + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1142 } 1143 1144 /* int ack */ 1145 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1146 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1147 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1148 ret++; 1149 } 1150 1151 if (gsts & ICH_MIINT) { 1152 int sts; 1153 1154 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1155 ICH_MICI + sc->sc_sts_reg); 1156 DPRINTF(ICH_DEBUG_INTR, 1157 ("auich_intr: ists=0x%x\n", sts)); 1158 1159 if (sts & ICH_FIFOE) 1160 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1161 1162 /* TODO mic input DMA */ 1163 1164 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1165 } 1166 1167 return ret; 1168 } 1169 1170 static int 1171 auich_trigger_output(void *v, void *start, void *end, int blksize, 1172 void (*intr)(void *), void *arg, const audio_params_t *param) 1173 { 1174 struct auich_softc *sc; 1175 struct auich_dmalist *q; 1176 struct auich_dma *p; 1177 size_t size; 1178 int qptr; 1179 #ifdef DIAGNOSTIC 1180 int csts; 1181 #endif 1182 1183 DPRINTF(ICH_DEBUG_DMA, 1184 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1185 start, end, blksize, intr, arg, param)); 1186 sc = v; 1187 sc->pcmo.intr = intr; 1188 sc->pcmo.arg = arg; 1189 #ifdef DIAGNOSTIC 1190 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1191 if (csts & PCI_STATUS_MASTER_ABORT) { 1192 printf("auich_trigger_output: PCI master abort\n"); 1193 } 1194 #endif 1195 1196 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1197 continue; 1198 if (!p) { 1199 printf("auich_trigger_output: bad addr %p\n", start); 1200 return EINVAL; 1201 } 1202 1203 size = (size_t)((caddr_t)end - (caddr_t)start); 1204 1205 /* 1206 * The logic behind this is: 1207 * setup one buffer to play, then LVI dump out the rest 1208 * to the scatter-gather chain. 1209 */ 1210 sc->pcmo.start = DMAADDR(p); 1211 sc->pcmo.p = sc->pcmo.start; 1212 sc->pcmo.end = sc->pcmo.start + size; 1213 sc->pcmo.blksize = blksize; 1214 1215 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1216 q = &sc->pcmo.dmalist[qptr]; 1217 1218 q->base = sc->pcmo.p; 1219 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1220 1221 sc->pcmo.p += blksize; 1222 if (sc->pcmo.p >= sc->pcmo.end) 1223 sc->pcmo.p = sc->pcmo.start; 1224 } 1225 1226 sc->pcmo.qptr = qptr = 0; 1227 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1228 (qptr - 1) & ICH_LVI_MASK); 1229 1230 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1231 sc->sc_cddma + ICH_PCMO_OFF(0)); 1232 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1233 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1234 1235 return 0; 1236 } 1237 1238 static int 1239 auich_trigger_input(void *v, void *start, void *end, int blksize, 1240 void (*intr)(void *), void *arg, const audio_params_t *param) 1241 { 1242 struct auich_softc *sc; 1243 struct auich_dmalist *q; 1244 struct auich_dma *p; 1245 size_t size; 1246 int qptr; 1247 #ifdef DIAGNOSTIC 1248 int csts; 1249 #endif 1250 1251 DPRINTF(ICH_DEBUG_DMA, 1252 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1253 start, end, blksize, intr, arg, param)); 1254 sc = v; 1255 sc->pcmi.intr = intr; 1256 sc->pcmi.arg = arg; 1257 1258 #ifdef DIAGNOSTIC 1259 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1260 if (csts & PCI_STATUS_MASTER_ABORT) { 1261 printf("auich_trigger_input: PCI master abort\n"); 1262 } 1263 #endif 1264 1265 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1266 continue; 1267 if (!p) { 1268 printf("auich_trigger_input: bad addr %p\n", start); 1269 return EINVAL; 1270 } 1271 1272 size = (size_t)((caddr_t)end - (caddr_t)start); 1273 1274 /* 1275 * The logic behind this is: 1276 * setup one buffer to play, then LVI dump out the rest 1277 * to the scatter-gather chain. 1278 */ 1279 sc->pcmi.start = DMAADDR(p); 1280 sc->pcmi.p = sc->pcmi.start; 1281 sc->pcmi.end = sc->pcmi.start + size; 1282 sc->pcmi.blksize = blksize; 1283 1284 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1285 q = &sc->pcmi.dmalist[qptr]; 1286 1287 q->base = sc->pcmi.p; 1288 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1289 1290 sc->pcmi.p += blksize; 1291 if (sc->pcmi.p >= sc->pcmi.end) 1292 sc->pcmi.p = sc->pcmi.start; 1293 } 1294 1295 sc->pcmi.qptr = qptr = 0; 1296 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1297 (qptr - 1) & ICH_LVI_MASK); 1298 1299 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1300 sc->sc_cddma + ICH_PCMI_OFF(0)); 1301 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1302 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1303 1304 return 0; 1305 } 1306 1307 static int 1308 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1309 struct auich_dma *p) 1310 { 1311 int error; 1312 1313 p->size = size; 1314 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1315 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1316 &p->nsegs, BUS_DMA_NOWAIT); 1317 if (error) 1318 return error; 1319 1320 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1321 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1322 if (error) 1323 goto free; 1324 1325 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1326 0, BUS_DMA_NOWAIT, &p->map); 1327 if (error) 1328 goto unmap; 1329 1330 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1331 BUS_DMA_NOWAIT); 1332 if (error) 1333 goto destroy; 1334 return 0; 1335 1336 destroy: 1337 bus_dmamap_destroy(sc->dmat, p->map); 1338 unmap: 1339 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1340 free: 1341 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1342 return error; 1343 } 1344 1345 static int 1346 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1347 { 1348 1349 bus_dmamap_unload(sc->dmat, p->map); 1350 bus_dmamap_destroy(sc->dmat, p->map); 1351 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1352 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1353 return 0; 1354 } 1355 1356 static int 1357 auich_alloc_cdata(struct auich_softc *sc) 1358 { 1359 bus_dma_segment_t seg; 1360 int error, rseg; 1361 1362 /* 1363 * Allocate the control data structure, and create and load the 1364 * DMA map for it. 1365 */ 1366 if ((error = bus_dmamem_alloc(sc->dmat, 1367 sizeof(struct auich_cdata), 1368 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1369 printf("%s: unable to allocate control data, error = %d\n", 1370 sc->sc_dev.dv_xname, error); 1371 goto fail_0; 1372 } 1373 1374 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1375 sizeof(struct auich_cdata), 1376 (caddr_t *) &sc->sc_cdata, 1377 sc->sc_dmamap_flags)) != 0) { 1378 printf("%s: unable to map control data, error = %d\n", 1379 sc->sc_dev.dv_xname, error); 1380 goto fail_1; 1381 } 1382 1383 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1384 sizeof(struct auich_cdata), 0, 0, 1385 &sc->sc_cddmamap)) != 0) { 1386 printf("%s: unable to create control data DMA map, " 1387 "error = %d\n", sc->sc_dev.dv_xname, error); 1388 goto fail_2; 1389 } 1390 1391 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1392 sc->sc_cdata, sizeof(struct auich_cdata), 1393 NULL, 0)) != 0) { 1394 printf("%s: unable tp load control data DMA map, " 1395 "error = %d\n", sc->sc_dev.dv_xname, error); 1396 goto fail_3; 1397 } 1398 1399 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1400 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1401 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1402 1403 return 0; 1404 1405 fail_3: 1406 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1407 fail_2: 1408 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1409 sizeof(struct auich_cdata)); 1410 fail_1: 1411 bus_dmamem_free(sc->dmat, &seg, rseg); 1412 fail_0: 1413 return error; 1414 } 1415 1416 static void 1417 auich_powerhook(int why, void *addr) 1418 { 1419 struct auich_softc *sc; 1420 1421 sc = (struct auich_softc *)addr; 1422 switch (why) { 1423 case PWR_SUSPEND: 1424 case PWR_STANDBY: 1425 /* Power down */ 1426 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1427 sc->sc_suspend = why; 1428 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1429 break; 1430 1431 case PWR_RESUME: 1432 /* Wake up */ 1433 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1434 if (sc->sc_suspend == PWR_RESUME) { 1435 printf("%s: resume without suspend.\n", 1436 sc->sc_dev.dv_xname); 1437 sc->sc_suspend = why; 1438 return; 1439 } 1440 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1441 sc->sc_suspend = why; 1442 auich_reset_codec(sc); 1443 DELAY(1000); 1444 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1445 break; 1446 1447 case PWR_SOFTSUSPEND: 1448 case PWR_SOFTSTANDBY: 1449 case PWR_SOFTRESUME: 1450 break; 1451 } 1452 } 1453 1454 /* 1455 * Calibrate card (some boards are overclocked and need scaling) 1456 */ 1457 static void 1458 auich_calibrate(struct auich_softc *sc) 1459 { 1460 struct timeval t1, t2; 1461 uint8_t ociv, nciv; 1462 uint64_t wait_us; 1463 uint32_t actual_48k_rate, bytes, ac97rate; 1464 void *temp_buffer; 1465 struct auich_dma *p; 1466 u_int rate; 1467 1468 /* 1469 * Grab audio from input for fixed interval and compare how 1470 * much we actually get with what we expect. Interval needs 1471 * to be sufficiently short that no interrupts are 1472 * generated. 1473 */ 1474 1475 /* Force the codec to a known state first. */ 1476 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1477 rate = sc->sc_ac97_clock = 48000; 1478 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1479 &rate); 1480 1481 /* Setup a buffer */ 1482 bytes = 64000; 1483 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1484 1485 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1486 continue; 1487 if (p == NULL) { 1488 printf("auich_calibrate: bad address %p\n", temp_buffer); 1489 return; 1490 } 1491 sc->pcmi.dmalist[0].base = DMAADDR(p); 1492 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1493 1494 /* 1495 * our data format is stereo, 16 bit so each sample is 4 bytes. 1496 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1497 * we're going to start recording with interrupts disabled and measure 1498 * the time taken for one block to complete. we know the block size, 1499 * we know the time in microseconds, we calculate the sample rate: 1500 * 1501 * actual_rate [bps] = bytes / (time [s] * 4) 1502 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1503 * actual_rate [Hz] = (bytes * 250000) / time [us] 1504 */ 1505 1506 /* prepare */ 1507 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1508 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1509 sc->sc_cddma + ICH_PCMI_OFF(0)); 1510 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1511 (0 - 1) & ICH_LVI_MASK); 1512 1513 /* start */ 1514 microtime(&t1); 1515 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1516 1517 /* wait */ 1518 nciv = ociv; 1519 do { 1520 microtime(&t2); 1521 if (t2.tv_sec - t1.tv_sec > 1) 1522 break; 1523 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1524 ICH_PCMI + ICH_CIV); 1525 } while (nciv == ociv); 1526 microtime(&t2); 1527 1528 /* stop */ 1529 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1530 1531 /* reset */ 1532 DELAY(100); 1533 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1534 1535 /* turn time delta into us */ 1536 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1537 1538 auich_freem(sc, temp_buffer, M_DEVBUF); 1539 1540 if (nciv == ociv) { 1541 printf("%s: ac97 link rate calibration timed out after %" 1542 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1543 return; 1544 } 1545 1546 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1547 1548 if (actual_48k_rate < 50000) 1549 ac97rate = 48000; 1550 else 1551 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1552 1553 printf("%s: measured ac97 link rate at %d Hz", 1554 sc->sc_dev.dv_xname, actual_48k_rate); 1555 if (ac97rate != actual_48k_rate) 1556 printf(", will use %d Hz", ac97rate); 1557 printf("\n"); 1558 1559 sc->sc_ac97_clock = ac97rate; 1560 } 1561
Indexes created Wed Oct 22 13:09:56 GMT 2025