auich.c revision 1.90.2.2
1 /* $NetBSD: auich.c,v 1.90.2.2 2005/12/06 22:03:08 riz Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.90.2.2 2005/12/06 22:03:08 riz Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 187 struct ac97_codec_if *codec_if; 188 struct ac97_host_if host_if; 189 190 /* DMA scatter-gather lists. */ 191 bus_dmamap_t sc_cddmamap; 192 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 193 194 struct auich_cdata *sc_cdata; 195 196 struct auich_ring { 197 int qptr; 198 struct auich_dmalist *dmalist; 199 200 uint32_t start, p, end; 201 int blksize; 202 203 void (*intr)(void *); 204 void *arg; 205 } pcmo, pcmi, mici; 206 207 struct auich_dma *sc_dmas; 208 209 /* SiS 7012 hack */ 210 int sc_sample_shift; 211 int sc_sts_reg; 212 /* 440MX workaround */ 213 int sc_dmamap_flags; 214 215 /* Power Management */ 216 void *sc_powerhook; 217 int sc_suspend; 218 struct pci_conf_state sc_pciconf; 219 220 /* sysctl */ 221 struct sysctllog *sc_log; 222 uint32_t sc_ac97_clock; 223 int sc_ac97_clock_mib; 224 225 #define AUICH_NFORMATS 3 226 struct audio_format sc_formats[AUICH_NFORMATS]; 227 struct audio_encoding_set *sc_encodings; 228 }; 229 230 /* Debug */ 231 #ifdef AUICH_DEBUG 232 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 233 int auich_debug = 0xfffe; 234 #define ICH_DEBUG_CODECIO 0x0001 235 #define ICH_DEBUG_DMA 0x0002 236 #define ICH_DEBUG_INTR 0x0004 237 #else 238 #define DPRINTF(x,y) /* nothing */ 239 #endif 240 241 static int auich_match(struct device *, struct cfdata *, void *); 242 static void auich_attach(struct device *, struct device *, void *); 243 static int auich_detach(struct device *, int); 244 static int auich_activate(struct device *, enum devact); 245 static int auich_intr(void *); 246 247 CFATTACH_DECL(auich, sizeof(struct auich_softc), 248 auich_match, auich_attach, auich_detach, auich_activate); 249 250 static int auich_query_encoding(void *, struct audio_encoding *); 251 static int auich_set_params(void *, int, int, audio_params_t *, 252 audio_params_t *, stream_filter_list_t *, 253 stream_filter_list_t *); 254 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 255 static void auich_halt_pipe(struct auich_softc *, int); 256 static int auich_halt_output(void *); 257 static int auich_halt_input(void *); 258 static int auich_getdev(void *, struct audio_device *); 259 static int auich_set_port(void *, mixer_ctrl_t *); 260 static int auich_get_port(void *, mixer_ctrl_t *); 261 static int auich_query_devinfo(void *, mixer_devinfo_t *); 262 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 263 static void auich_freem(void *, void *, struct malloc_type *); 264 static size_t auich_round_buffersize(void *, int, size_t); 265 static paddr_t auich_mappage(void *, void *, off_t, int); 266 static int auich_get_props(void *); 267 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 268 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 269 static int auich_trigger_output(void *, void *, void *, int, 270 void (*)(void *), void *, const audio_params_t *); 271 static int auich_trigger_input(void *, void *, void *, int, 272 void (*)(void *), void *, const audio_params_t *); 273 274 static int auich_alloc_cdata(struct auich_softc *); 275 276 static int auich_allocmem(struct auich_softc *, size_t, size_t, 277 struct auich_dma *); 278 static int auich_freemem(struct auich_softc *, struct auich_dma *); 279 280 static void auich_powerhook(int, void *); 281 static int auich_set_rate(struct auich_softc *, int, u_long); 282 static int auich_sysctl_verify(SYSCTLFN_ARGS); 283 static void auich_finish_attach(struct device *); 284 static void auich_calibrate(struct auich_softc *); 285 286 static int auich_attach_codec(void *, struct ac97_codec_if *); 287 static int auich_read_codec(void *, uint8_t, uint16_t *); 288 static int auich_write_codec(void *, uint8_t, uint16_t); 289 static int auich_reset_codec(void *); 290 291 const struct audio_hw_if auich_hw_if = { 292 NULL, /* open */ 293 NULL, /* close */ 294 NULL, /* drain */ 295 auich_query_encoding, 296 auich_set_params, 297 auich_round_blocksize, 298 NULL, /* commit_setting */ 299 NULL, /* init_output */ 300 NULL, /* init_input */ 301 NULL, /* start_output */ 302 NULL, /* start_input */ 303 auich_halt_output, 304 auich_halt_input, 305 NULL, /* speaker_ctl */ 306 auich_getdev, 307 NULL, /* getfd */ 308 auich_set_port, 309 auich_get_port, 310 auich_query_devinfo, 311 auich_allocm, 312 auich_freem, 313 auich_round_buffersize, 314 auich_mappage, 315 auich_get_props, 316 auich_trigger_output, 317 auich_trigger_input, 318 NULL, /* dev_ioctl */ 319 }; 320 321 #define AUICH_FORMATS_4CH 1 322 #define AUICH_FORMATS_6CH 2 323 static const struct audio_format auich_formats[AUICH_NFORMATS] = { 324 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 325 2, AUFMT_STEREO, 0, {8000, 48000}}, 326 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 327 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 328 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 329 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 330 }; 331 332 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 333 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 334 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 335 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 336 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 337 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 338 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 339 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 340 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 341 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 342 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 343 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 344 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 345 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 346 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 347 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 348 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 349 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 350 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 351 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 352 353 static const struct auich_devtype { 354 pcireg_t id; 355 const char *name; 356 const char *shortname; /* must be less than 11 characters */ 357 } auich_devices[] = { 358 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 359 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 360 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 361 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 362 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 363 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 364 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 365 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 366 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 367 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 368 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 369 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 370 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 371 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 372 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 373 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 374 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 375 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 376 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 377 { 0, NULL, NULL }, 378 }; 379 380 static const struct auich_devtype * 381 auich_lookup(struct pci_attach_args *pa) 382 { 383 const struct auich_devtype *d; 384 385 for (d = auich_devices; d->name != NULL; d++) { 386 if (pa->pa_id == d->id) 387 return d; 388 } 389 390 return NULL; 391 } 392 393 static int 394 auich_match(struct device *parent, struct cfdata *match, void *aux) 395 { 396 struct pci_attach_args *pa; 397 398 pa = aux; 399 if (auich_lookup(pa) != NULL) 400 return 1; 401 402 return 0; 403 } 404 405 static void 406 auich_attach(struct device *parent, struct device *self, void *aux) 407 { 408 struct auich_softc *sc; 409 struct pci_attach_args *pa; 410 pci_intr_handle_t ih; 411 pcireg_t v; 412 const char *intrstr; 413 const struct auich_devtype *d; 414 struct sysctlnode *node; 415 int err, node_mib, i; 416 417 sc = (struct auich_softc *)self; 418 pa = aux; 419 aprint_naive(": Audio controller\n"); 420 421 d = auich_lookup(pa); 422 if (d == NULL) 423 panic("auich_attach: impossible"); 424 425 sc->sc_pc = pa->pa_pc; 426 sc->sc_pt = pa->pa_tag; 427 428 aprint_normal(": %s\n", d->name); 429 430 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 || 431 d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB ) { 432 /* 433 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 434 */ 435 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 436 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 437 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 438 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 439 v | ICH_CFG_IOSE); 440 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 441 0, &sc->iot, &sc->mix_ioh, NULL, 442 &sc->mix_size)) { 443 aprint_error("%s: can't map codec i/o space\n", 444 sc->sc_dev.dv_xname); 445 return; 446 } 447 } 448 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 449 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 450 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 451 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 452 v | ICH_CFG_IOSE); 453 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 454 0, &sc->iot, &sc->aud_ioh, NULL, 455 &sc->aud_size)) { 456 aprint_error("%s: can't map device i/o space\n", 457 sc->sc_dev.dv_xname); 458 return; 459 } 460 } 461 } else { 462 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 463 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 464 aprint_error("%s: can't map codec i/o space\n", 465 sc->sc_dev.dv_xname); 466 return; 467 } 468 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 469 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 470 aprint_error("%s: can't map device i/o space\n", 471 sc->sc_dev.dv_xname); 472 return; 473 } 474 } 475 sc->dmat = pa->pa_dmat; 476 477 /* enable bus mastering */ 478 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 479 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 480 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 481 482 /* Map and establish the interrupt. */ 483 if (pci_intr_map(pa, &ih)) { 484 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 485 return; 486 } 487 intrstr = pci_intr_string(pa->pa_pc, ih); 488 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 489 auich_intr, sc); 490 if (sc->sc_ih == NULL) { 491 aprint_error("%s: can't establish interrupt", 492 sc->sc_dev.dv_xname); 493 if (intrstr != NULL) 494 aprint_normal(" at %s", intrstr); 495 aprint_normal("\n"); 496 return; 497 } 498 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 499 500 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 501 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 502 "0x%02x", PCI_REVISION(pa->pa_class)); 503 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 504 505 /* SiS 7012 needs special handling */ 506 if (d->id == PCIID_SIS7012) { 507 sc->sc_sts_reg = ICH_PICB; 508 sc->sc_sample_shift = 0; 509 /* Un-mute output. From Linux. */ 510 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 511 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 512 ICH_SIS_CTL_UNMUTE); 513 } else { 514 sc->sc_sts_reg = ICH_STS; 515 sc->sc_sample_shift = 1; 516 } 517 518 /* Workaround for a 440MX B-stepping erratum */ 519 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 520 if (d->id == PCIID_440MX) { 521 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 522 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 523 } 524 525 /* Set up DMA lists. */ 526 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 527 auich_alloc_cdata(sc); 528 529 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 530 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 531 532 sc->host_if.arg = sc; 533 sc->host_if.attach = auich_attach_codec; 534 sc->host_if.read = auich_read_codec; 535 sc->host_if.write = auich_write_codec; 536 sc->host_if.reset = auich_reset_codec; 537 538 if (ac97_attach(&sc->host_if, self) != 0) 539 return; 540 541 /* setup audio_format */ 542 memcpy(sc->sc_formats, auich_formats, sizeof(auich_formats)); 543 if (!AC97_IS_4CH(sc->codec_if)) 544 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_4CH]); 545 if (!AC97_IS_6CH(sc->codec_if)) 546 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_6CH]); 547 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 548 for (i = 0; i < AUICH_NFORMATS; i++) { 549 sc->sc_formats[i].frequency_type = 1; 550 sc->sc_formats[i].frequency[0] = 48000; 551 } 552 } 553 554 if (0 != auconv_create_encodings(sc->sc_formats, AUICH_NFORMATS, 555 &sc->sc_encodings)) { 556 return; 557 } 558 559 /* Watch for power change */ 560 sc->sc_suspend = PWR_RESUME; 561 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 562 563 config_interrupts(self, auich_finish_attach); 564 565 /* sysctl setup */ 566 if (AC97_IS_FIXED_RATE(sc->codec_if)) 567 return; 568 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 569 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 570 CTL_HW, CTL_EOL); 571 if (err != 0) 572 goto sysctl_err; 573 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 574 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 575 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 576 if (err != 0) 577 goto sysctl_err; 578 node_mib = node->sysctl_num; 579 /* passing the sc address instead of &sc->sc_ac97_clock */ 580 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 581 CTLTYPE_INT, "ac97rate", 582 SYSCTL_DESCR("AC'97 codec link rate"), 583 auich_sysctl_verify, 0, sc, 0, 584 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 585 if (err != 0) 586 goto sysctl_err; 587 sc->sc_ac97_clock_mib = node->sysctl_num; 588 589 return; 590 591 sysctl_err: 592 printf("%s: failed to add sysctl nodes. (%d)\n", 593 sc->sc_dev.dv_xname, err); 594 return; /* failure of sysctl is not fatal. */ 595 } 596 597 static int 598 auich_activate(struct device *self, enum devact act) 599 { 600 struct auich_softc *sc; 601 int ret; 602 603 sc = (struct auich_softc *)self; 604 ret = 0; 605 switch (act) { 606 case DVACT_ACTIVATE: 607 return EOPNOTSUPP; 608 case DVACT_DEACTIVATE: 609 if (sc->sc_audiodev != NULL) 610 ret = config_deactivate(sc->sc_audiodev); 611 return ret; 612 } 613 return EOPNOTSUPP; 614 } 615 616 static int 617 auich_detach(struct device *self, int flags) 618 { 619 struct auich_softc *sc; 620 621 sc = (struct auich_softc *)self; 622 623 /* audio */ 624 if (sc->sc_audiodev != NULL) 625 config_detach(sc->sc_audiodev, flags); 626 627 /* sysctl */ 628 sysctl_teardown(&sc->sc_log); 629 630 /* audio_encoding_set */ 631 auconv_delete_encodings(sc->sc_encodings); 632 633 /* ac97 */ 634 if (sc->codec_if != NULL) 635 sc->codec_if->vtbl->detach(sc->codec_if); 636 637 /* PCI */ 638 if (sc->sc_ih != NULL) 639 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 640 if (sc->mix_size != 0) 641 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 642 if (sc->aud_size != 0) 643 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 644 return 0; 645 } 646 647 static int 648 auich_sysctl_verify(SYSCTLFN_ARGS) 649 { 650 int error, tmp; 651 struct sysctlnode node; 652 struct auich_softc *sc; 653 654 node = *rnode; 655 sc = rnode->sysctl_data; 656 tmp = sc->sc_ac97_clock; 657 node.sysctl_data = &tmp; 658 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 659 if (error || newp == NULL) 660 return error; 661 662 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 663 if (tmp < 48000 || tmp > 96000) 664 return EINVAL; 665 sc->sc_ac97_clock = tmp; 666 } 667 668 return 0; 669 } 670 671 static void 672 auich_finish_attach(struct device *self) 673 { 674 struct auich_softc *sc; 675 676 sc = (void *)self; 677 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 678 auich_calibrate(sc); 679 680 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 681 } 682 683 #define ICH_CODECIO_INTERVAL 10 684 static int 685 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 686 { 687 struct auich_softc *sc; 688 int i; 689 uint32_t status; 690 691 sc = v; 692 /* wait for an access semaphore */ 693 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 694 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 695 DELAY(ICH_CODECIO_INTERVAL)); 696 697 if (i > 0) { 698 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 699 DPRINTF(ICH_DEBUG_CODECIO, 700 ("auich_read_codec(%x, %x)\n", reg, *val)); 701 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 702 if (status & ICH_RCS) { 703 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 704 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 705 *val = 0xffff; 706 DPRINTF(ICH_DEBUG_CODECIO, 707 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 708 return -1; 709 } 710 return 0; 711 } else { 712 DPRINTF(ICH_DEBUG_CODECIO, 713 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 714 return -1; 715 } 716 } 717 718 static int 719 auich_write_codec(void *v, uint8_t reg, uint16_t val) 720 { 721 struct auich_softc *sc; 722 int i; 723 724 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 725 sc = v; 726 /* wait for an access semaphore */ 727 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 728 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 729 DELAY(ICH_CODECIO_INTERVAL)); 730 731 if (i > 0) { 732 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 733 return 0; 734 } else { 735 DPRINTF(ICH_DEBUG_CODECIO, 736 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 737 return -1; 738 } 739 } 740 741 static int 742 auich_attach_codec(void *v, struct ac97_codec_if *cif) 743 { 744 struct auich_softc *sc; 745 746 sc = v; 747 sc->codec_if = cif; 748 return 0; 749 } 750 751 static int 752 auich_reset_codec(void *v) 753 { 754 struct auich_softc *sc; 755 int i; 756 uint32_t control, status; 757 758 sc = v; 759 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 760 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 761 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 762 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 763 764 for (i = 500000; i >= 0; i--) { 765 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 766 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 767 break; 768 DELAY(1); 769 } 770 if (i <= 0) { 771 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 772 return ETIMEDOUT; 773 } 774 #ifdef DEBUG 775 if (status & ICH_SCR) 776 printf("%s: The 2nd codec is ready.\n", 777 sc->sc_dev.dv_xname); 778 if (status & ICH_S2CR) 779 printf("%s: The 3rd codec is ready.\n", 780 sc->sc_dev.dv_xname); 781 #endif 782 return 0; 783 } 784 785 static int 786 auich_query_encoding(void *v, struct audio_encoding *aep) 787 { 788 struct auich_softc *sc; 789 790 sc = (struct auich_softc *)v; 791 return auconv_query_encoding(sc->sc_encodings, aep); 792 } 793 794 static int 795 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 796 { 797 int ret; 798 u_int ratetmp; 799 800 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 801 ratetmp = srate; 802 if (mode == AUMODE_RECORD) 803 return sc->codec_if->vtbl->set_rate(sc->codec_if, 804 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 805 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 806 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 807 if (ret) 808 return ret; 809 ratetmp = srate; 810 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 811 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 812 if (ret) 813 return ret; 814 ratetmp = srate; 815 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 816 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 817 return ret; 818 } 819 820 static int 821 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 822 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 823 { 824 struct auich_softc *sc; 825 audio_params_t *p; 826 stream_filter_list_t *fil; 827 int mode, index; 828 uint32_t control; 829 830 sc = v; 831 for (mode = AUMODE_RECORD; mode != -1; 832 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 833 if ((setmode & mode) == 0) 834 continue; 835 836 p = mode == AUMODE_PLAY ? play : rec; 837 fil = mode == AUMODE_PLAY ? pfil : rfil; 838 if (p == NULL) 839 continue; 840 841 if (p->sample_rate < 8000 || 842 p->sample_rate > 48000) 843 return EINVAL; 844 845 index = auconv_set_converter(sc->sc_formats, AUICH_NFORMATS, 846 mode, p, TRUE, fil); 847 if (index < 0) 848 return EINVAL; 849 if (fil->req_size > 0) 850 p = &fil->filters[0].param; 851 /* p represents HW encoding */ 852 if (sc->sc_formats[index].frequency_type != 1 853 && auich_set_rate(sc, mode, p->sample_rate)) 854 return EINVAL; 855 if (mode == AUMODE_PLAY) { 856 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 857 control &= ~ICH_PCM246_MASK; 858 if (p->channels == 4) { 859 control |= ICH_PCM4; 860 } else if (p->channels == 6) { 861 control |= ICH_PCM6; 862 } 863 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 864 } 865 } 866 867 return 0; 868 } 869 870 static int 871 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 872 { 873 874 return blk & ~0x3f; /* keep good alignment */ 875 } 876 877 static void 878 auich_halt_pipe(struct auich_softc *sc, int pipe) 879 { 880 int i; 881 uint32_t status; 882 883 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 884 for (i = 0; i < 100; i++) { 885 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 886 if (status & ICH_DCH) 887 break; 888 DELAY(1); 889 } 890 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 891 892 #if AUICH_DEBUG 893 if (i > 0) 894 printf("auich_halt_pipe: halt took %d cycles\n", i); 895 #endif 896 } 897 898 static int 899 auich_halt_output(void *v) 900 { 901 struct auich_softc *sc; 902 903 sc = v; 904 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 905 906 auich_halt_pipe(sc, ICH_PCMO); 907 sc->pcmo.intr = NULL; 908 909 return 0; 910 } 911 912 static int 913 auich_halt_input(void *v) 914 { 915 struct auich_softc *sc; 916 917 sc = v; 918 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 919 920 auich_halt_pipe(sc, ICH_PCMI); 921 sc->pcmi.intr = NULL; 922 923 return 0; 924 } 925 926 static int 927 auich_getdev(void *v, struct audio_device *adp) 928 { 929 struct auich_softc *sc; 930 931 sc = v; 932 *adp = sc->sc_audev; 933 return 0; 934 } 935 936 static int 937 auich_set_port(void *v, mixer_ctrl_t *cp) 938 { 939 struct auich_softc *sc; 940 941 sc = v; 942 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 943 } 944 945 static int 946 auich_get_port(void *v, mixer_ctrl_t *cp) 947 { 948 struct auich_softc *sc; 949 950 sc = v; 951 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 952 } 953 954 static int 955 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 956 { 957 struct auich_softc *sc; 958 959 sc = v; 960 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 961 } 962 963 static void * 964 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 965 int flags) 966 { 967 struct auich_softc *sc; 968 struct auich_dma *p; 969 int error; 970 971 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 972 return NULL; 973 974 p = malloc(sizeof(*p), pool, flags|M_ZERO); 975 if (p == NULL) 976 return NULL; 977 978 sc = v; 979 error = auich_allocmem(sc, size, 0, p); 980 if (error) { 981 free(p, pool); 982 return NULL; 983 } 984 985 p->next = sc->sc_dmas; 986 sc->sc_dmas = p; 987 988 return KERNADDR(p); 989 } 990 991 static void 992 auich_freem(void *v, void *ptr, struct malloc_type *pool) 993 { 994 struct auich_softc *sc; 995 struct auich_dma *p, **pp; 996 997 sc = v; 998 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 999 if (KERNADDR(p) == ptr) { 1000 auich_freemem(sc, p); 1001 *pp = p->next; 1002 free(p, pool); 1003 return; 1004 } 1005 } 1006 } 1007 1008 static size_t 1009 auich_round_buffersize(void *v, int direction, size_t size) 1010 { 1011 1012 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1013 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1014 1015 return size; 1016 } 1017 1018 static paddr_t 1019 auich_mappage(void *v, void *mem, off_t off, int prot) 1020 { 1021 struct auich_softc *sc; 1022 struct auich_dma *p; 1023 1024 if (off < 0) 1025 return -1; 1026 sc = v; 1027 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1028 continue; 1029 if (!p) 1030 return -1; 1031 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1032 off, prot, BUS_DMA_WAITOK); 1033 } 1034 1035 static int 1036 auich_get_props(void *v) 1037 { 1038 struct auich_softc *sc; 1039 int props; 1040 1041 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1042 sc = v; 1043 /* 1044 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1045 * rate because of aurateconv. Applications can't know what rate the 1046 * device can process in the case of mmap(). 1047 */ 1048 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 1049 props |= AUDIO_PROP_MMAP; 1050 return props; 1051 } 1052 1053 static int 1054 auich_intr(void *v) 1055 { 1056 struct auich_softc *sc; 1057 int ret, gsts; 1058 #ifdef DIAGNOSTIC 1059 int csts; 1060 #endif 1061 1062 sc = v; 1063 ret = 0; 1064 #ifdef DIAGNOSTIC 1065 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1066 if (csts & PCI_STATUS_MASTER_ABORT) { 1067 printf("auich_intr: PCI master abort\n"); 1068 } 1069 #endif 1070 1071 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 1072 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1073 1074 if (gsts & ICH_POINT) { 1075 int sts; 1076 1077 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1078 ICH_PCMO + sc->sc_sts_reg); 1079 DPRINTF(ICH_DEBUG_INTR, 1080 ("auich_intr: osts=0x%x\n", sts)); 1081 1082 if (sts & ICH_FIFOE) 1083 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1084 1085 if (sts & ICH_BCIS) 1086 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1087 1088 /* int ack */ 1089 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1090 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1091 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1092 ret++; 1093 } 1094 1095 if (gsts & ICH_PIINT) { 1096 int sts; 1097 1098 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1099 ICH_PCMI + sc->sc_sts_reg); 1100 DPRINTF(ICH_DEBUG_INTR, 1101 ("auich_intr: ists=0x%x\n", sts)); 1102 1103 if (sts & ICH_FIFOE) 1104 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1105 1106 if (sts & ICH_BCIS) 1107 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1108 1109 /* int ack */ 1110 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1111 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1112 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1113 ret++; 1114 } 1115 1116 if (gsts & ICH_MINT) { 1117 int sts; 1118 1119 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1120 ICH_MICI + sc->sc_sts_reg); 1121 DPRINTF(ICH_DEBUG_INTR, 1122 ("auich_intr: ists=0x%x\n", sts)); 1123 1124 if (sts & ICH_FIFOE) 1125 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1126 1127 if (sts & ICH_BCIS) 1128 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1129 1130 /* int ack */ 1131 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1132 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1133 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MINT); 1134 ret++; 1135 } 1136 1137 return ret; 1138 } 1139 1140 static void 1141 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1142 { 1143 int blksize, qptr; 1144 struct auich_dmalist *q; 1145 1146 blksize = ring->blksize; 1147 1148 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1149 q = &ring->dmalist[qptr]; 1150 q->base = ring->p; 1151 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1152 1153 ring->p += blksize; 1154 if (ring->p >= ring->end) 1155 ring->p = ring->start; 1156 } 1157 ring->qptr = 0; 1158 1159 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1160 (qptr - 1) & ICH_LVI_MASK); 1161 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1162 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1163 } 1164 1165 static void 1166 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1167 { 1168 int blksize, qptr, nqptr; 1169 struct auich_dmalist *q; 1170 1171 blksize = ring->blksize; 1172 qptr = ring->qptr; 1173 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1174 1175 while (qptr != nqptr) { 1176 q = &ring->dmalist[qptr]; 1177 q->base = ring->p; 1178 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1179 1180 DPRINTF(ICH_DEBUG_INTR, 1181 ("auich_intr: %p, %p = %x @ 0x%x\n", 1182 &ring->dmalist[qptr], q, q->len, q->base)); 1183 1184 ring->p += blksize; 1185 if (ring->p >= ring->end) 1186 ring->p = ring->start; 1187 1188 qptr = (qptr + 1) & ICH_LVI_MASK; 1189 if (ring->intr) 1190 ring->intr(ring->arg); 1191 } 1192 ring->qptr = qptr; 1193 1194 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1195 (qptr - 1) & ICH_LVI_MASK); 1196 } 1197 1198 static int 1199 auich_trigger_output(void *v, void *start, void *end, int blksize, 1200 void (*intr)(void *), void *arg, const audio_params_t *param) 1201 { 1202 struct auich_softc *sc; 1203 struct auich_dma *p; 1204 size_t size; 1205 1206 DPRINTF(ICH_DEBUG_DMA, 1207 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1208 start, end, blksize, intr, arg, param)); 1209 sc = v; 1210 1211 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1212 continue; 1213 if (!p) { 1214 printf("auich_trigger_output: bad addr %p\n", start); 1215 return EINVAL; 1216 } 1217 1218 size = (size_t)((caddr_t)end - (caddr_t)start); 1219 1220 sc->pcmo.intr = intr; 1221 sc->pcmo.arg = arg; 1222 sc->pcmo.start = DMAADDR(p); 1223 sc->pcmo.p = sc->pcmo.start; 1224 sc->pcmo.end = sc->pcmo.start + size; 1225 sc->pcmo.blksize = blksize; 1226 1227 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1228 sc->sc_cddma + ICH_PCMO_OFF(0)); 1229 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1230 1231 return 0; 1232 } 1233 1234 static int 1235 auich_trigger_input(void *v, void *start, void *end, int blksize, 1236 void (*intr)(void *), void *arg, const audio_params_t *param) 1237 { 1238 struct auich_softc *sc; 1239 struct auich_dma *p; 1240 size_t size; 1241 1242 DPRINTF(ICH_DEBUG_DMA, 1243 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1244 start, end, blksize, intr, arg, param)); 1245 sc = v; 1246 1247 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1248 continue; 1249 if (!p) { 1250 printf("auich_trigger_input: bad addr %p\n", start); 1251 return EINVAL; 1252 } 1253 1254 size = (size_t)((caddr_t)end - (caddr_t)start); 1255 1256 sc->pcmi.intr = intr; 1257 sc->pcmi.arg = arg; 1258 sc->pcmi.start = DMAADDR(p); 1259 sc->pcmi.p = sc->pcmi.start; 1260 sc->pcmi.end = sc->pcmi.start + size; 1261 sc->pcmi.blksize = blksize; 1262 1263 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1264 sc->sc_cddma + ICH_PCMI_OFF(0)); 1265 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1266 1267 return 0; 1268 } 1269 1270 static int 1271 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1272 struct auich_dma *p) 1273 { 1274 int error; 1275 1276 p->size = size; 1277 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1278 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1279 &p->nsegs, BUS_DMA_NOWAIT); 1280 if (error) 1281 return error; 1282 1283 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1284 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1285 if (error) 1286 goto free; 1287 1288 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1289 0, BUS_DMA_NOWAIT, &p->map); 1290 if (error) 1291 goto unmap; 1292 1293 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1294 BUS_DMA_NOWAIT); 1295 if (error) 1296 goto destroy; 1297 return 0; 1298 1299 destroy: 1300 bus_dmamap_destroy(sc->dmat, p->map); 1301 unmap: 1302 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1303 free: 1304 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1305 return error; 1306 } 1307 1308 static int 1309 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1310 { 1311 1312 bus_dmamap_unload(sc->dmat, p->map); 1313 bus_dmamap_destroy(sc->dmat, p->map); 1314 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1315 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1316 return 0; 1317 } 1318 1319 static int 1320 auich_alloc_cdata(struct auich_softc *sc) 1321 { 1322 bus_dma_segment_t seg; 1323 int error, rseg; 1324 1325 /* 1326 * Allocate the control data structure, and create and load the 1327 * DMA map for it. 1328 */ 1329 if ((error = bus_dmamem_alloc(sc->dmat, 1330 sizeof(struct auich_cdata), 1331 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1332 printf("%s: unable to allocate control data, error = %d\n", 1333 sc->sc_dev.dv_xname, error); 1334 goto fail_0; 1335 } 1336 1337 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1338 sizeof(struct auich_cdata), 1339 (caddr_t *) &sc->sc_cdata, 1340 sc->sc_dmamap_flags)) != 0) { 1341 printf("%s: unable to map control data, error = %d\n", 1342 sc->sc_dev.dv_xname, error); 1343 goto fail_1; 1344 } 1345 1346 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1347 sizeof(struct auich_cdata), 0, 0, 1348 &sc->sc_cddmamap)) != 0) { 1349 printf("%s: unable to create control data DMA map, " 1350 "error = %d\n", sc->sc_dev.dv_xname, error); 1351 goto fail_2; 1352 } 1353 1354 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1355 sc->sc_cdata, sizeof(struct auich_cdata), 1356 NULL, 0)) != 0) { 1357 printf("%s: unable tp load control data DMA map, " 1358 "error = %d\n", sc->sc_dev.dv_xname, error); 1359 goto fail_3; 1360 } 1361 1362 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1363 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1364 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1365 1366 return 0; 1367 1368 fail_3: 1369 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1370 fail_2: 1371 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1372 sizeof(struct auich_cdata)); 1373 fail_1: 1374 bus_dmamem_free(sc->dmat, &seg, rseg); 1375 fail_0: 1376 return error; 1377 } 1378 1379 static void 1380 auich_powerhook(int why, void *addr) 1381 { 1382 struct auich_softc *sc; 1383 1384 sc = (struct auich_softc *)addr; 1385 switch (why) { 1386 case PWR_SUSPEND: 1387 case PWR_STANDBY: 1388 /* Power down */ 1389 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1390 sc->sc_suspend = why; 1391 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1392 break; 1393 1394 case PWR_RESUME: 1395 /* Wake up */ 1396 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1397 if (sc->sc_suspend == PWR_RESUME) { 1398 printf("%s: resume without suspend.\n", 1399 sc->sc_dev.dv_xname); 1400 sc->sc_suspend = why; 1401 return; 1402 } 1403 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1404 sc->sc_suspend = why; 1405 auich_reset_codec(sc); 1406 DELAY(1000); 1407 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1408 break; 1409 1410 case PWR_SOFTSUSPEND: 1411 case PWR_SOFTSTANDBY: 1412 case PWR_SOFTRESUME: 1413 break; 1414 } 1415 } 1416 1417 /* 1418 * Calibrate card (some boards are overclocked and need scaling) 1419 */ 1420 static void 1421 auich_calibrate(struct auich_softc *sc) 1422 { 1423 struct timeval t1, t2; 1424 uint8_t ociv, nciv; 1425 uint64_t wait_us; 1426 uint32_t actual_48k_rate, bytes, ac97rate; 1427 void *temp_buffer; 1428 struct auich_dma *p; 1429 u_int rate; 1430 1431 /* 1432 * Grab audio from input for fixed interval and compare how 1433 * much we actually get with what we expect. Interval needs 1434 * to be sufficiently short that no interrupts are 1435 * generated. 1436 */ 1437 1438 /* Force the codec to a known state first. */ 1439 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1440 rate = sc->sc_ac97_clock = 48000; 1441 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1442 &rate); 1443 1444 /* Setup a buffer */ 1445 bytes = 64000; 1446 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1447 1448 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1449 continue; 1450 if (p == NULL) { 1451 printf("auich_calibrate: bad address %p\n", temp_buffer); 1452 return; 1453 } 1454 sc->pcmi.dmalist[0].base = DMAADDR(p); 1455 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1456 1457 /* 1458 * our data format is stereo, 16 bit so each sample is 4 bytes. 1459 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1460 * we're going to start recording with interrupts disabled and measure 1461 * the time taken for one block to complete. we know the block size, 1462 * we know the time in microseconds, we calculate the sample rate: 1463 * 1464 * actual_rate [bps] = bytes / (time [s] * 4) 1465 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1466 * actual_rate [Hz] = (bytes * 250000) / time [us] 1467 */ 1468 1469 /* prepare */ 1470 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1471 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1472 sc->sc_cddma + ICH_PCMI_OFF(0)); 1473 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1474 (0 - 1) & ICH_LVI_MASK); 1475 1476 /* start */ 1477 microtime(&t1); 1478 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1479 1480 /* wait */ 1481 nciv = ociv; 1482 do { 1483 microtime(&t2); 1484 if (t2.tv_sec - t1.tv_sec > 1) 1485 break; 1486 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1487 ICH_PCMI + ICH_CIV); 1488 } while (nciv == ociv); 1489 microtime(&t2); 1490 1491 /* stop */ 1492 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1493 1494 /* reset */ 1495 DELAY(100); 1496 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1497 1498 /* turn time delta into us */ 1499 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1500 1501 auich_freem(sc, temp_buffer, M_DEVBUF); 1502 1503 if (nciv == ociv) { 1504 printf("%s: ac97 link rate calibration timed out after %" 1505 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1506 return; 1507 } 1508 1509 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1510 1511 if (actual_48k_rate < 50000) 1512 ac97rate = 48000; 1513 else 1514 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1515 1516 printf("%s: measured ac97 link rate at %d Hz", 1517 sc->sc_dev.dv_xname, actual_48k_rate); 1518 if (ac97rate != actual_48k_rate) 1519 printf(", will use %d Hz", ac97rate); 1520 printf("\n"); 1521 1522 sc->sc_ac97_clock = ac97rate; 1523 } 1524
Indexes created Thu Oct 23 18:09:57 GMT 2025