auich.c revision 1.92
1 /* $NetBSD: auich.c,v 1.92 2005/04/07 23:21:10 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.92 2005/04/07 23:21:10 jmcneill Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 187 struct ac97_codec_if *codec_if; 188 struct ac97_host_if host_if; 189 int codecnum; 190 191 /* DMA scatter-gather lists. */ 192 bus_dmamap_t sc_cddmamap; 193 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 194 195 struct auich_cdata *sc_cdata; 196 197 struct auich_ring { 198 int qptr; 199 struct auich_dmalist *dmalist; 200 201 uint32_t start, p, end; 202 int blksize; 203 204 void (*intr)(void *); 205 void *arg; 206 } pcmo, pcmi, mici; 207 208 struct auich_dma *sc_dmas; 209 210 /* SiS 7012 hack */ 211 int sc_sample_shift; 212 int sc_sts_reg; 213 /* 440MX workaround */ 214 int sc_dmamap_flags; 215 216 /* Power Management */ 217 void *sc_powerhook; 218 int sc_suspend; 219 struct pci_conf_state sc_pciconf; 220 221 /* sysctl */ 222 struct sysctllog *sc_log; 223 uint32_t sc_ac97_clock; 224 int sc_ac97_clock_mib; 225 226 int sc_modem_offset; 227 228 #define AUICH_AUDIO_NFORMATS 3 229 #define AUICH_MODEM_NFORMATS 1 230 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 231 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 232 struct audio_encoding_set *sc_encodings; 233 }; 234 235 /* Debug */ 236 #ifdef AUICH_DEBUG 237 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 238 int auich_debug = 0xfffe; 239 #define ICH_DEBUG_CODECIO 0x0001 240 #define ICH_DEBUG_DMA 0x0002 241 #define ICH_DEBUG_INTR 0x0004 242 #else 243 #define DPRINTF(x,y) /* nothing */ 244 #endif 245 246 static int auich_match(struct device *, struct cfdata *, void *); 247 static void auich_attach(struct device *, struct device *, void *); 248 static int auich_detach(struct device *, int); 249 static int auich_activate(struct device *, enum devact); 250 static int auich_intr(void *); 251 252 CFATTACH_DECL(auich, sizeof(struct auich_softc), 253 auich_match, auich_attach, auich_detach, auich_activate); 254 255 static int auich_query_encoding(void *, struct audio_encoding *); 256 static int auich_set_params(void *, int, int, audio_params_t *, 257 audio_params_t *, stream_filter_list_t *, 258 stream_filter_list_t *); 259 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 260 static void auich_halt_pipe(struct auich_softc *, int); 261 static int auich_halt_output(void *); 262 static int auich_halt_input(void *); 263 static int auich_getdev(void *, struct audio_device *); 264 static int auich_set_port(void *, mixer_ctrl_t *); 265 static int auich_get_port(void *, mixer_ctrl_t *); 266 static int auich_query_devinfo(void *, mixer_devinfo_t *); 267 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 268 static void auich_freem(void *, void *, struct malloc_type *); 269 static size_t auich_round_buffersize(void *, int, size_t); 270 static paddr_t auich_mappage(void *, void *, off_t, int); 271 static int auich_get_props(void *); 272 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 273 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 274 static int auich_trigger_output(void *, void *, void *, int, 275 void (*)(void *), void *, const audio_params_t *); 276 static int auich_trigger_input(void *, void *, void *, int, 277 void (*)(void *), void *, const audio_params_t *); 278 279 static int auich_alloc_cdata(struct auich_softc *); 280 281 static int auich_allocmem(struct auich_softc *, size_t, size_t, 282 struct auich_dma *); 283 static int auich_freemem(struct auich_softc *, struct auich_dma *); 284 285 static void auich_powerhook(int, void *); 286 static int auich_set_rate(struct auich_softc *, int, u_long); 287 static int auich_sysctl_verify(SYSCTLFN_ARGS); 288 static void auich_finish_attach(struct device *); 289 static void auich_calibrate(struct auich_softc *); 290 291 static int auich_attach_codec(void *, struct ac97_codec_if *); 292 static int auich_read_codec(void *, uint8_t, uint16_t *); 293 static int auich_write_codec(void *, uint8_t, uint16_t); 294 static int auich_reset_codec(void *); 295 static enum ac97_host_flags auich_flags_codec(void *); 296 297 const struct audio_hw_if auich_hw_if = { 298 NULL, /* open */ 299 NULL, /* close */ 300 NULL, /* drain */ 301 auich_query_encoding, 302 auich_set_params, 303 auich_round_blocksize, 304 NULL, /* commit_setting */ 305 NULL, /* init_output */ 306 NULL, /* init_input */ 307 NULL, /* start_output */ 308 NULL, /* start_input */ 309 auich_halt_output, 310 auich_halt_input, 311 NULL, /* speaker_ctl */ 312 auich_getdev, 313 NULL, /* getfd */ 314 auich_set_port, 315 auich_get_port, 316 auich_query_devinfo, 317 auich_allocm, 318 auich_freem, 319 auich_round_buffersize, 320 auich_mappage, 321 auich_get_props, 322 auich_trigger_output, 323 auich_trigger_input, 324 NULL, /* dev_ioctl */ 325 }; 326 327 #define AUICH_FORMATS_1CH 0 328 #define AUICH_FORMATS_4CH 1 329 #define AUICH_FORMATS_6CH 2 330 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 331 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 332 2, AUFMT_STEREO, 0, {8000, 48000}}, 333 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 334 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 335 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 336 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 337 }; 338 339 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 340 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 341 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 342 }; 343 344 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 345 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 346 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 347 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 348 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 349 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 350 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 351 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 352 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 353 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 354 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 355 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 356 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 357 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 358 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 359 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 360 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 361 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 362 363 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 364 365 struct auich_devtype { 366 pcireg_t id; 367 const char *name; 368 const char *shortname; /* must be less than 11 characters */ 369 }; 370 371 static const struct auich_devtype auich_audio_devices[] = { 372 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 373 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 374 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 375 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 376 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 377 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 378 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 379 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 380 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 381 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 382 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 383 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 384 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 385 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 386 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 387 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 388 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 389 { 0, NULL, NULL }, 390 }; 391 392 static const struct auich_devtype auich_modem_devices[] = { 393 #ifdef AUICH_ATTACH_MODEM 394 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 395 #endif 396 { 0, NULL, NULL }, 397 }; 398 399 static const struct auich_devtype * 400 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 401 { 402 const struct auich_devtype *d; 403 404 for (d = auich_devices; d->name != NULL; d++) { 405 if (pa->pa_id == d->id) 406 return d; 407 } 408 409 return NULL; 410 } 411 412 static int 413 auich_match(struct device *parent, struct cfdata *match, void *aux) 414 { 415 struct pci_attach_args *pa; 416 417 pa = aux; 418 if (auich_lookup(pa, auich_audio_devices) != NULL) 419 return 1; 420 if (auich_lookup(pa, auich_modem_devices) != NULL) 421 return 1; 422 423 return 0; 424 } 425 426 static void 427 auich_attach(struct device *parent, struct device *self, void *aux) 428 { 429 struct auich_softc *sc; 430 struct pci_attach_args *pa; 431 pci_intr_handle_t ih; 432 pcireg_t v; 433 const char *intrstr; 434 const struct auich_devtype *d; 435 struct sysctlnode *node, *node_ac97clock; 436 int err, node_mib, i; 437 438 sc = (struct auich_softc *)self; 439 pa = aux; 440 441 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) 442 sc->sc_modem_offset = 0x10; 443 else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) 444 sc->sc_modem_offset = 0; 445 else 446 panic("auich_attach: impossible"); 447 448 if (sc->sc_modem_offset == 0) 449 aprint_naive(": Audio controller\n"); 450 else 451 aprint_naive(": Modem controller\n"); 452 453 sc->sc_pc = pa->pa_pc; 454 sc->sc_pt = pa->pa_tag; 455 456 aprint_normal(": %s\n", d->name); 457 458 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 459 || d->id == PCIID_ICH4MODEM) { 460 /* 461 * Use native mode for ICH4/ICH5/ICH6 462 */ 463 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 464 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 465 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 466 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 467 v | ICH_CFG_IOSE); 468 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 469 0, &sc->iot, &sc->mix_ioh, NULL, 470 &sc->mix_size)) { 471 aprint_error("%s: can't map codec i/o space\n", 472 sc->sc_dev.dv_xname); 473 return; 474 } 475 } 476 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 477 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 478 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 479 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 480 v | ICH_CFG_IOSE); 481 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 482 0, &sc->iot, &sc->aud_ioh, NULL, 483 &sc->aud_size)) { 484 aprint_error("%s: can't map device i/o space\n", 485 sc->sc_dev.dv_xname); 486 return; 487 } 488 } 489 } else { 490 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 491 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 492 aprint_error("%s: can't map codec i/o space\n", 493 sc->sc_dev.dv_xname); 494 return; 495 } 496 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 497 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 498 aprint_error("%s: can't map device i/o space\n", 499 sc->sc_dev.dv_xname); 500 return; 501 } 502 } 503 sc->dmat = pa->pa_dmat; 504 505 /* enable bus mastering */ 506 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 507 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 508 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 509 510 /* Map and establish the interrupt. */ 511 if (pci_intr_map(pa, &ih)) { 512 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 513 return; 514 } 515 intrstr = pci_intr_string(pa->pa_pc, ih); 516 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 517 auich_intr, sc); 518 if (sc->sc_ih == NULL) { 519 aprint_error("%s: can't establish interrupt", 520 sc->sc_dev.dv_xname); 521 if (intrstr != NULL) 522 aprint_normal(" at %s", intrstr); 523 aprint_normal("\n"); 524 return; 525 } 526 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 527 528 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 529 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 530 "0x%02x", PCI_REVISION(pa->pa_class)); 531 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 532 533 /* SiS 7012 needs special handling */ 534 if (d->id == PCIID_SIS7012) { 535 sc->sc_sts_reg = ICH_PICB; 536 sc->sc_sample_shift = 0; 537 /* Un-mute output. From Linux. */ 538 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 539 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 540 ICH_SIS_CTL_UNMUTE); 541 } else { 542 sc->sc_sts_reg = ICH_STS; 543 sc->sc_sample_shift = 1; 544 } 545 546 /* Workaround for a 440MX B-stepping erratum */ 547 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 548 if (d->id == PCIID_440MX) { 549 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 550 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 551 } 552 553 /* Set up DMA lists. */ 554 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 555 auich_alloc_cdata(sc); 556 557 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 558 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 559 560 sc->codecnum = sc->sc_modem_offset == 0 ? 0 : 1; 561 562 sc->host_if.arg = sc; 563 sc->host_if.attach = auich_attach_codec; 564 sc->host_if.read = auich_read_codec; 565 sc->host_if.write = auich_write_codec; 566 sc->host_if.reset = auich_reset_codec; 567 sc->host_if.flags = auich_flags_codec; 568 569 if (ac97_attach(&sc->host_if, self) != 0) 570 return; 571 572 /* setup audio_format */ 573 if (sc->sc_modem_offset == 0) { 574 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 575 if (!AC97_IS_4CH(sc->codec_if)) 576 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 577 if (!AC97_IS_6CH(sc->codec_if)) 578 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 579 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 580 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 581 sc->sc_audio_formats[i].frequency_type = 1; 582 sc->sc_audio_formats[i].frequency[0] = 48000; 583 } 584 } 585 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 586 &sc->sc_encodings)) 587 return; 588 } else { 589 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 590 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 591 &sc->sc_encodings)) 592 return; 593 } 594 595 596 /* Watch for power change */ 597 sc->sc_suspend = PWR_RESUME; 598 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 599 600 config_interrupts(self, auich_finish_attach); 601 602 /* sysctl setup */ 603 if (AC97_IS_FIXED_RATE(sc->codec_if) && sc->sc_modem_offset == 0) 604 return; 605 606 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 607 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 608 CTL_HW, CTL_EOL); 609 if (err != 0) 610 goto sysctl_err; 611 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 612 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 613 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 614 if (err != 0) 615 goto sysctl_err; 616 node_mib = node->sysctl_num; 617 618 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 619 /* passing the sc address instead of &sc->sc_ac97_clock */ 620 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 621 CTLFLAG_READWRITE, 622 CTLTYPE_INT, "ac97rate", 623 SYSCTL_DESCR("AC'97 codec link rate"), 624 auich_sysctl_verify, 0, sc, 0, 625 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 626 if (err != 0) 627 goto sysctl_err; 628 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 629 } 630 631 return; 632 633 sysctl_err: 634 printf("%s: failed to add sysctl nodes. (%d)\n", 635 sc->sc_dev.dv_xname, err); 636 return; /* failure of sysctl is not fatal. */ 637 } 638 639 static int 640 auich_activate(struct device *self, enum devact act) 641 { 642 struct auich_softc *sc; 643 int ret; 644 645 sc = (struct auich_softc *)self; 646 ret = 0; 647 switch (act) { 648 case DVACT_ACTIVATE: 649 return EOPNOTSUPP; 650 case DVACT_DEACTIVATE: 651 if (sc->sc_audiodev != NULL) 652 ret = config_deactivate(sc->sc_audiodev); 653 return ret; 654 } 655 return EOPNOTSUPP; 656 } 657 658 static int 659 auich_detach(struct device *self, int flags) 660 { 661 struct auich_softc *sc; 662 663 sc = (struct auich_softc *)self; 664 665 /* audio */ 666 if (sc->sc_audiodev != NULL) 667 config_detach(sc->sc_audiodev, flags); 668 669 /* sysctl */ 670 sysctl_teardown(&sc->sc_log); 671 672 /* audio_encoding_set */ 673 auconv_delete_encodings(sc->sc_encodings); 674 675 /* ac97 */ 676 if (sc->codec_if != NULL) 677 sc->codec_if->vtbl->detach(sc->codec_if); 678 679 /* PCI */ 680 if (sc->sc_ih != NULL) 681 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 682 if (sc->mix_size != 0) 683 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 684 if (sc->aud_size != 0) 685 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 686 return 0; 687 } 688 689 static int 690 auich_sysctl_verify(SYSCTLFN_ARGS) 691 { 692 int error, tmp; 693 struct sysctlnode node; 694 struct auich_softc *sc; 695 696 node = *rnode; 697 sc = rnode->sysctl_data; 698 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 699 tmp = sc->sc_ac97_clock; 700 node.sysctl_data = &tmp; 701 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 702 if (error || newp == NULL) 703 return error; 704 705 if (tmp < 48000 || tmp > 96000) 706 return EINVAL; 707 sc->sc_ac97_clock = tmp; 708 } 709 710 return 0; 711 } 712 713 static void 714 auich_finish_attach(struct device *self) 715 { 716 struct auich_softc *sc; 717 718 sc = (void *)self; 719 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 720 auich_calibrate(sc); 721 722 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 723 } 724 725 #define ICH_CODECIO_INTERVAL 10 726 static int 727 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 728 { 729 struct auich_softc *sc; 730 int i; 731 uint32_t status; 732 733 sc = v; 734 /* wait for an access semaphore */ 735 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 736 bus_space_read_1(sc->iot, sc->aud_ioh, 737 ICH_CAS + sc->sc_modem_offset) & 1; 738 DELAY(ICH_CODECIO_INTERVAL)); 739 740 if (i > 0) { 741 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg + (sc->codecnum * 0x80)); 742 DPRINTF(ICH_DEBUG_CODECIO, 743 ("auich_read_codec(%x, %x)\n", reg, *val)); 744 status = bus_space_read_4(sc->iot, sc->aud_ioh, 745 ICH_GSTS + sc->sc_modem_offset); 746 if (status & ICH_RCS) { 747 bus_space_write_4(sc->iot, sc->aud_ioh, 748 ICH_GSTS + sc->sc_modem_offset, 749 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 750 *val = 0xffff; 751 DPRINTF(ICH_DEBUG_CODECIO, 752 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 753 return -1; 754 } 755 return 0; 756 } else { 757 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 758 return -1; 759 } 760 } 761 762 static int 763 auich_write_codec(void *v, uint8_t reg, uint16_t val) 764 { 765 struct auich_softc *sc; 766 int i; 767 768 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 769 sc = v; 770 /* wait for an access semaphore */ 771 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 772 bus_space_read_1(sc->iot, sc->aud_ioh, 773 ICH_CAS + sc->sc_modem_offset) & 1; 774 DELAY(ICH_CODECIO_INTERVAL)); 775 776 if (i > 0) { 777 bus_space_write_2(sc->iot, sc->mix_ioh, reg + (sc->codecnum * 0x80), val); 778 return 0; 779 } else { 780 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 781 return -1; 782 } 783 } 784 785 static int 786 auich_attach_codec(void *v, struct ac97_codec_if *cif) 787 { 788 struct auich_softc *sc; 789 790 sc = v; 791 sc->codec_if = cif; 792 793 return 0; 794 } 795 796 static int 797 auich_reset_codec(void *v) 798 { 799 struct auich_softc *sc; 800 int i; 801 uint32_t control, status; 802 803 sc = v; 804 control = bus_space_read_4(sc->iot, sc->aud_ioh, 805 ICH_GCTRL + sc->sc_modem_offset); 806 if (sc->sc_modem_offset == 0) 807 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 808 else 809 control &= ~ICH_ACLSO; 810 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 811 bus_space_write_4(sc->iot, sc->aud_ioh, 812 ICH_GCTRL + sc->sc_modem_offset, control); 813 814 for (i = 500000; i >= 0; i--) { 815 status = bus_space_read_4(sc->iot, sc->aud_ioh, 816 ICH_GSTS + sc->sc_modem_offset); 817 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 818 break; 819 DELAY(1); 820 } 821 if (i <= 0) { 822 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 823 return ETIMEDOUT; 824 } 825 #ifdef DEBUG 826 if (status & ICH_SCR) 827 printf("%s: The 2nd codec is ready.\n", 828 sc->sc_dev.dv_xname); 829 if (status & ICH_S2CR) 830 printf("%s: The 3rd codec is ready.\n", 831 sc->sc_dev.dv_xname); 832 #endif 833 return 0; 834 } 835 836 static enum ac97_host_flags 837 auich_flags_codec(void *v) 838 { 839 struct auich_softc *sc; 840 841 sc = (struct auich_softc *)v; 842 if (sc->sc_modem_offset != 0) 843 return AC97_HOST_SKIP_AUDIO; 844 else 845 return AC97_HOST_SKIP_MODEM; 846 } 847 848 static int 849 auich_query_encoding(void *v, struct audio_encoding *aep) 850 { 851 struct auich_softc *sc; 852 853 sc = (struct auich_softc *)v; 854 return auconv_query_encoding(sc->sc_encodings, aep); 855 } 856 857 static int 858 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 859 { 860 int ret; 861 u_int ratetmp; 862 863 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 864 ratetmp = srate; 865 if (mode == AUMODE_RECORD) 866 return sc->codec_if->vtbl->set_rate(sc->codec_if, 867 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 868 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 869 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 870 if (ret) 871 return ret; 872 ratetmp = srate; 873 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 874 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 875 if (ret) 876 return ret; 877 ratetmp = srate; 878 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 879 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 880 return ret; 881 } 882 883 static int 884 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 885 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 886 { 887 struct auich_softc *sc; 888 audio_params_t *p; 889 stream_filter_list_t *fil; 890 int mode, index; 891 uint32_t control; 892 893 sc = v; 894 for (mode = AUMODE_RECORD; mode != -1; 895 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 896 if ((setmode & mode) == 0) 897 continue; 898 899 p = mode == AUMODE_PLAY ? play : rec; 900 fil = mode == AUMODE_PLAY ? pfil : rfil; 901 if (p == NULL) 902 continue; 903 904 if (sc->sc_modem_offset == 0) { 905 if (p->sample_rate < 8000 || 906 p->sample_rate > 48000) 907 return EINVAL; 908 909 index = auconv_set_converter(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 910 mode, p, TRUE, fil); 911 } else { 912 if (p->sample_rate != 8000 && p->sample_rate != 16000) 913 return EINVAL; 914 index = auconv_set_converter(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 915 mode, p, TRUE, fil); 916 } 917 if (index < 0) 918 return EINVAL; 919 if (fil->req_size > 0) 920 p = &fil->filters[0].param; 921 /* p represents HW encoding */ 922 if (sc->sc_modem_offset == 0) { 923 if (sc->sc_audio_formats[index].frequency_type != 1 924 && auich_set_rate(sc, mode, p->sample_rate)) 925 return EINVAL; 926 } else { 927 if (sc->sc_modem_formats[index].frequency_type != 1 928 && auich_set_rate(sc, mode, p->sample_rate)) 929 return EINVAL; 930 auich_write_codec(sc, AC97_REG_LINE1_RATE, 931 p->sample_rate); 932 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 933 } 934 if (mode == AUMODE_PLAY) { 935 control = bus_space_read_4(sc->iot, sc->aud_ioh, 936 ICH_GCTRL + sc->sc_modem_offset); 937 if (sc->sc_modem_offset == 0) 938 control &= ~ICH_PCM246_MASK; 939 if (p->channels == 4) { 940 control |= ICH_PCM4; 941 } else if (p->channels == 6) { 942 control |= ICH_PCM6; 943 } 944 bus_space_write_4(sc->iot, sc->aud_ioh, 945 ICH_GCTRL + sc->sc_modem_offset, control); 946 } 947 } 948 949 return 0; 950 } 951 952 static int 953 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 954 { 955 956 return blk & ~0x3f; /* keep good alignment */ 957 } 958 959 static void 960 auich_halt_pipe(struct auich_softc *sc, int pipe) 961 { 962 int i; 963 uint32_t status; 964 965 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 966 for (i = 0; i < 100; i++) { 967 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 968 if (status & ICH_DCH) 969 break; 970 DELAY(1); 971 } 972 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 973 974 #if 1 975 if (i > 0) 976 printf("auich_halt_pipe: halt took %d cycles\n", i); 977 #endif 978 } 979 980 static int 981 auich_halt_output(void *v) 982 { 983 struct auich_softc *sc; 984 985 sc = v; 986 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 987 988 auich_halt_pipe(sc, ICH_PCMO); 989 sc->pcmo.intr = NULL; 990 991 return 0; 992 } 993 994 static int 995 auich_halt_input(void *v) 996 { 997 struct auich_softc *sc; 998 999 sc = v; 1000 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1001 1002 auich_halt_pipe(sc, ICH_PCMI); 1003 sc->pcmi.intr = NULL; 1004 1005 return 0; 1006 } 1007 1008 static int 1009 auich_getdev(void *v, struct audio_device *adp) 1010 { 1011 struct auich_softc *sc; 1012 1013 sc = v; 1014 *adp = sc->sc_audev; 1015 return 0; 1016 } 1017 1018 static int 1019 auich_set_port(void *v, mixer_ctrl_t *cp) 1020 { 1021 struct auich_softc *sc; 1022 1023 sc = v; 1024 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1025 } 1026 1027 static int 1028 auich_get_port(void *v, mixer_ctrl_t *cp) 1029 { 1030 struct auich_softc *sc; 1031 1032 sc = v; 1033 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1034 } 1035 1036 static int 1037 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1038 { 1039 struct auich_softc *sc; 1040 1041 sc = v; 1042 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1043 } 1044 1045 static void * 1046 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 1047 int flags) 1048 { 1049 struct auich_softc *sc; 1050 struct auich_dma *p; 1051 int error; 1052 1053 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1054 return NULL; 1055 1056 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1057 if (p == NULL) 1058 return NULL; 1059 1060 sc = v; 1061 error = auich_allocmem(sc, size, 0, p); 1062 if (error) { 1063 free(p, pool); 1064 return NULL; 1065 } 1066 1067 p->next = sc->sc_dmas; 1068 sc->sc_dmas = p; 1069 1070 return KERNADDR(p); 1071 } 1072 1073 static void 1074 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1075 { 1076 struct auich_softc *sc; 1077 struct auich_dma *p, **pp; 1078 1079 sc = v; 1080 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1081 if (KERNADDR(p) == ptr) { 1082 auich_freemem(sc, p); 1083 *pp = p->next; 1084 free(p, pool); 1085 return; 1086 } 1087 } 1088 } 1089 1090 static size_t 1091 auich_round_buffersize(void *v, int direction, size_t size) 1092 { 1093 1094 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1095 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1096 1097 return size; 1098 } 1099 1100 static paddr_t 1101 auich_mappage(void *v, void *mem, off_t off, int prot) 1102 { 1103 struct auich_softc *sc; 1104 struct auich_dma *p; 1105 1106 if (off < 0) 1107 return -1; 1108 sc = v; 1109 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1110 continue; 1111 if (!p) 1112 return -1; 1113 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1114 off, prot, BUS_DMA_WAITOK); 1115 } 1116 1117 static int 1118 auich_get_props(void *v) 1119 { 1120 struct auich_softc *sc; 1121 int props; 1122 1123 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1124 sc = v; 1125 /* 1126 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1127 * rate because of aurateconv. Applications can't know what rate the 1128 * device can process in the case of mmap(). 1129 */ 1130 if (!AC97_IS_FIXED_RATE(sc->codec_if) || sc->sc_modem_offset != 0) 1131 props |= AUDIO_PROP_MMAP; 1132 return props; 1133 } 1134 1135 static int 1136 auich_intr(void *v) 1137 { 1138 struct auich_softc *sc; 1139 int ret, gsts; 1140 #ifdef DIAGNOSTIC 1141 int csts; 1142 #endif 1143 1144 sc = v; 1145 ret = 0; 1146 #ifdef DIAGNOSTIC 1147 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1148 if (csts & PCI_STATUS_MASTER_ABORT) { 1149 printf("auich_intr: PCI master abort\n"); 1150 } 1151 #endif 1152 1153 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1154 ICH_GSTS + sc->sc_modem_offset); 1155 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1156 1157 if ((sc->sc_modem_offset == 0 && gsts & ICH_POINT) || 1158 (sc->sc_modem_offset != 0 && gsts & ICH_MOINT)) { 1159 int sts; 1160 1161 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1162 ICH_PCMO + sc->sc_sts_reg); 1163 DPRINTF(ICH_DEBUG_INTR, 1164 ("auich_intr: osts=0x%x\n", sts)); 1165 1166 if (sts & ICH_FIFOE) 1167 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1168 1169 if (sts & ICH_BCIS) 1170 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1171 1172 /* int ack */ 1173 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1174 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1175 if (sc->sc_modem_offset == 0) 1176 bus_space_write_4(sc->iot, sc->aud_ioh, 1177 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1178 else 1179 bus_space_write_4(sc->iot, sc->aud_ioh, 1180 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1181 ret++; 1182 } 1183 1184 if ((sc->sc_modem_offset == 0 && gsts & ICH_PIINT) || 1185 (sc->sc_modem_offset != 0 && gsts & ICH_MIINT)) { 1186 int sts; 1187 1188 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1189 ICH_PCMI + sc->sc_sts_reg); 1190 DPRINTF(ICH_DEBUG_INTR, 1191 ("auich_intr: ists=0x%x\n", sts)); 1192 1193 if (sts & ICH_FIFOE) 1194 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1195 1196 if (sts & ICH_BCIS) 1197 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1198 1199 /* int ack */ 1200 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1201 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1202 if (sc->sc_modem_offset == 0) 1203 bus_space_write_4(sc->iot, sc->aud_ioh, 1204 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1205 else 1206 bus_space_write_4(sc->iot, sc->aud_ioh, 1207 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1208 ret++; 1209 } 1210 1211 if (sc->sc_modem_offset != 0 && gsts & ICH_MINT) { 1212 int sts; 1213 1214 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1215 ICH_MICI + sc->sc_sts_reg); 1216 DPRINTF(ICH_DEBUG_INTR, 1217 ("auich_intr: ists=0x%x\n", sts)); 1218 1219 if (sts & ICH_FIFOE) 1220 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1221 1222 if (sts & ICH_BCIS) 1223 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1224 1225 /* int ack */ 1226 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1227 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1228 bus_space_write_4(sc->iot, sc->aud_ioh, 1229 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1230 ret++; 1231 } 1232 1233 return ret; 1234 } 1235 1236 static void 1237 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1238 { 1239 int blksize, qptr; 1240 struct auich_dmalist *q; 1241 1242 blksize = ring->blksize; 1243 1244 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1245 q = &ring->dmalist[qptr]; 1246 q->base = ring->p; 1247 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1248 1249 ring->p += blksize; 1250 if (ring->p >= ring->end) 1251 ring->p = ring->start; 1252 } 1253 ring->qptr = 0; 1254 1255 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1256 (qptr - 1) & ICH_LVI_MASK); 1257 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1258 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1259 } 1260 1261 static void 1262 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1263 { 1264 int blksize, qptr, nqptr; 1265 struct auich_dmalist *q; 1266 1267 blksize = ring->blksize; 1268 qptr = ring->qptr; 1269 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1270 1271 while (qptr != nqptr) { 1272 q = &ring->dmalist[qptr]; 1273 q->base = ring->p; 1274 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1275 1276 DPRINTF(ICH_DEBUG_INTR, 1277 ("auich_intr: %p, %p = %x @ 0x%x\n", 1278 &ring->dmalist[qptr], q, q->len, q->base)); 1279 1280 ring->p += blksize; 1281 if (ring->p >= ring->end) 1282 ring->p = ring->start; 1283 1284 qptr = (qptr + 1) & ICH_LVI_MASK; 1285 if (ring->intr) 1286 ring->intr(ring->arg); 1287 } 1288 ring->qptr = qptr; 1289 1290 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1291 (qptr - 1) & ICH_LVI_MASK); 1292 } 1293 1294 static int 1295 auich_trigger_output(void *v, void *start, void *end, int blksize, 1296 void (*intr)(void *), void *arg, const audio_params_t *param) 1297 { 1298 struct auich_softc *sc; 1299 struct auich_dma *p; 1300 size_t size; 1301 1302 DPRINTF(ICH_DEBUG_DMA, 1303 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1304 start, end, blksize, intr, arg, param)); 1305 sc = v; 1306 1307 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1308 continue; 1309 if (!p) { 1310 printf("auich_trigger_output: bad addr %p\n", start); 1311 return EINVAL; 1312 } 1313 1314 size = (size_t)((caddr_t)end - (caddr_t)start); 1315 1316 sc->pcmo.intr = intr; 1317 sc->pcmo.arg = arg; 1318 sc->pcmo.start = DMAADDR(p); 1319 sc->pcmo.p = sc->pcmo.start; 1320 sc->pcmo.end = sc->pcmo.start + size; 1321 sc->pcmo.blksize = blksize; 1322 1323 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1324 sc->sc_cddma + ICH_PCMO_OFF(0)); 1325 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1326 1327 return 0; 1328 } 1329 1330 static int 1331 auich_trigger_input(void *v, void *start, void *end, int blksize, 1332 void (*intr)(void *), void *arg, const audio_params_t *param) 1333 { 1334 struct auich_softc *sc; 1335 struct auich_dma *p; 1336 size_t size; 1337 1338 DPRINTF(ICH_DEBUG_DMA, 1339 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1340 start, end, blksize, intr, arg, param)); 1341 sc = v; 1342 1343 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1344 continue; 1345 if (!p) { 1346 printf("auich_trigger_input: bad addr %p\n", start); 1347 return EINVAL; 1348 } 1349 1350 size = (size_t)((caddr_t)end - (caddr_t)start); 1351 1352 sc->pcmi.intr = intr; 1353 sc->pcmi.arg = arg; 1354 sc->pcmi.start = DMAADDR(p); 1355 sc->pcmi.p = sc->pcmi.start; 1356 sc->pcmi.end = sc->pcmi.start + size; 1357 sc->pcmi.blksize = blksize; 1358 1359 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1360 sc->sc_cddma + ICH_PCMI_OFF(0)); 1361 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1362 1363 return 0; 1364 } 1365 1366 static int 1367 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1368 struct auich_dma *p) 1369 { 1370 int error; 1371 1372 p->size = size; 1373 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1374 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1375 &p->nsegs, BUS_DMA_NOWAIT); 1376 if (error) 1377 return error; 1378 1379 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1380 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1381 if (error) 1382 goto free; 1383 1384 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1385 0, BUS_DMA_NOWAIT, &p->map); 1386 if (error) 1387 goto unmap; 1388 1389 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1390 BUS_DMA_NOWAIT); 1391 if (error) 1392 goto destroy; 1393 return 0; 1394 1395 destroy: 1396 bus_dmamap_destroy(sc->dmat, p->map); 1397 unmap: 1398 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1399 free: 1400 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1401 return error; 1402 } 1403 1404 static int 1405 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1406 { 1407 1408 bus_dmamap_unload(sc->dmat, p->map); 1409 bus_dmamap_destroy(sc->dmat, p->map); 1410 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1411 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1412 return 0; 1413 } 1414 1415 static int 1416 auich_alloc_cdata(struct auich_softc *sc) 1417 { 1418 bus_dma_segment_t seg; 1419 int error, rseg; 1420 1421 /* 1422 * Allocate the control data structure, and create and load the 1423 * DMA map for it. 1424 */ 1425 if ((error = bus_dmamem_alloc(sc->dmat, 1426 sizeof(struct auich_cdata), 1427 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1428 printf("%s: unable to allocate control data, error = %d\n", 1429 sc->sc_dev.dv_xname, error); 1430 goto fail_0; 1431 } 1432 1433 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1434 sizeof(struct auich_cdata), 1435 (caddr_t *) &sc->sc_cdata, 1436 sc->sc_dmamap_flags)) != 0) { 1437 printf("%s: unable to map control data, error = %d\n", 1438 sc->sc_dev.dv_xname, error); 1439 goto fail_1; 1440 } 1441 1442 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1443 sizeof(struct auich_cdata), 0, 0, 1444 &sc->sc_cddmamap)) != 0) { 1445 printf("%s: unable to create control data DMA map, " 1446 "error = %d\n", sc->sc_dev.dv_xname, error); 1447 goto fail_2; 1448 } 1449 1450 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1451 sc->sc_cdata, sizeof(struct auich_cdata), 1452 NULL, 0)) != 0) { 1453 printf("%s: unable tp load control data DMA map, " 1454 "error = %d\n", sc->sc_dev.dv_xname, error); 1455 goto fail_3; 1456 } 1457 1458 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1459 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1460 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1461 1462 return 0; 1463 1464 fail_3: 1465 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1466 fail_2: 1467 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1468 sizeof(struct auich_cdata)); 1469 fail_1: 1470 bus_dmamem_free(sc->dmat, &seg, rseg); 1471 fail_0: 1472 return error; 1473 } 1474 1475 static void 1476 auich_powerhook(int why, void *addr) 1477 { 1478 struct auich_softc *sc; 1479 1480 sc = (struct auich_softc *)addr; 1481 switch (why) { 1482 case PWR_SUSPEND: 1483 case PWR_STANDBY: 1484 /* Power down */ 1485 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1486 sc->sc_suspend = why; 1487 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1488 break; 1489 1490 case PWR_RESUME: 1491 /* Wake up */ 1492 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1493 if (sc->sc_suspend == PWR_RESUME) { 1494 printf("%s: resume without suspend.\n", 1495 sc->sc_dev.dv_xname); 1496 sc->sc_suspend = why; 1497 return; 1498 } 1499 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1500 sc->sc_suspend = why; 1501 auich_reset_codec(sc); 1502 DELAY(1000); 1503 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1504 break; 1505 1506 case PWR_SOFTSUSPEND: 1507 case PWR_SOFTSTANDBY: 1508 case PWR_SOFTRESUME: 1509 break; 1510 } 1511 } 1512 1513 /* 1514 * Calibrate card (some boards are overclocked and need scaling) 1515 */ 1516 static void 1517 auich_calibrate(struct auich_softc *sc) 1518 { 1519 struct timeval t1, t2; 1520 uint8_t ociv, nciv; 1521 uint64_t wait_us; 1522 uint32_t actual_48k_rate, bytes, ac97rate; 1523 void *temp_buffer; 1524 struct auich_dma *p; 1525 u_int rate; 1526 1527 /* 1528 * Grab audio from input for fixed interval and compare how 1529 * much we actually get with what we expect. Interval needs 1530 * to be sufficiently short that no interrupts are 1531 * generated. 1532 */ 1533 1534 /* Force the codec to a known state first. */ 1535 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1536 rate = sc->sc_ac97_clock = 48000; 1537 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1538 &rate); 1539 1540 /* Setup a buffer */ 1541 bytes = 64000; 1542 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1543 1544 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1545 continue; 1546 if (p == NULL) { 1547 printf("auich_calibrate: bad address %p\n", temp_buffer); 1548 return; 1549 } 1550 sc->pcmi.dmalist[0].base = DMAADDR(p); 1551 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1552 1553 /* 1554 * our data format is stereo, 16 bit so each sample is 4 bytes. 1555 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1556 * we're going to start recording with interrupts disabled and measure 1557 * the time taken for one block to complete. we know the block size, 1558 * we know the time in microseconds, we calculate the sample rate: 1559 * 1560 * actual_rate [bps] = bytes / (time [s] * 4) 1561 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1562 * actual_rate [Hz] = (bytes * 250000) / time [us] 1563 */ 1564 1565 /* prepare */ 1566 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1567 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1568 sc->sc_cddma + ICH_PCMI_OFF(0)); 1569 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1570 (0 - 1) & ICH_LVI_MASK); 1571 1572 /* start */ 1573 microtime(&t1); 1574 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1575 1576 /* wait */ 1577 nciv = ociv; 1578 do { 1579 microtime(&t2); 1580 if (t2.tv_sec - t1.tv_sec > 1) 1581 break; 1582 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1583 ICH_PCMI + ICH_CIV); 1584 } while (nciv == ociv); 1585 microtime(&t2); 1586 1587 /* stop */ 1588 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1589 1590 /* reset */ 1591 DELAY(100); 1592 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1593 1594 /* turn time delta into us */ 1595 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1596 1597 auich_freem(sc, temp_buffer, M_DEVBUF); 1598 1599 if (nciv == ociv) { 1600 printf("%s: ac97 link rate calibration timed out after %" 1601 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1602 return; 1603 } 1604 1605 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1606 1607 if (actual_48k_rate < 50000) 1608 ac97rate = 48000; 1609 else 1610 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1611 1612 printf("%s: measured ac97 link rate at %d Hz", 1613 sc->sc_dev.dv_xname, actual_48k_rate); 1614 if (ac97rate != actual_48k_rate) 1615 printf(", will use %d Hz", ac97rate); 1616 printf("\n"); 1617 1618 sc->sc_ac97_clock = ac97rate; 1619 } 1620
Indexes created Thu Oct 23 22:10:10 GMT 2025