auich.c revision 1.94
1 /* $NetBSD: auich.c,v 1.94 2005/04/11 11:20:45 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven (at) katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg (at) freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.94 2005/04/11 11:20:45 jmcneill Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 187 struct ac97_codec_if *codec_if; 188 struct ac97_host_if host_if; 189 int sc_codecnum; 190 int sc_codectype; 191 192 /* DMA scatter-gather lists. */ 193 bus_dmamap_t sc_cddmamap; 194 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 195 196 struct auich_cdata *sc_cdata; 197 198 struct auich_ring { 199 int qptr; 200 struct auich_dmalist *dmalist; 201 202 uint32_t start, p, end; 203 int blksize; 204 205 void (*intr)(void *); 206 void *arg; 207 } pcmo, pcmi, mici; 208 209 struct auich_dma *sc_dmas; 210 211 /* SiS 7012 hack */ 212 int sc_sample_shift; 213 int sc_sts_reg; 214 /* 440MX workaround */ 215 int sc_dmamap_flags; 216 217 /* Power Management */ 218 void *sc_powerhook; 219 int sc_suspend; 220 struct pci_conf_state sc_pciconf; 221 222 /* sysctl */ 223 struct sysctllog *sc_log; 224 uint32_t sc_ac97_clock; 225 int sc_ac97_clock_mib; 226 227 int sc_modem_offset; 228 229 #define AUICH_AUDIO_NFORMATS 3 230 #define AUICH_MODEM_NFORMATS 1 231 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 232 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 233 struct audio_encoding_set *sc_encodings; 234 }; 235 236 /* Debug */ 237 #ifdef AUICH_DEBUG 238 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 239 int auich_debug = 0xfffe; 240 #define ICH_DEBUG_CODECIO 0x0001 241 #define ICH_DEBUG_DMA 0x0002 242 #define ICH_DEBUG_INTR 0x0004 243 #else 244 #define DPRINTF(x,y) /* nothing */ 245 #endif 246 247 static int auich_match(struct device *, struct cfdata *, void *); 248 static void auich_attach(struct device *, struct device *, void *); 249 static int auich_detach(struct device *, int); 250 static int auich_activate(struct device *, enum devact); 251 static int auich_intr(void *); 252 253 CFATTACH_DECL(auich, sizeof(struct auich_softc), 254 auich_match, auich_attach, auich_detach, auich_activate); 255 256 static int auich_query_encoding(void *, struct audio_encoding *); 257 static int auich_set_params(void *, int, int, audio_params_t *, 258 audio_params_t *, stream_filter_list_t *, 259 stream_filter_list_t *); 260 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 261 static void auich_halt_pipe(struct auich_softc *, int); 262 static int auich_halt_output(void *); 263 static int auich_halt_input(void *); 264 static int auich_getdev(void *, struct audio_device *); 265 static int auich_set_port(void *, mixer_ctrl_t *); 266 static int auich_get_port(void *, mixer_ctrl_t *); 267 static int auich_query_devinfo(void *, mixer_devinfo_t *); 268 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 269 static void auich_freem(void *, void *, struct malloc_type *); 270 static size_t auich_round_buffersize(void *, int, size_t); 271 static paddr_t auich_mappage(void *, void *, off_t, int); 272 static int auich_get_props(void *); 273 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 274 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 275 static int auich_trigger_output(void *, void *, void *, int, 276 void (*)(void *), void *, const audio_params_t *); 277 static int auich_trigger_input(void *, void *, void *, int, 278 void (*)(void *), void *, const audio_params_t *); 279 280 static int auich_alloc_cdata(struct auich_softc *); 281 282 static int auich_allocmem(struct auich_softc *, size_t, size_t, 283 struct auich_dma *); 284 static int auich_freemem(struct auich_softc *, struct auich_dma *); 285 286 static void auich_powerhook(int, void *); 287 static int auich_set_rate(struct auich_softc *, int, u_long); 288 static int auich_sysctl_verify(SYSCTLFN_ARGS); 289 static void auich_finish_attach(struct device *); 290 static void auich_calibrate(struct auich_softc *); 291 292 static int auich_attach_codec(void *, struct ac97_codec_if *); 293 static int auich_read_codec(void *, uint8_t, uint16_t *); 294 static int auich_write_codec(void *, uint8_t, uint16_t); 295 static int auich_reset_codec(void *); 296 297 const struct audio_hw_if auich_hw_if = { 298 NULL, /* open */ 299 NULL, /* close */ 300 NULL, /* drain */ 301 auich_query_encoding, 302 auich_set_params, 303 auich_round_blocksize, 304 NULL, /* commit_setting */ 305 NULL, /* init_output */ 306 NULL, /* init_input */ 307 NULL, /* start_output */ 308 NULL, /* start_input */ 309 auich_halt_output, 310 auich_halt_input, 311 NULL, /* speaker_ctl */ 312 auich_getdev, 313 NULL, /* getfd */ 314 auich_set_port, 315 auich_get_port, 316 auich_query_devinfo, 317 auich_allocm, 318 auich_freem, 319 auich_round_buffersize, 320 auich_mappage, 321 auich_get_props, 322 auich_trigger_output, 323 auich_trigger_input, 324 NULL, /* dev_ioctl */ 325 }; 326 327 #define AUICH_FORMATS_1CH 0 328 #define AUICH_FORMATS_4CH 1 329 #define AUICH_FORMATS_6CH 2 330 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 331 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 332 2, AUFMT_STEREO, 0, {8000, 48000}}, 333 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 334 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 335 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 336 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 337 }; 338 339 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 340 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 341 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 342 }; 343 344 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 345 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 346 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 347 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 348 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 349 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 350 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 351 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 352 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 353 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 354 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 355 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 356 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 357 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 358 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 359 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 360 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 361 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 362 363 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 364 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 365 366 struct auich_devtype { 367 pcireg_t id; 368 const char *name; 369 const char *shortname; /* must be less than 11 characters */ 370 }; 371 372 static const struct auich_devtype auich_audio_devices[] = { 373 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 374 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 375 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 376 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 377 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 378 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 379 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 380 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 381 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 382 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 383 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 384 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 385 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 386 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 387 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 388 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 389 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 390 { 0, NULL, NULL }, 391 }; 392 393 static const struct auich_devtype auich_modem_devices[] = { 394 #ifdef AUICH_ATTACH_MODEM 395 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 396 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 397 #endif 398 { 0, NULL, NULL }, 399 }; 400 401 static const struct auich_devtype * 402 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 403 { 404 const struct auich_devtype *d; 405 406 for (d = auich_devices; d->name != NULL; d++) { 407 if (pa->pa_id == d->id) 408 return d; 409 } 410 411 return NULL; 412 } 413 414 static int 415 auich_match(struct device *parent, struct cfdata *match, void *aux) 416 { 417 struct pci_attach_args *pa; 418 419 pa = aux; 420 if (auich_lookup(pa, auich_audio_devices) != NULL) 421 return 1; 422 if (auich_lookup(pa, auich_modem_devices) != NULL) 423 return 1; 424 425 return 0; 426 } 427 428 static void 429 auich_attach(struct device *parent, struct device *self, void *aux) 430 { 431 struct auich_softc *sc; 432 struct pci_attach_args *pa; 433 pci_intr_handle_t ih; 434 pcireg_t v; 435 const char *intrstr; 436 const struct auich_devtype *d; 437 struct sysctlnode *node, *node_ac97clock; 438 int err, node_mib, i; 439 440 sc = (struct auich_softc *)self; 441 pa = aux; 442 443 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 444 sc->sc_modem_offset = 0x10; 445 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 446 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 447 sc->sc_modem_offset = 0; 448 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 449 } else 450 panic("auich_attach: impossible"); 451 452 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 453 aprint_naive(": Audio controller\n"); 454 else 455 aprint_naive(": Modem controller\n"); 456 457 sc->sc_pc = pa->pa_pc; 458 sc->sc_pt = pa->pa_tag; 459 460 aprint_normal(": %s\n", d->name); 461 462 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 463 || d->id == PCIID_ICH4MODEM) { 464 /* 465 * Use native mode for ICH4/ICH5/ICH6 466 */ 467 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 468 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 469 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 470 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 471 v | ICH_CFG_IOSE); 472 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 473 0, &sc->iot, &sc->mix_ioh, NULL, 474 &sc->mix_size)) { 475 aprint_error("%s: can't map codec i/o space\n", 476 sc->sc_dev.dv_xname); 477 return; 478 } 479 } 480 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 481 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 482 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 483 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 484 v | ICH_CFG_IOSE); 485 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 486 0, &sc->iot, &sc->aud_ioh, NULL, 487 &sc->aud_size)) { 488 aprint_error("%s: can't map device i/o space\n", 489 sc->sc_dev.dv_xname); 490 return; 491 } 492 } 493 } else { 494 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 495 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 496 aprint_error("%s: can't map codec i/o space\n", 497 sc->sc_dev.dv_xname); 498 return; 499 } 500 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 501 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 502 aprint_error("%s: can't map device i/o space\n", 503 sc->sc_dev.dv_xname); 504 return; 505 } 506 } 507 sc->dmat = pa->pa_dmat; 508 509 /* enable bus mastering */ 510 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 511 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 512 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 513 514 /* Map and establish the interrupt. */ 515 if (pci_intr_map(pa, &ih)) { 516 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 517 return; 518 } 519 intrstr = pci_intr_string(pa->pa_pc, ih); 520 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 521 auich_intr, sc); 522 if (sc->sc_ih == NULL) { 523 aprint_error("%s: can't establish interrupt", 524 sc->sc_dev.dv_xname); 525 if (intrstr != NULL) 526 aprint_normal(" at %s", intrstr); 527 aprint_normal("\n"); 528 return; 529 } 530 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 531 532 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 533 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 534 "0x%02x", PCI_REVISION(pa->pa_class)); 535 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 536 537 /* SiS 7012 needs special handling */ 538 if (d->id == PCIID_SIS7012) { 539 sc->sc_sts_reg = ICH_PICB; 540 sc->sc_sample_shift = 0; 541 /* Un-mute output. From Linux. */ 542 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 543 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 544 ICH_SIS_CTL_UNMUTE); 545 } else { 546 sc->sc_sts_reg = ICH_STS; 547 sc->sc_sample_shift = 1; 548 } 549 550 /* Workaround for a 440MX B-stepping erratum */ 551 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 552 if (d->id == PCIID_440MX) { 553 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 554 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 555 } 556 557 /* Set up DMA lists. */ 558 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 559 auich_alloc_cdata(sc); 560 561 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 562 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 563 564 /* Modem codecs are always the secondary codec on ICH */ 565 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 566 567 sc->host_if.arg = sc; 568 sc->host_if.attach = auich_attach_codec; 569 sc->host_if.read = auich_read_codec; 570 sc->host_if.write = auich_write_codec; 571 sc->host_if.reset = auich_reset_codec; 572 573 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 574 return; 575 576 /* setup audio_format */ 577 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 578 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 579 if (!AC97_IS_4CH(sc->codec_if)) 580 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 581 if (!AC97_IS_6CH(sc->codec_if)) 582 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 583 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 584 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 585 sc->sc_audio_formats[i].frequency_type = 1; 586 sc->sc_audio_formats[i].frequency[0] = 48000; 587 } 588 } 589 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 590 &sc->sc_encodings)) 591 return; 592 } else { 593 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 594 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 595 &sc->sc_encodings)) 596 return; 597 } 598 599 600 /* Watch for power change */ 601 sc->sc_suspend = PWR_RESUME; 602 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 603 604 config_interrupts(self, auich_finish_attach); 605 606 /* sysctl setup */ 607 if (AC97_IS_FIXED_RATE(sc->codec_if) && 608 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 609 return; 610 611 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 612 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 613 CTL_HW, CTL_EOL); 614 if (err != 0) 615 goto sysctl_err; 616 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 617 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 618 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 619 if (err != 0) 620 goto sysctl_err; 621 node_mib = node->sysctl_num; 622 623 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 624 /* passing the sc address instead of &sc->sc_ac97_clock */ 625 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 626 CTLFLAG_READWRITE, 627 CTLTYPE_INT, "ac97rate", 628 SYSCTL_DESCR("AC'97 codec link rate"), 629 auich_sysctl_verify, 0, sc, 0, 630 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 631 if (err != 0) 632 goto sysctl_err; 633 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 634 } 635 636 return; 637 638 sysctl_err: 639 printf("%s: failed to add sysctl nodes. (%d)\n", 640 sc->sc_dev.dv_xname, err); 641 return; /* failure of sysctl is not fatal. */ 642 } 643 644 static int 645 auich_activate(struct device *self, enum devact act) 646 { 647 struct auich_softc *sc; 648 int ret; 649 650 sc = (struct auich_softc *)self; 651 ret = 0; 652 switch (act) { 653 case DVACT_ACTIVATE: 654 return EOPNOTSUPP; 655 case DVACT_DEACTIVATE: 656 if (sc->sc_audiodev != NULL) 657 ret = config_deactivate(sc->sc_audiodev); 658 return ret; 659 } 660 return EOPNOTSUPP; 661 } 662 663 static int 664 auich_detach(struct device *self, int flags) 665 { 666 struct auich_softc *sc; 667 668 sc = (struct auich_softc *)self; 669 670 /* audio */ 671 if (sc->sc_audiodev != NULL) 672 config_detach(sc->sc_audiodev, flags); 673 674 /* sysctl */ 675 sysctl_teardown(&sc->sc_log); 676 677 /* audio_encoding_set */ 678 auconv_delete_encodings(sc->sc_encodings); 679 680 /* ac97 */ 681 if (sc->codec_if != NULL) 682 sc->codec_if->vtbl->detach(sc->codec_if); 683 684 /* PCI */ 685 if (sc->sc_ih != NULL) 686 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 687 if (sc->mix_size != 0) 688 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 689 if (sc->aud_size != 0) 690 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 691 return 0; 692 } 693 694 static int 695 auich_sysctl_verify(SYSCTLFN_ARGS) 696 { 697 int error, tmp; 698 struct sysctlnode node; 699 struct auich_softc *sc; 700 701 node = *rnode; 702 sc = rnode->sysctl_data; 703 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 704 tmp = sc->sc_ac97_clock; 705 node.sysctl_data = &tmp; 706 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 707 if (error || newp == NULL) 708 return error; 709 710 if (tmp < 48000 || tmp > 96000) 711 return EINVAL; 712 sc->sc_ac97_clock = tmp; 713 } 714 715 return 0; 716 } 717 718 static void 719 auich_finish_attach(struct device *self) 720 { 721 struct auich_softc *sc; 722 723 sc = (void *)self; 724 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 725 auich_calibrate(sc); 726 727 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 728 } 729 730 #define ICH_CODECIO_INTERVAL 10 731 static int 732 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 733 { 734 struct auich_softc *sc; 735 int i; 736 uint32_t status; 737 738 sc = v; 739 /* wait for an access semaphore */ 740 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 741 bus_space_read_1(sc->iot, sc->aud_ioh, 742 ICH_CAS + sc->sc_modem_offset) & 1; 743 DELAY(ICH_CODECIO_INTERVAL)); 744 745 if (i > 0) { 746 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 747 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 748 DPRINTF(ICH_DEBUG_CODECIO, 749 ("auich_read_codec(%x, %x)\n", reg, *val)); 750 status = bus_space_read_4(sc->iot, sc->aud_ioh, 751 ICH_GSTS + sc->sc_modem_offset); 752 if (status & ICH_RCS) { 753 bus_space_write_4(sc->iot, sc->aud_ioh, 754 ICH_GSTS + sc->sc_modem_offset, 755 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 756 *val = 0xffff; 757 DPRINTF(ICH_DEBUG_CODECIO, 758 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 759 return -1; 760 } 761 return 0; 762 } else { 763 aprint_normal("%s: read_codec timeout\n", sc->sc_dev.dv_xname); 764 return -1; 765 } 766 } 767 768 static int 769 auich_write_codec(void *v, uint8_t reg, uint16_t val) 770 { 771 struct auich_softc *sc; 772 int i; 773 774 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 775 sc = v; 776 /* wait for an access semaphore */ 777 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 778 bus_space_read_1(sc->iot, sc->aud_ioh, 779 ICH_CAS + sc->sc_modem_offset) & 1; 780 DELAY(ICH_CODECIO_INTERVAL)); 781 782 if (i > 0) { 783 bus_space_write_2(sc->iot, sc->mix_ioh, 784 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 785 return 0; 786 } else { 787 aprint_normal("%s: write_codec timeout\n", sc->sc_dev.dv_xname); 788 return -1; 789 } 790 } 791 792 static int 793 auich_attach_codec(void *v, struct ac97_codec_if *cif) 794 { 795 struct auich_softc *sc; 796 797 sc = v; 798 sc->codec_if = cif; 799 800 return 0; 801 } 802 803 static int 804 auich_reset_codec(void *v) 805 { 806 struct auich_softc *sc; 807 int i; 808 uint32_t control, status; 809 810 sc = v; 811 control = bus_space_read_4(sc->iot, sc->aud_ioh, 812 ICH_GCTRL + sc->sc_modem_offset); 813 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 814 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 815 else 816 control &= ~ICH_ACLSO; 817 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 818 bus_space_write_4(sc->iot, sc->aud_ioh, 819 ICH_GCTRL + sc->sc_modem_offset, control); 820 821 for (i = 500000; i >= 0; i--) { 822 status = bus_space_read_4(sc->iot, sc->aud_ioh, 823 ICH_GSTS + sc->sc_modem_offset); 824 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 825 break; 826 DELAY(1); 827 } 828 if (i <= 0) { 829 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 830 return ETIMEDOUT; 831 } 832 #ifdef DEBUG 833 if (status & ICH_SCR) 834 printf("%s: The 2nd codec is ready.\n", 835 sc->sc_dev.dv_xname); 836 if (status & ICH_S2CR) 837 printf("%s: The 3rd codec is ready.\n", 838 sc->sc_dev.dv_xname); 839 #endif 840 return 0; 841 } 842 843 static int 844 auich_query_encoding(void *v, struct audio_encoding *aep) 845 { 846 struct auich_softc *sc; 847 848 sc = (struct auich_softc *)v; 849 return auconv_query_encoding(sc->sc_encodings, aep); 850 } 851 852 static int 853 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 854 { 855 int ret; 856 u_int ratetmp; 857 858 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 859 ratetmp = srate; 860 if (mode == AUMODE_RECORD) 861 return sc->codec_if->vtbl->set_rate(sc->codec_if, 862 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 863 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 864 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 865 if (ret) 866 return ret; 867 ratetmp = srate; 868 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 869 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 870 if (ret) 871 return ret; 872 ratetmp = srate; 873 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 874 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 875 return ret; 876 } 877 878 static int 879 auich_set_params(void *v, int setmode, int usemode, audio_params_t *play, 880 audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) 881 { 882 struct auich_softc *sc; 883 audio_params_t *p; 884 stream_filter_list_t *fil; 885 int mode, index; 886 uint32_t control; 887 888 sc = v; 889 for (mode = AUMODE_RECORD; mode != -1; 890 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 891 if ((setmode & mode) == 0) 892 continue; 893 894 p = mode == AUMODE_PLAY ? play : rec; 895 fil = mode == AUMODE_PLAY ? pfil : rfil; 896 if (p == NULL) 897 continue; 898 899 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 900 if (p->sample_rate < 8000 || 901 p->sample_rate > 48000) 902 return EINVAL; 903 904 index = auconv_set_converter(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 905 mode, p, TRUE, fil); 906 } else { 907 if (p->sample_rate != 8000 && p->sample_rate != 16000) 908 return EINVAL; 909 index = auconv_set_converter(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 910 mode, p, TRUE, fil); 911 } 912 if (index < 0) 913 return EINVAL; 914 if (fil->req_size > 0) 915 p = &fil->filters[0].param; 916 /* p represents HW encoding */ 917 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 918 if (sc->sc_audio_formats[index].frequency_type != 1 919 && auich_set_rate(sc, mode, p->sample_rate)) 920 return EINVAL; 921 } else { 922 if (sc->sc_modem_formats[index].frequency_type != 1 923 && auich_set_rate(sc, mode, p->sample_rate)) 924 return EINVAL; 925 auich_write_codec(sc, AC97_REG_LINE1_RATE, 926 p->sample_rate); 927 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 928 } 929 if (mode == AUMODE_PLAY && 930 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 931 control = bus_space_read_4(sc->iot, sc->aud_ioh, 932 ICH_GCTRL + sc->sc_modem_offset); 933 control &= ~ICH_PCM246_MASK; 934 if (p->channels == 4) { 935 control |= ICH_PCM4; 936 } else if (p->channels == 6) { 937 control |= ICH_PCM6; 938 } 939 bus_space_write_4(sc->iot, sc->aud_ioh, 940 ICH_GCTRL + sc->sc_modem_offset, control); 941 } 942 } 943 944 return 0; 945 } 946 947 static int 948 auich_round_blocksize(void *v, int blk, int mode, const audio_params_t *param) 949 { 950 951 return blk & ~0x3f; /* keep good alignment */ 952 } 953 954 static void 955 auich_halt_pipe(struct auich_softc *sc, int pipe) 956 { 957 int i; 958 uint32_t status; 959 960 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 961 for (i = 0; i < 100; i++) { 962 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 963 if (status & ICH_DCH) 964 break; 965 DELAY(1); 966 } 967 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 968 969 #if 1 970 if (i > 0) 971 printf("auich_halt_pipe: halt took %d cycles\n", i); 972 #endif 973 } 974 975 static int 976 auich_halt_output(void *v) 977 { 978 struct auich_softc *sc; 979 980 sc = v; 981 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 982 983 auich_halt_pipe(sc, ICH_PCMO); 984 sc->pcmo.intr = NULL; 985 986 return 0; 987 } 988 989 static int 990 auich_halt_input(void *v) 991 { 992 struct auich_softc *sc; 993 994 sc = v; 995 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", sc->sc_dev.dv_xname)); 996 997 auich_halt_pipe(sc, ICH_PCMI); 998 sc->pcmi.intr = NULL; 999 1000 return 0; 1001 } 1002 1003 static int 1004 auich_getdev(void *v, struct audio_device *adp) 1005 { 1006 struct auich_softc *sc; 1007 1008 sc = v; 1009 *adp = sc->sc_audev; 1010 return 0; 1011 } 1012 1013 static int 1014 auich_set_port(void *v, mixer_ctrl_t *cp) 1015 { 1016 struct auich_softc *sc; 1017 1018 sc = v; 1019 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1020 } 1021 1022 static int 1023 auich_get_port(void *v, mixer_ctrl_t *cp) 1024 { 1025 struct auich_softc *sc; 1026 1027 sc = v; 1028 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1029 } 1030 1031 static int 1032 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1033 { 1034 struct auich_softc *sc; 1035 1036 sc = v; 1037 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1038 } 1039 1040 static void * 1041 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 1042 int flags) 1043 { 1044 struct auich_softc *sc; 1045 struct auich_dma *p; 1046 int error; 1047 1048 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1049 return NULL; 1050 1051 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1052 if (p == NULL) 1053 return NULL; 1054 1055 sc = v; 1056 error = auich_allocmem(sc, size, 0, p); 1057 if (error) { 1058 free(p, pool); 1059 return NULL; 1060 } 1061 1062 p->next = sc->sc_dmas; 1063 sc->sc_dmas = p; 1064 1065 return KERNADDR(p); 1066 } 1067 1068 static void 1069 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1070 { 1071 struct auich_softc *sc; 1072 struct auich_dma *p, **pp; 1073 1074 sc = v; 1075 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1076 if (KERNADDR(p) == ptr) { 1077 auich_freemem(sc, p); 1078 *pp = p->next; 1079 free(p, pool); 1080 return; 1081 } 1082 } 1083 } 1084 1085 static size_t 1086 auich_round_buffersize(void *v, int direction, size_t size) 1087 { 1088 1089 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1090 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1091 1092 return size; 1093 } 1094 1095 static paddr_t 1096 auich_mappage(void *v, void *mem, off_t off, int prot) 1097 { 1098 struct auich_softc *sc; 1099 struct auich_dma *p; 1100 1101 if (off < 0) 1102 return -1; 1103 sc = v; 1104 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1105 continue; 1106 if (!p) 1107 return -1; 1108 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1109 off, prot, BUS_DMA_WAITOK); 1110 } 1111 1112 static int 1113 auich_get_props(void *v) 1114 { 1115 struct auich_softc *sc; 1116 int props; 1117 1118 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1119 sc = v; 1120 /* 1121 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1122 * rate because of aurateconv. Applications can't know what rate the 1123 * device can process in the case of mmap(). 1124 */ 1125 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1126 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1127 props |= AUDIO_PROP_MMAP; 1128 return props; 1129 } 1130 1131 static int 1132 auich_intr(void *v) 1133 { 1134 struct auich_softc *sc; 1135 int ret, gsts; 1136 #ifdef DIAGNOSTIC 1137 int csts; 1138 #endif 1139 1140 sc = v; 1141 ret = 0; 1142 #ifdef DIAGNOSTIC 1143 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1144 if (csts & PCI_STATUS_MASTER_ABORT) { 1145 printf("auich_intr: PCI master abort\n"); 1146 } 1147 #endif 1148 1149 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1150 ICH_GSTS + sc->sc_modem_offset); 1151 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1152 1153 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1154 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1155 int sts; 1156 1157 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1158 ICH_PCMO + sc->sc_sts_reg); 1159 DPRINTF(ICH_DEBUG_INTR, 1160 ("auich_intr: osts=0x%x\n", sts)); 1161 1162 if (sts & ICH_FIFOE) 1163 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1164 1165 if (sts & ICH_BCIS) 1166 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1167 1168 /* int ack */ 1169 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1170 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1171 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1172 bus_space_write_4(sc->iot, sc->aud_ioh, 1173 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1174 else 1175 bus_space_write_4(sc->iot, sc->aud_ioh, 1176 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1177 ret++; 1178 } 1179 1180 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1181 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1182 int sts; 1183 1184 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1185 ICH_PCMI + sc->sc_sts_reg); 1186 DPRINTF(ICH_DEBUG_INTR, 1187 ("auich_intr: ists=0x%x\n", sts)); 1188 1189 if (sts & ICH_FIFOE) 1190 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1191 1192 if (sts & ICH_BCIS) 1193 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1194 1195 /* int ack */ 1196 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1197 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1198 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1199 bus_space_write_4(sc->iot, sc->aud_ioh, 1200 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1201 else 1202 bus_space_write_4(sc->iot, sc->aud_ioh, 1203 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1204 ret++; 1205 } 1206 1207 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1208 int sts; 1209 1210 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1211 ICH_MICI + sc->sc_sts_reg); 1212 DPRINTF(ICH_DEBUG_INTR, 1213 ("auich_intr: ists=0x%x\n", sts)); 1214 1215 if (sts & ICH_FIFOE) 1216 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1217 1218 if (sts & ICH_BCIS) 1219 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1220 1221 /* int ack */ 1222 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1223 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1224 bus_space_write_4(sc->iot, sc->aud_ioh, 1225 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1226 ret++; 1227 } 1228 1229 return ret; 1230 } 1231 1232 static void 1233 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1234 { 1235 int blksize, qptr; 1236 struct auich_dmalist *q; 1237 1238 blksize = ring->blksize; 1239 1240 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1241 q = &ring->dmalist[qptr]; 1242 q->base = ring->p; 1243 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1244 1245 ring->p += blksize; 1246 if (ring->p >= ring->end) 1247 ring->p = ring->start; 1248 } 1249 ring->qptr = 0; 1250 1251 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1252 (qptr - 1) & ICH_LVI_MASK); 1253 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1254 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1255 } 1256 1257 static void 1258 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1259 { 1260 int blksize, qptr, nqptr; 1261 struct auich_dmalist *q; 1262 1263 blksize = ring->blksize; 1264 qptr = ring->qptr; 1265 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1266 1267 while (qptr != nqptr) { 1268 q = &ring->dmalist[qptr]; 1269 q->base = ring->p; 1270 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1271 1272 DPRINTF(ICH_DEBUG_INTR, 1273 ("auich_intr: %p, %p = %x @ 0x%x\n", 1274 &ring->dmalist[qptr], q, q->len, q->base)); 1275 1276 ring->p += blksize; 1277 if (ring->p >= ring->end) 1278 ring->p = ring->start; 1279 1280 qptr = (qptr + 1) & ICH_LVI_MASK; 1281 if (ring->intr) 1282 ring->intr(ring->arg); 1283 } 1284 ring->qptr = qptr; 1285 1286 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1287 (qptr - 1) & ICH_LVI_MASK); 1288 } 1289 1290 static int 1291 auich_trigger_output(void *v, void *start, void *end, int blksize, 1292 void (*intr)(void *), void *arg, const audio_params_t *param) 1293 { 1294 struct auich_softc *sc; 1295 struct auich_dma *p; 1296 size_t size; 1297 1298 DPRINTF(ICH_DEBUG_DMA, 1299 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1300 start, end, blksize, intr, arg, param)); 1301 sc = v; 1302 1303 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1304 continue; 1305 if (!p) { 1306 printf("auich_trigger_output: bad addr %p\n", start); 1307 return EINVAL; 1308 } 1309 1310 size = (size_t)((caddr_t)end - (caddr_t)start); 1311 1312 sc->pcmo.intr = intr; 1313 sc->pcmo.arg = arg; 1314 sc->pcmo.start = DMAADDR(p); 1315 sc->pcmo.p = sc->pcmo.start; 1316 sc->pcmo.end = sc->pcmo.start + size; 1317 sc->pcmo.blksize = blksize; 1318 1319 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1320 sc->sc_cddma + ICH_PCMO_OFF(0)); 1321 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1322 1323 return 0; 1324 } 1325 1326 static int 1327 auich_trigger_input(void *v, void *start, void *end, int blksize, 1328 void (*intr)(void *), void *arg, const audio_params_t *param) 1329 { 1330 struct auich_softc *sc; 1331 struct auich_dma *p; 1332 size_t size; 1333 1334 DPRINTF(ICH_DEBUG_DMA, 1335 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1336 start, end, blksize, intr, arg, param)); 1337 sc = v; 1338 1339 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1340 continue; 1341 if (!p) { 1342 printf("auich_trigger_input: bad addr %p\n", start); 1343 return EINVAL; 1344 } 1345 1346 size = (size_t)((caddr_t)end - (caddr_t)start); 1347 1348 sc->pcmi.intr = intr; 1349 sc->pcmi.arg = arg; 1350 sc->pcmi.start = DMAADDR(p); 1351 sc->pcmi.p = sc->pcmi.start; 1352 sc->pcmi.end = sc->pcmi.start + size; 1353 sc->pcmi.blksize = blksize; 1354 1355 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1356 sc->sc_cddma + ICH_PCMI_OFF(0)); 1357 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1358 1359 return 0; 1360 } 1361 1362 static int 1363 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1364 struct auich_dma *p) 1365 { 1366 int error; 1367 1368 p->size = size; 1369 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1370 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1371 &p->nsegs, BUS_DMA_NOWAIT); 1372 if (error) 1373 return error; 1374 1375 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1376 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1377 if (error) 1378 goto free; 1379 1380 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1381 0, BUS_DMA_NOWAIT, &p->map); 1382 if (error) 1383 goto unmap; 1384 1385 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1386 BUS_DMA_NOWAIT); 1387 if (error) 1388 goto destroy; 1389 return 0; 1390 1391 destroy: 1392 bus_dmamap_destroy(sc->dmat, p->map); 1393 unmap: 1394 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1395 free: 1396 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1397 return error; 1398 } 1399 1400 static int 1401 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1402 { 1403 1404 bus_dmamap_unload(sc->dmat, p->map); 1405 bus_dmamap_destroy(sc->dmat, p->map); 1406 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1407 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1408 return 0; 1409 } 1410 1411 static int 1412 auich_alloc_cdata(struct auich_softc *sc) 1413 { 1414 bus_dma_segment_t seg; 1415 int error, rseg; 1416 1417 /* 1418 * Allocate the control data structure, and create and load the 1419 * DMA map for it. 1420 */ 1421 if ((error = bus_dmamem_alloc(sc->dmat, 1422 sizeof(struct auich_cdata), 1423 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1424 printf("%s: unable to allocate control data, error = %d\n", 1425 sc->sc_dev.dv_xname, error); 1426 goto fail_0; 1427 } 1428 1429 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1430 sizeof(struct auich_cdata), 1431 (caddr_t *) &sc->sc_cdata, 1432 sc->sc_dmamap_flags)) != 0) { 1433 printf("%s: unable to map control data, error = %d\n", 1434 sc->sc_dev.dv_xname, error); 1435 goto fail_1; 1436 } 1437 1438 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1439 sizeof(struct auich_cdata), 0, 0, 1440 &sc->sc_cddmamap)) != 0) { 1441 printf("%s: unable to create control data DMA map, " 1442 "error = %d\n", sc->sc_dev.dv_xname, error); 1443 goto fail_2; 1444 } 1445 1446 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1447 sc->sc_cdata, sizeof(struct auich_cdata), 1448 NULL, 0)) != 0) { 1449 printf("%s: unable tp load control data DMA map, " 1450 "error = %d\n", sc->sc_dev.dv_xname, error); 1451 goto fail_3; 1452 } 1453 1454 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1455 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1456 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1457 1458 return 0; 1459 1460 fail_3: 1461 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1462 fail_2: 1463 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1464 sizeof(struct auich_cdata)); 1465 fail_1: 1466 bus_dmamem_free(sc->dmat, &seg, rseg); 1467 fail_0: 1468 return error; 1469 } 1470 1471 static void 1472 auich_powerhook(int why, void *addr) 1473 { 1474 struct auich_softc *sc; 1475 1476 sc = (struct auich_softc *)addr; 1477 switch (why) { 1478 case PWR_SUSPEND: 1479 case PWR_STANDBY: 1480 /* Power down */ 1481 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1482 sc->sc_suspend = why; 1483 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1484 break; 1485 1486 case PWR_RESUME: 1487 /* Wake up */ 1488 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1489 if (sc->sc_suspend == PWR_RESUME) { 1490 printf("%s: resume without suspend.\n", 1491 sc->sc_dev.dv_xname); 1492 sc->sc_suspend = why; 1493 return; 1494 } 1495 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 1496 sc->sc_suspend = why; 1497 auich_reset_codec(sc); 1498 DELAY(1000); 1499 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1500 break; 1501 1502 case PWR_SOFTSUSPEND: 1503 case PWR_SOFTSTANDBY: 1504 case PWR_SOFTRESUME: 1505 break; 1506 } 1507 } 1508 1509 /* 1510 * Calibrate card (some boards are overclocked and need scaling) 1511 */ 1512 static void 1513 auich_calibrate(struct auich_softc *sc) 1514 { 1515 struct timeval t1, t2; 1516 uint8_t ociv, nciv; 1517 uint64_t wait_us; 1518 uint32_t actual_48k_rate, bytes, ac97rate; 1519 void *temp_buffer; 1520 struct auich_dma *p; 1521 u_int rate; 1522 1523 /* 1524 * Grab audio from input for fixed interval and compare how 1525 * much we actually get with what we expect. Interval needs 1526 * to be sufficiently short that no interrupts are 1527 * generated. 1528 */ 1529 1530 /* Force the codec to a known state first. */ 1531 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1532 rate = sc->sc_ac97_clock = 48000; 1533 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1534 &rate); 1535 1536 /* Setup a buffer */ 1537 bytes = 64000; 1538 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1539 1540 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1541 continue; 1542 if (p == NULL) { 1543 printf("auich_calibrate: bad address %p\n", temp_buffer); 1544 return; 1545 } 1546 sc->pcmi.dmalist[0].base = DMAADDR(p); 1547 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1548 1549 /* 1550 * our data format is stereo, 16 bit so each sample is 4 bytes. 1551 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1552 * we're going to start recording with interrupts disabled and measure 1553 * the time taken for one block to complete. we know the block size, 1554 * we know the time in microseconds, we calculate the sample rate: 1555 * 1556 * actual_rate [bps] = bytes / (time [s] * 4) 1557 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1558 * actual_rate [Hz] = (bytes * 250000) / time [us] 1559 */ 1560 1561 /* prepare */ 1562 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1563 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1564 sc->sc_cddma + ICH_PCMI_OFF(0)); 1565 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1566 (0 - 1) & ICH_LVI_MASK); 1567 1568 /* start */ 1569 microtime(&t1); 1570 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1571 1572 /* wait */ 1573 nciv = ociv; 1574 do { 1575 microtime(&t2); 1576 if (t2.tv_sec - t1.tv_sec > 1) 1577 break; 1578 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1579 ICH_PCMI + ICH_CIV); 1580 } while (nciv == ociv); 1581 microtime(&t2); 1582 1583 /* stop */ 1584 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1585 1586 /* reset */ 1587 DELAY(100); 1588 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1589 1590 /* turn time delta into us */ 1591 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1592 1593 auich_freem(sc, temp_buffer, M_DEVBUF); 1594 1595 if (nciv == ociv) { 1596 printf("%s: ac97 link rate calibration timed out after %" 1597 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1598 return; 1599 } 1600 1601 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1602 1603 if (actual_48k_rate < 50000) 1604 ac97rate = 48000; 1605 else 1606 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1607 1608 printf("%s: measured ac97 link rate at %d Hz", 1609 sc->sc_dev.dv_xname, actual_48k_rate); 1610 if (ac97rate != actual_48k_rate) 1611 printf(", will use %d Hz", ac97rate); 1612 printf("\n"); 1613 1614 sc->sc_ac97_clock = ac97rate; 1615 } 1616
Indexes created Thu Oct 23 22:10:10 GMT 2025