autri.c revision 1.3.2.7
1 1.3.2.7 thorpej /* $NetBSD: autri.c,v 1.3.2.7 2003/01/07 21:34:37 thorpej Exp $ */ 2 1.3.2.2 nathanw 3 1.3.2.2 nathanw /* 4 1.3.2.2 nathanw * Copyright (c) 2001 SOMEYA Yoshihiko and KUROSAWA Takahiro. 5 1.3.2.2 nathanw * All rights reserved. 6 1.3.2.2 nathanw * 7 1.3.2.2 nathanw * Redistribution and use in source and binary forms, with or without 8 1.3.2.2 nathanw * modification, are permitted provided that the following conditions 9 1.3.2.2 nathanw * are met: 10 1.3.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 11 1.3.2.2 nathanw * notice, this list of conditions and the following disclaimer. 12 1.3.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 13 1.3.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 14 1.3.2.2 nathanw * documentation and/or other materials provided with the distribution. 15 1.3.2.2 nathanw * 16 1.3.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.3.2.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.3.2.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.3.2.2 nathanw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.3.2.2 nathanw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 1.3.2.2 nathanw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 1.3.2.2 nathanw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 1.3.2.2 nathanw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 1.3.2.2 nathanw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 1.3.2.2 nathanw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 1.3.2.2 nathanw */ 27 1.3.2.2 nathanw 28 1.3.2.2 nathanw /* 29 1.3.2.2 nathanw * Trident 4DWAVE-DX/NX, SiS 7018, ALi M5451 Sound Driver 30 1.3.2.2 nathanw * 31 1.3.2.2 nathanw * The register information is taken from the ALSA driver. 32 1.3.2.2 nathanw * 33 1.3.2.2 nathanw * Documentation links: 34 1.3.2.2 nathanw * - ftp://ftp.alsa-project.org/pub/manuals/trident/ 35 1.3.2.2 nathanw */ 36 1.3.2.2 nathanw 37 1.3.2.2 nathanw #include "midi.h" 38 1.3.2.2 nathanw 39 1.3.2.2 nathanw #include <sys/param.h> 40 1.3.2.2 nathanw #include <sys/systm.h> 41 1.3.2.2 nathanw #include <sys/kernel.h> 42 1.3.2.2 nathanw #include <sys/fcntl.h> 43 1.3.2.2 nathanw #include <sys/malloc.h> 44 1.3.2.2 nathanw #include <sys/device.h> 45 1.3.2.2 nathanw #include <sys/proc.h> 46 1.3.2.2 nathanw 47 1.3.2.2 nathanw #include <dev/pci/pcidevs.h> 48 1.3.2.2 nathanw #include <dev/pci/pcireg.h> 49 1.3.2.2 nathanw #include <dev/pci/pcivar.h> 50 1.3.2.2 nathanw 51 1.3.2.2 nathanw #include <sys/audioio.h> 52 1.3.2.2 nathanw #include <dev/audio_if.h> 53 1.3.2.2 nathanw #include <dev/midi_if.h> 54 1.3.2.2 nathanw #include <dev/mulaw.h> 55 1.3.2.2 nathanw #include <dev/auconv.h> 56 1.3.2.2 nathanw #include <dev/ic/ac97reg.h> 57 1.3.2.2 nathanw #include <dev/ic/ac97var.h> 58 1.3.2.2 nathanw #include <dev/ic/mpuvar.h> 59 1.3.2.2 nathanw 60 1.3.2.2 nathanw #include <machine/bus.h> 61 1.3.2.2 nathanw #include <machine/intr.h> 62 1.3.2.2 nathanw 63 1.3.2.2 nathanw #include <dev/pci/autrireg.h> 64 1.3.2.2 nathanw #include <dev/pci/autrivar.h> 65 1.3.2.2 nathanw 66 1.3.2.2 nathanw #ifdef AUDIO_DEBUG 67 1.3.2.2 nathanw # define DPRINTF(x) if (autridebug) printf x 68 1.3.2.2 nathanw # define DPRINTFN(n,x) if (autridebug > (n)) printf x 69 1.3.2.2 nathanw int autridebug = 0; 70 1.3.2.2 nathanw #else 71 1.3.2.2 nathanw # define DPRINTF(x) 72 1.3.2.2 nathanw # define DPRINTFN(n,x) 73 1.3.2.2 nathanw #endif 74 1.3.2.2 nathanw 75 1.3.2.2 nathanw int autri_match(struct device *, struct cfdata *, void *); 76 1.3.2.2 nathanw void autri_attach(struct device *, struct device *, void *); 77 1.3.2.2 nathanw int autri_intr(void *); 78 1.3.2.2 nathanw 79 1.3.2.2 nathanw #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 80 1.3.2.2 nathanw #define KERNADDR(p) ((void *)((p)->addr)) 81 1.3.2.2 nathanw 82 1.3.2.2 nathanw int autri_allocmem(struct autri_softc *, size_t, 83 1.3.2.2 nathanw size_t, struct autri_dma *); 84 1.3.2.2 nathanw int autri_freemem(struct autri_softc *, struct autri_dma *); 85 1.3.2.2 nathanw 86 1.3.2.2 nathanw #define TWRITE1(sc, r, x) bus_space_write_1((sc)->memt, (sc)->memh, (r), (x)) 87 1.3.2.2 nathanw #define TWRITE2(sc, r, x) bus_space_write_2((sc)->memt, (sc)->memh, (r), (x)) 88 1.3.2.2 nathanw #define TWRITE4(sc, r, x) bus_space_write_4((sc)->memt, (sc)->memh, (r), (x)) 89 1.3.2.2 nathanw #define TREAD1(sc, r) bus_space_read_1((sc)->memt, (sc)->memh, (r)) 90 1.3.2.2 nathanw #define TREAD2(sc, r) bus_space_read_2((sc)->memt, (sc)->memh, (r)) 91 1.3.2.2 nathanw #define TREAD4(sc, r) bus_space_read_4((sc)->memt, (sc)->memh, (r)) 92 1.3.2.2 nathanw 93 1.3.2.2 nathanw static __inline void autri_reg_set_1(struct autri_softc *, int, uint8_t); 94 1.3.2.2 nathanw static __inline void autri_reg_clear_1(struct autri_softc *, int, uint8_t); 95 1.3.2.2 nathanw static __inline void autri_reg_set_4(struct autri_softc *, int, uint32_t); 96 1.3.2.2 nathanw static __inline void autri_reg_clear_4(struct autri_softc *, int, uint32_t); 97 1.3.2.2 nathanw 98 1.3.2.2 nathanw int autri_attach_codec(void *sc, struct ac97_codec_if *); 99 1.3.2.2 nathanw int autri_read_codec(void *sc, u_int8_t a, u_int16_t *d); 100 1.3.2.2 nathanw int autri_write_codec(void *sc, u_int8_t a, u_int16_t d); 101 1.3.2.2 nathanw void autri_reset_codec(void *sc); 102 1.3.2.5 nathanw enum ac97_host_flags autri_flags_codec(void *sc); 103 1.3.2.2 nathanw 104 1.3.2.2 nathanw static void autri_powerhook(int why,void *addr); 105 1.3.2.2 nathanw static int autri_init(void *sc); 106 1.3.2.2 nathanw static struct autri_dma *autri_find_dma(struct autri_softc *, void *); 107 1.3.2.2 nathanw static void autri_setup_channel(struct autri_softc *sc,int mode, 108 1.3.2.2 nathanw struct audio_params *param); 109 1.3.2.2 nathanw static void autri_enable_interrupt(struct autri_softc *sc, int ch); 110 1.3.2.2 nathanw static void autri_disable_interrupt(struct autri_softc *sc, int ch); 111 1.3.2.2 nathanw static void autri_startch(struct autri_softc *sc, int ch, int ch_intr); 112 1.3.2.2 nathanw static void autri_stopch(struct autri_softc *sc, int ch, int ch_intr); 113 1.3.2.2 nathanw static void autri_enable_loop_interrupt(void *sc); 114 1.3.2.2 nathanw #if 0 115 1.3.2.2 nathanw static void autri_disable_loop_interrupt(void *sc); 116 1.3.2.2 nathanw #endif 117 1.3.2.2 nathanw 118 1.3.2.5 nathanw CFATTACH_DECL(autri, sizeof(struct autri_softc), 119 1.3.2.5 nathanw autri_match, autri_attach, NULL, NULL); 120 1.3.2.2 nathanw 121 1.3.2.2 nathanw int autri_open(void *, int); 122 1.3.2.2 nathanw void autri_close(void *); 123 1.3.2.2 nathanw int autri_query_encoding(void *, struct audio_encoding *); 124 1.3.2.2 nathanw int autri_set_params(void *, int, int, 125 1.3.2.2 nathanw struct audio_params *, struct audio_params *); 126 1.3.2.2 nathanw int autri_round_blocksize(void *, int); 127 1.3.2.2 nathanw int autri_trigger_output(void *, void *, void *, int, void (*)(void *), 128 1.3.2.2 nathanw void *, struct audio_params *); 129 1.3.2.2 nathanw int autri_trigger_input(void *, void *, void *, int, void (*)(void *), 130 1.3.2.2 nathanw void *, struct audio_params *); 131 1.3.2.2 nathanw int autri_halt_output(void *); 132 1.3.2.2 nathanw int autri_halt_input(void *); 133 1.3.2.2 nathanw int autri_getdev(void *, struct audio_device *); 134 1.3.2.2 nathanw int autri_mixer_set_port(void *, mixer_ctrl_t *); 135 1.3.2.2 nathanw int autri_mixer_get_port(void *, mixer_ctrl_t *); 136 1.3.2.2 nathanw void* autri_malloc(void *, int, size_t, int, int); 137 1.3.2.2 nathanw void autri_free(void *, void *, int); 138 1.3.2.2 nathanw size_t autri_round_buffersize(void *, int, size_t); 139 1.3.2.2 nathanw paddr_t autri_mappage(void *, void *, off_t, int); 140 1.3.2.2 nathanw int autri_get_props(void *); 141 1.3.2.2 nathanw int autri_query_devinfo(void *addr, mixer_devinfo_t *dip); 142 1.3.2.2 nathanw 143 1.3.2.2 nathanw int autri_get_portnum_by_name(struct autri_softc *, char *, char *, char *); 144 1.3.2.2 nathanw 145 1.3.2.2 nathanw static struct audio_hw_if autri_hw_if = { 146 1.3.2.2 nathanw autri_open, 147 1.3.2.2 nathanw autri_close, 148 1.3.2.2 nathanw NULL, /* drain */ 149 1.3.2.2 nathanw autri_query_encoding, 150 1.3.2.2 nathanw autri_set_params, 151 1.3.2.2 nathanw autri_round_blocksize, 152 1.3.2.2 nathanw NULL, /* commit_settings */ 153 1.3.2.2 nathanw NULL, /* init_output */ 154 1.3.2.2 nathanw NULL, /* init_input */ 155 1.3.2.2 nathanw NULL, /* start_output */ 156 1.3.2.2 nathanw NULL, /* start_input */ 157 1.3.2.2 nathanw autri_halt_output, 158 1.3.2.2 nathanw autri_halt_input, 159 1.3.2.2 nathanw NULL, /* speaker_ctl */ 160 1.3.2.2 nathanw autri_getdev, 161 1.3.2.2 nathanw NULL, /* setfd */ 162 1.3.2.2 nathanw autri_mixer_set_port, 163 1.3.2.2 nathanw autri_mixer_get_port, 164 1.3.2.2 nathanw autri_query_devinfo, 165 1.3.2.2 nathanw autri_malloc, 166 1.3.2.2 nathanw autri_free, 167 1.3.2.2 nathanw autri_round_buffersize, 168 1.3.2.2 nathanw autri_mappage, 169 1.3.2.2 nathanw autri_get_props, 170 1.3.2.2 nathanw autri_trigger_output, 171 1.3.2.2 nathanw autri_trigger_input, 172 1.3.2.2 nathanw NULL, /* dev_ioctl */ 173 1.3.2.2 nathanw }; 174 1.3.2.2 nathanw 175 1.3.2.2 nathanw #if NMIDI > 0 176 1.3.2.2 nathanw void autri_midi_close(void *); 177 1.3.2.2 nathanw void autri_midi_getinfo(void *, struct midi_info *); 178 1.3.2.2 nathanw int autri_midi_open(void *, int, void (*)(void *, int), 179 1.3.2.2 nathanw void (*)(void *), void *); 180 1.3.2.2 nathanw int autri_midi_output(void *, int); 181 1.3.2.2 nathanw 182 1.3.2.2 nathanw struct midi_hw_if autri_midi_hw_if = { 183 1.3.2.2 nathanw autri_midi_open, 184 1.3.2.2 nathanw autri_midi_close, 185 1.3.2.2 nathanw autri_midi_output, 186 1.3.2.2 nathanw autri_midi_getinfo, 187 1.3.2.2 nathanw NULL, /* ioctl */ 188 1.3.2.2 nathanw }; 189 1.3.2.2 nathanw #endif 190 1.3.2.2 nathanw 191 1.3.2.2 nathanw /* 192 1.3.2.2 nathanw * register set/clear bit 193 1.3.2.2 nathanw */ 194 1.3.2.2 nathanw static __inline void 195 1.3.2.2 nathanw autri_reg_set_1(struct autri_softc *sc, int no, uint8_t mask) 196 1.3.2.2 nathanw { 197 1.3.2.2 nathanw bus_space_write_1(sc->memt, sc->memh, no, 198 1.3.2.2 nathanw (bus_space_read_1(sc->memt, sc->memh, no) | mask)); 199 1.3.2.2 nathanw } 200 1.3.2.2 nathanw 201 1.3.2.2 nathanw static __inline void 202 1.3.2.2 nathanw autri_reg_clear_1(struct autri_softc *sc, int no, uint8_t mask) 203 1.3.2.2 nathanw { 204 1.3.2.2 nathanw bus_space_write_1(sc->memt, sc->memh, no, 205 1.3.2.2 nathanw (bus_space_read_1(sc->memt, sc->memh, no) & ~mask)); 206 1.3.2.2 nathanw } 207 1.3.2.2 nathanw 208 1.3.2.2 nathanw static __inline void 209 1.3.2.2 nathanw autri_reg_set_4(struct autri_softc *sc, int no, uint32_t mask) 210 1.3.2.2 nathanw { 211 1.3.2.2 nathanw bus_space_write_4(sc->memt, sc->memh, no, 212 1.3.2.2 nathanw (bus_space_read_4(sc->memt, sc->memh, no) | mask)); 213 1.3.2.2 nathanw } 214 1.3.2.2 nathanw 215 1.3.2.2 nathanw static __inline void 216 1.3.2.2 nathanw autri_reg_clear_4(struct autri_softc *sc, int no, uint32_t mask) 217 1.3.2.2 nathanw { 218 1.3.2.2 nathanw bus_space_write_4(sc->memt, sc->memh, no, 219 1.3.2.2 nathanw (bus_space_read_4(sc->memt, sc->memh, no) & ~mask)); 220 1.3.2.2 nathanw } 221 1.3.2.2 nathanw 222 1.3.2.2 nathanw /* 223 1.3.2.2 nathanw * AC'97 codec 224 1.3.2.2 nathanw */ 225 1.3.2.2 nathanw int 226 1.3.2.2 nathanw autri_attach_codec(void *sc_, struct ac97_codec_if *codec_if) 227 1.3.2.2 nathanw { 228 1.3.2.2 nathanw struct autri_codec_softc *sc = sc_; 229 1.3.2.2 nathanw 230 1.3.2.2 nathanw DPRINTF(("autri_attach_codec()\n")); 231 1.3.2.2 nathanw 232 1.3.2.2 nathanw sc->codec_if = codec_if; 233 1.3.2.2 nathanw return 0; 234 1.3.2.2 nathanw } 235 1.3.2.2 nathanw 236 1.3.2.2 nathanw int 237 1.3.2.2 nathanw autri_read_codec(void *sc_, u_int8_t index, u_int16_t *data) 238 1.3.2.2 nathanw { 239 1.3.2.2 nathanw struct autri_codec_softc *codec = sc_; 240 1.3.2.2 nathanw struct autri_softc *sc = codec->sc; 241 1.3.2.2 nathanw u_int32_t status, addr, cmd, busy; 242 1.3.2.2 nathanw u_int16_t count; 243 1.3.2.2 nathanw 244 1.3.2.2 nathanw /*DPRINTF(("sc->sc->type : 0x%X",sc->sc->type));*/ 245 1.3.2.2 nathanw 246 1.3.2.2 nathanw switch (sc->sc_devid) { 247 1.3.2.2 nathanw case AUTRI_DEVICE_ID_4DWAVE_DX: 248 1.3.2.2 nathanw addr = AUTRI_DX_ACR1; 249 1.3.2.2 nathanw cmd = AUTRI_DX_ACR1_CMD_READ; 250 1.3.2.2 nathanw busy = AUTRI_DX_ACR1_BUSY_READ; 251 1.3.2.2 nathanw break; 252 1.3.2.2 nathanw case AUTRI_DEVICE_ID_4DWAVE_NX: 253 1.3.2.2 nathanw addr = AUTRI_NX_ACR2; 254 1.3.2.2 nathanw cmd = AUTRI_NX_ACR2_CMD_READ; 255 1.3.2.2 nathanw busy = AUTRI_NX_ACR2_BUSY_READ | AUTRI_NX_ACR2_RECV_WAIT; 256 1.3.2.2 nathanw break; 257 1.3.2.2 nathanw case AUTRI_DEVICE_ID_SIS_7018: 258 1.3.2.2 nathanw addr = AUTRI_SIS_ACRD; 259 1.3.2.2 nathanw cmd = AUTRI_SIS_ACRD_CMD_READ; 260 1.3.2.2 nathanw busy = AUTRI_SIS_ACRD_BUSY_READ | AUTRI_SIS_ACRD_AUDIO_BUSY; 261 1.3.2.2 nathanw break; 262 1.3.2.2 nathanw case AUTRI_DEVICE_ID_ALI_M5451: 263 1.3.2.2 nathanw if (sc->sc_revision > 0x01) 264 1.3.2.2 nathanw addr = AUTRI_ALI_ACWR; 265 1.3.2.2 nathanw else 266 1.3.2.2 nathanw addr = AUTRI_ALI_ACRD; 267 1.3.2.2 nathanw cmd = AUTRI_ALI_ACRD_CMD_READ; 268 1.3.2.2 nathanw busy = AUTRI_ALI_ACRD_BUSY_READ; 269 1.3.2.2 nathanw break; 270 1.3.2.2 nathanw default: 271 1.3.2.2 nathanw printf("%s: autri_read_codec : unknown device\n", 272 1.3.2.2 nathanw sc->sc_dev.dv_xname); 273 1.3.2.2 nathanw return -1; 274 1.3.2.2 nathanw } 275 1.3.2.2 nathanw 276 1.3.2.2 nathanw /* wait for 'Ready to Read' */ 277 1.3.2.2 nathanw for (count=0; count<0xffff; count++) { 278 1.3.2.2 nathanw if ((TREAD4(sc, addr) & busy) == 0) 279 1.3.2.2 nathanw break; 280 1.3.2.2 nathanw } 281 1.3.2.2 nathanw 282 1.3.2.2 nathanw if (count == 0xffff) { 283 1.3.2.2 nathanw printf("%s: Codec timeout. Busy reading AC'97 codec.\n", 284 1.3.2.2 nathanw sc->sc_dev.dv_xname); 285 1.3.2.2 nathanw return -1; 286 1.3.2.2 nathanw } 287 1.3.2.2 nathanw 288 1.3.2.2 nathanw /* send Read Command to AC'97 */ 289 1.3.2.2 nathanw TWRITE4(sc, addr, (index & 0x7f) | cmd); 290 1.3.2.2 nathanw 291 1.3.2.2 nathanw /* wait for 'Returned data is avalable' */ 292 1.3.2.2 nathanw for (count=0; count<0xffff; count++) { 293 1.3.2.2 nathanw status = TREAD4(sc, addr); 294 1.3.2.2 nathanw if ((status & busy) == 0) 295 1.3.2.2 nathanw break; 296 1.3.2.2 nathanw } 297 1.3.2.2 nathanw 298 1.3.2.2 nathanw if (count == 0xffff) { 299 1.3.2.2 nathanw printf("%s: Codec timeout. Busy reading AC'97 codec.\n", 300 1.3.2.2 nathanw sc->sc_dev.dv_xname); 301 1.3.2.2 nathanw return -1; 302 1.3.2.2 nathanw } 303 1.3.2.2 nathanw 304 1.3.2.2 nathanw *data = (status >> 16) & 0x0000ffff; 305 1.3.2.2 nathanw /*DPRINTF(("autri_read_codec(0x%X) return 0x%X\n",reg,*data));*/ 306 1.3.2.2 nathanw return 0; 307 1.3.2.2 nathanw } 308 1.3.2.2 nathanw 309 1.3.2.2 nathanw int 310 1.3.2.2 nathanw autri_write_codec(void *sc_, u_int8_t index, u_int16_t data) 311 1.3.2.2 nathanw { 312 1.3.2.2 nathanw struct autri_codec_softc *codec = sc_; 313 1.3.2.2 nathanw struct autri_softc *sc = codec->sc; 314 1.3.2.2 nathanw u_int32_t addr, cmd, busy; 315 1.3.2.2 nathanw u_int16_t count; 316 1.3.2.2 nathanw 317 1.3.2.2 nathanw /*DPRINTF(("autri_write_codec(0x%X,0x%X)\n",index,data));*/ 318 1.3.2.2 nathanw 319 1.3.2.2 nathanw switch (sc->sc_devid) { 320 1.3.2.2 nathanw case AUTRI_DEVICE_ID_4DWAVE_DX: 321 1.3.2.2 nathanw addr = AUTRI_DX_ACR0; 322 1.3.2.2 nathanw cmd = AUTRI_DX_ACR0_CMD_WRITE; 323 1.3.2.2 nathanw busy = AUTRI_DX_ACR0_BUSY_WRITE; 324 1.3.2.2 nathanw break; 325 1.3.2.2 nathanw case AUTRI_DEVICE_ID_4DWAVE_NX: 326 1.3.2.2 nathanw addr = AUTRI_NX_ACR1; 327 1.3.2.2 nathanw cmd = AUTRI_NX_ACR1_CMD_WRITE; 328 1.3.2.2 nathanw busy = AUTRI_NX_ACR1_BUSY_WRITE; 329 1.3.2.2 nathanw break; 330 1.3.2.2 nathanw case AUTRI_DEVICE_ID_SIS_7018: 331 1.3.2.2 nathanw addr = AUTRI_SIS_ACWR; 332 1.3.2.2 nathanw cmd = AUTRI_SIS_ACWR_CMD_WRITE; 333 1.3.2.2 nathanw busy = AUTRI_SIS_ACWR_BUSY_WRITE | AUTRI_SIS_ACWR_AUDIO_BUSY; 334 1.3.2.2 nathanw break; 335 1.3.2.2 nathanw case AUTRI_DEVICE_ID_ALI_M5451: 336 1.3.2.2 nathanw addr = AUTRI_ALI_ACWR; 337 1.3.2.2 nathanw cmd = AUTRI_ALI_ACWR_CMD_WRITE; 338 1.3.2.2 nathanw if (sc->sc_revision > 0x01) 339 1.3.2.2 nathanw cmd |= 0x0100; 340 1.3.2.2 nathanw busy = AUTRI_ALI_ACWR_BUSY_WRITE; 341 1.3.2.2 nathanw break; 342 1.3.2.2 nathanw default: 343 1.3.2.2 nathanw printf("%s: autri_write_codec : unknown device.\n", 344 1.3.2.2 nathanw sc->sc_dev.dv_xname); 345 1.3.2.2 nathanw return -1; 346 1.3.2.2 nathanw } 347 1.3.2.2 nathanw 348 1.3.2.2 nathanw /* wait for 'Ready to Write' */ 349 1.3.2.2 nathanw for (count=0; count<0xffff; count++) { 350 1.3.2.2 nathanw if ((TREAD4(sc, addr) & busy) == 0) 351 1.3.2.2 nathanw break; 352 1.3.2.2 nathanw } 353 1.3.2.2 nathanw 354 1.3.2.2 nathanw if (count == 0xffff) { 355 1.3.2.2 nathanw printf("%s: Codec timeout. Busy writing AC'97 codec\n", 356 1.3.2.2 nathanw sc->sc_dev.dv_xname); 357 1.3.2.2 nathanw return -1; 358 1.3.2.2 nathanw } 359 1.3.2.2 nathanw 360 1.3.2.2 nathanw /* send Write Command to AC'97 */ 361 1.3.2.2 nathanw TWRITE4(sc, addr, (data << 16) | (index & 0x7f) | cmd); 362 1.3.2.2 nathanw 363 1.3.2.2 nathanw return 0; 364 1.3.2.2 nathanw } 365 1.3.2.2 nathanw 366 1.3.2.2 nathanw void 367 1.3.2.2 nathanw autri_reset_codec(void *sc_) 368 1.3.2.2 nathanw { 369 1.3.2.2 nathanw struct autri_codec_softc *codec = sc_; 370 1.3.2.2 nathanw struct autri_softc *sc = codec->sc; 371 1.3.2.2 nathanw u_int32_t reg, ready; 372 1.3.2.2 nathanw int addr, count = 200; 373 1.3.2.2 nathanw 374 1.3.2.2 nathanw DPRINTF(("autri_reset_codec(codec=%p,sc=%p)\n",codec,sc)); 375 1.3.2.2 nathanw DPRINTF(("sc->sc_devid=%X\n",sc->sc_devid)); 376 1.3.2.2 nathanw 377 1.3.2.3 nathanw switch (sc->sc_devid) { 378 1.3.2.2 nathanw case AUTRI_DEVICE_ID_4DWAVE_DX: 379 1.3.2.2 nathanw /* warm reset AC'97 codec */ 380 1.3.2.2 nathanw autri_reg_set_4(sc, AUTRI_DX_ACR2, 1); 381 1.3.2.2 nathanw delay(100); 382 1.3.2.2 nathanw /* release reset */ 383 1.3.2.2 nathanw autri_reg_clear_4(sc, AUTRI_DX_ACR2, 1); 384 1.3.2.2 nathanw delay(100); 385 1.3.2.2 nathanw 386 1.3.2.2 nathanw addr = AUTRI_DX_ACR2; 387 1.3.2.2 nathanw ready = AUTRI_DX_ACR2_CODEC_READY; 388 1.3.2.2 nathanw break; 389 1.3.2.2 nathanw case AUTRI_DEVICE_ID_4DWAVE_NX: 390 1.3.2.2 nathanw /* warm reset AC'97 codec */ 391 1.3.2.2 nathanw autri_reg_set_4(sc, AUTRI_NX_ACR0, 1); 392 1.3.2.2 nathanw delay(100); 393 1.3.2.2 nathanw /* release reset */ 394 1.3.2.2 nathanw autri_reg_clear_4(sc, AUTRI_NX_ACR0, 1); 395 1.3.2.2 nathanw delay(100); 396 1.3.2.2 nathanw 397 1.3.2.2 nathanw addr = AUTRI_NX_ACR0; 398 1.3.2.2 nathanw ready = AUTRI_NX_ACR0_CODEC_READY; 399 1.3.2.2 nathanw break; 400 1.3.2.2 nathanw case AUTRI_DEVICE_ID_SIS_7018: 401 1.3.2.4 nathanw /* cold reset AC'97 codec */ 402 1.3.2.4 nathanw autri_reg_set_4(sc, AUTRI_SIS_SCTRL, 2); 403 1.3.2.4 nathanw delay(1000); 404 1.3.2.2 nathanw /* release reset (warm & cold) */ 405 1.3.2.2 nathanw autri_reg_clear_4(sc, AUTRI_SIS_SCTRL, 3); 406 1.3.2.4 nathanw delay(2000); 407 1.3.2.2 nathanw 408 1.3.2.2 nathanw addr = AUTRI_SIS_SCTRL; 409 1.3.2.2 nathanw ready = AUTRI_SIS_SCTRL_CODEC_READY; 410 1.3.2.2 nathanw break; 411 1.3.2.2 nathanw case AUTRI_DEVICE_ID_ALI_M5451: 412 1.3.2.2 nathanw /* warm reset AC'97 codec */ 413 1.3.2.2 nathanw autri_reg_set_4(sc, AUTRI_ALI_SCTRL, 1); 414 1.3.2.2 nathanw delay(100); 415 1.3.2.2 nathanw /* release reset (warm & cold) */ 416 1.3.2.2 nathanw autri_reg_clear_4(sc, AUTRI_ALI_SCTRL, 3); 417 1.3.2.2 nathanw delay(100); 418 1.3.2.2 nathanw 419 1.3.2.2 nathanw addr = AUTRI_ALI_SCTRL; 420 1.3.2.2 nathanw ready = AUTRI_ALI_SCTRL_CODEC_READY; 421 1.3.2.2 nathanw break; 422 1.3.2.2 nathanw } 423 1.3.2.2 nathanw 424 1.3.2.2 nathanw /* wait for 'Codec Ready' */ 425 1.3.2.2 nathanw while (count--) { 426 1.3.2.2 nathanw reg = TREAD4(sc, addr); 427 1.3.2.2 nathanw if (reg & ready) 428 1.3.2.2 nathanw break; 429 1.3.2.2 nathanw delay(1000); 430 1.3.2.2 nathanw } 431 1.3.2.2 nathanw 432 1.3.2.2 nathanw if (count == 0) 433 1.3.2.2 nathanw printf("%s: Codec timeout. AC'97 is not ready for operation.\n", 434 1.3.2.2 nathanw sc->sc_dev.dv_xname); 435 1.3.2.2 nathanw } 436 1.3.2.2 nathanw 437 1.3.2.5 nathanw enum ac97_host_flags 438 1.3.2.5 nathanw autri_flags_codec(void *sc_) 439 1.3.2.5 nathanw { 440 1.3.2.5 nathanw return AC97_HOST_DONT_READ; 441 1.3.2.5 nathanw } 442 1.3.2.5 nathanw 443 1.3.2.2 nathanw /* 444 1.3.2.2 nathanw * 445 1.3.2.2 nathanw */ 446 1.3.2.2 nathanw 447 1.3.2.2 nathanw int 448 1.3.2.2 nathanw autri_match(struct device *parent, struct cfdata *match, void *aux) 449 1.3.2.2 nathanw { 450 1.3.2.2 nathanw struct pci_attach_args *pa = (struct pci_attach_args *) aux; 451 1.3.2.2 nathanw 452 1.3.2.2 nathanw switch (PCI_VENDOR(pa->pa_id)) { 453 1.3.2.2 nathanw case PCI_VENDOR_TRIDENT: 454 1.3.2.2 nathanw switch (PCI_PRODUCT(pa->pa_id)) { 455 1.3.2.2 nathanw case PCI_PRODUCT_TRIDENT_4DWAVE_DX: 456 1.3.2.2 nathanw case PCI_PRODUCT_TRIDENT_4DWAVE_NX: 457 1.3.2.2 nathanw return 1; 458 1.3.2.2 nathanw } 459 1.3.2.2 nathanw break; 460 1.3.2.2 nathanw case PCI_VENDOR_SIS: 461 1.3.2.2 nathanw switch (PCI_PRODUCT(pa->pa_id)) { 462 1.3.2.2 nathanw case PCI_PRODUCT_SIS_7018: 463 1.3.2.2 nathanw return 1; 464 1.3.2.2 nathanw } 465 1.3.2.2 nathanw break; 466 1.3.2.2 nathanw case PCI_VENDOR_ALI: 467 1.3.2.2 nathanw switch (PCI_PRODUCT(pa->pa_id)) { 468 1.3.2.2 nathanw case PCI_PRODUCT_ALI_M5451: 469 1.3.2.2 nathanw return 1; 470 1.3.2.2 nathanw } 471 1.3.2.2 nathanw break; 472 1.3.2.2 nathanw } 473 1.3.2.2 nathanw 474 1.3.2.2 nathanw return 0; 475 1.3.2.2 nathanw } 476 1.3.2.2 nathanw 477 1.3.2.2 nathanw void 478 1.3.2.2 nathanw autri_attach(struct device *parent, struct device *self, void *aux) 479 1.3.2.2 nathanw { 480 1.3.2.2 nathanw struct autri_softc *sc = (struct autri_softc *)self; 481 1.3.2.2 nathanw struct pci_attach_args *pa = (struct pci_attach_args *)aux; 482 1.3.2.2 nathanw pci_chipset_tag_t pc = pa->pa_pc; 483 1.3.2.2 nathanw struct autri_codec_softc *codec; 484 1.3.2.2 nathanw pci_intr_handle_t ih; 485 1.3.2.2 nathanw char const *intrstr; 486 1.3.2.2 nathanw char devinfo[256]; 487 1.3.2.2 nathanw mixer_ctrl_t ctl; 488 1.3.2.2 nathanw int i, r; 489 1.3.2.2 nathanw u_int32_t reg; 490 1.3.2.2 nathanw 491 1.3.2.2 nathanw sc->sc_devid = pa->pa_id; 492 1.3.2.2 nathanw sc->sc_class = pa->pa_class; 493 1.3.2.2 nathanw 494 1.3.2.2 nathanw pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 495 1.3.2.2 nathanw sc->sc_revision = PCI_REVISION(pa->pa_class); 496 1.3.2.2 nathanw printf(": %s (rev. 0x%02x)\n", devinfo, sc->sc_revision); 497 1.3.2.2 nathanw 498 1.3.2.2 nathanw /* map register to memory */ 499 1.3.2.2 nathanw if (pci_mapreg_map(pa, AUTRI_PCI_MEMORY_BASE, 500 1.3.2.2 nathanw PCI_MAPREG_TYPE_MEM, 0, &sc->memt, &sc->memh, NULL, NULL)) { 501 1.3.2.2 nathanw printf("%s: can't map memory space\n", sc->sc_dev.dv_xname); 502 1.3.2.2 nathanw return; 503 1.3.2.2 nathanw } 504 1.3.2.2 nathanw 505 1.3.2.2 nathanw /* map and establish the interrupt */ 506 1.3.2.2 nathanw if (pci_intr_map(pa, &ih)) { 507 1.3.2.2 nathanw printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 508 1.3.2.2 nathanw return; 509 1.3.2.2 nathanw } 510 1.3.2.2 nathanw intrstr = pci_intr_string(pc, ih); 511 1.3.2.2 nathanw sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, autri_intr, sc); 512 1.3.2.2 nathanw if (sc->sc_ih == NULL) { 513 1.3.2.2 nathanw printf("%s: couldn't establish interrupt", 514 1.3.2.2 nathanw sc->sc_dev.dv_xname); 515 1.3.2.2 nathanw if (intrstr != NULL) 516 1.3.2.2 nathanw printf(" at %s", intrstr); 517 1.3.2.2 nathanw printf("\n"); 518 1.3.2.2 nathanw return; 519 1.3.2.2 nathanw } 520 1.3.2.2 nathanw printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 521 1.3.2.2 nathanw 522 1.3.2.2 nathanw sc->sc_dmatag = pa->pa_dmat; 523 1.3.2.2 nathanw sc->sc_pc = pc; 524 1.3.2.2 nathanw sc->sc_pt = pa->pa_tag; 525 1.3.2.2 nathanw 526 1.3.2.2 nathanw /* enable the device */ 527 1.3.2.2 nathanw reg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 528 1.3.2.2 nathanw reg |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE); 529 1.3.2.2 nathanw pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 530 1.3.2.2 nathanw 531 1.3.2.2 nathanw /* initialize the device */ 532 1.3.2.2 nathanw autri_init(sc); 533 1.3.2.2 nathanw 534 1.3.2.2 nathanw /* attach AC'97 codec */ 535 1.3.2.2 nathanw codec = &sc->sc_codec; 536 1.3.2.2 nathanw memcpy(&codec->sc_dev, &sc->sc_dev, sizeof(codec->sc_dev)); 537 1.3.2.2 nathanw codec->sc = sc; 538 1.3.2.2 nathanw 539 1.3.2.2 nathanw codec->host_if.arg = codec; 540 1.3.2.2 nathanw codec->host_if.attach = autri_attach_codec; 541 1.3.2.2 nathanw codec->host_if.reset = autri_reset_codec; 542 1.3.2.2 nathanw codec->host_if.read = autri_read_codec; 543 1.3.2.2 nathanw codec->host_if.write = autri_write_codec; 544 1.3.2.5 nathanw codec->host_if.flags = autri_flags_codec; 545 1.3.2.2 nathanw 546 1.3.2.2 nathanw if ((r = ac97_attach(&codec->host_if)) != 0) { 547 1.3.2.2 nathanw printf("%s: can't attach codec (error 0x%X)\n", 548 1.3.2.2 nathanw sc->sc_dev.dv_xname, r); 549 1.3.2.2 nathanw return; 550 1.3.2.2 nathanw } 551 1.3.2.2 nathanw 552 1.3.2.2 nathanw /* disable mutes */ 553 1.3.2.2 nathanw for (i = 0; i < 4; i++) { 554 1.3.2.2 nathanw static struct { 555 1.3.2.2 nathanw char *class, *device; 556 1.3.2.2 nathanw } d[] = { 557 1.3.2.2 nathanw { AudioCoutputs, AudioNmaster}, 558 1.3.2.2 nathanw { AudioCinputs, AudioNdac}, 559 1.3.2.2 nathanw { AudioCinputs, AudioNcd}, 560 1.3.2.2 nathanw { AudioCrecord, AudioNvolume}, 561 1.3.2.2 nathanw }; 562 1.3.2.2 nathanw 563 1.3.2.2 nathanw ctl.type = AUDIO_MIXER_ENUM; 564 1.3.2.2 nathanw ctl.un.ord = 0; 565 1.3.2.2 nathanw 566 1.3.2.2 nathanw #if 0 567 1.3.2.2 nathanw ctl.dev = sc->sc_codec.codec_if->vtbl->get_portnum_by_name(sc->sc_codec.codec_if, 568 1.3.2.2 nathanw d[i].class, d[i].device, AudioNmute); 569 1.3.2.2 nathanw #endif 570 1.3.2.2 nathanw ctl.dev = autri_get_portnum_by_name(sc,d[i].class, 571 1.3.2.2 nathanw d[i].device, AudioNmute); 572 1.3.2.2 nathanw autri_mixer_set_port(sc, &ctl); 573 1.3.2.2 nathanw } 574 1.3.2.2 nathanw 575 1.3.2.2 nathanw /* set a reasonable default volume */ 576 1.3.2.2 nathanw ctl.type = AUDIO_MIXER_VALUE; 577 1.3.2.2 nathanw ctl.un.value.num_channels = 2; 578 1.3.2.2 nathanw ctl.un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 579 1.3.2.2 nathanw ctl.un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 127; 580 1.3.2.2 nathanw 581 1.3.2.2 nathanw ctl.dev = autri_get_portnum_by_name(sc,AudioCoutputs,AudioNmaster,NULL); 582 1.3.2.2 nathanw autri_mixer_set_port(sc, &ctl); 583 1.3.2.2 nathanw 584 1.3.2.2 nathanw audio_attach_mi(&autri_hw_if, sc, &sc->sc_dev); 585 1.3.2.2 nathanw 586 1.3.2.2 nathanw #if NMIDI > 0 587 1.3.2.2 nathanw midi_attach_mi(&autri_midi_hw_if, sc, &sc->sc_dev); 588 1.3.2.2 nathanw #endif 589 1.3.2.2 nathanw 590 1.3.2.2 nathanw sc->sc_old_power = PWR_RESUME; 591 1.3.2.2 nathanw powerhook_establish(autri_powerhook, sc); 592 1.3.2.2 nathanw } 593 1.3.2.2 nathanw 594 1.3.2.2 nathanw static void 595 1.3.2.2 nathanw autri_powerhook(int why, void *addr) 596 1.3.2.2 nathanw { 597 1.3.2.2 nathanw struct autri_softc *sc = addr; 598 1.3.2.2 nathanw 599 1.3.2.2 nathanw if (why == PWR_RESUME && sc->sc_old_power == PWR_SUSPEND) { 600 1.3.2.2 nathanw DPRINTF(("PWR_RESUME\n")); 601 1.3.2.2 nathanw autri_init(sc); 602 1.3.2.2 nathanw /*autri_reset_codec(&sc->sc_codec);*/ 603 1.3.2.2 nathanw (sc->sc_codec.codec_if->vtbl->restore_ports)(sc->sc_codec.codec_if); 604 1.3.2.2 nathanw } 605 1.3.2.2 nathanw sc->sc_old_power = why; 606 1.3.2.2 nathanw } 607 1.3.2.2 nathanw 608 1.3.2.2 nathanw int 609 1.3.2.2 nathanw autri_init(void *sc_) 610 1.3.2.2 nathanw { 611 1.3.2.2 nathanw struct autri_softc *sc = sc_; 612 1.3.2.2 nathanw u_int32_t reg; 613 1.3.2.2 nathanw 614 1.3.2.2 nathanw pci_chipset_tag_t pc = sc->sc_pc; 615 1.3.2.2 nathanw pcitag_t pt = sc->sc_pt; 616 1.3.2.2 nathanw 617 1.3.2.2 nathanw DPRINTF(("in autri_init()\n")); 618 1.3.2.2 nathanw DPRINTFN(5,("pci_conf_read(0x40) : 0x%X\n",pci_conf_read(pc,pt,0x40))); 619 1.3.2.2 nathanw DPRINTFN(5,("pci_conf_read(0x44) : 0x%X\n",pci_conf_read(pc,pt,0x44))); 620 1.3.2.2 nathanw 621 1.3.2.2 nathanw switch (sc->sc_devid) { 622 1.3.2.2 nathanw case AUTRI_DEVICE_ID_4DWAVE_DX: 623 1.3.2.2 nathanw /* disable Legacy Control */ 624 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_DDMA_CFG,0); 625 1.3.2.2 nathanw reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE); 626 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000); 627 1.3.2.2 nathanw delay(100); 628 1.3.2.2 nathanw /* audio engine reset */ 629 1.3.2.2 nathanw reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE); 630 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x00040000); 631 1.3.2.2 nathanw delay(100); 632 1.3.2.2 nathanw /* release reset */ 633 1.3.2.2 nathanw reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE); 634 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00040000); 635 1.3.2.2 nathanw delay(100); 636 1.3.2.2 nathanw /* DAC on */ 637 1.3.2.2 nathanw autri_reg_set_4(sc,AUTRI_DX_ACR2,0x02); 638 1.3.2.2 nathanw break; 639 1.3.2.2 nathanw case AUTRI_DEVICE_ID_4DWAVE_NX: 640 1.3.2.2 nathanw /* disable Legacy Control */ 641 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_DDMA_CFG,0); 642 1.3.2.2 nathanw reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE); 643 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000); 644 1.3.2.2 nathanw delay(100); 645 1.3.2.2 nathanw /* audio engine reset */ 646 1.3.2.2 nathanw reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE); 647 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x00010000); 648 1.3.2.2 nathanw delay(100); 649 1.3.2.2 nathanw /* release reset */ 650 1.3.2.2 nathanw reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE); 651 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00010000); 652 1.3.2.2 nathanw delay(100); 653 1.3.2.2 nathanw /* DAC on */ 654 1.3.2.2 nathanw autri_reg_set_4(sc,AUTRI_NX_ACR0,0x02); 655 1.3.2.2 nathanw break; 656 1.3.2.2 nathanw case AUTRI_DEVICE_ID_SIS_7018: 657 1.3.2.2 nathanw /* disable Legacy Control */ 658 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_DDMA_CFG,0); 659 1.3.2.2 nathanw reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE); 660 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000); 661 1.3.2.2 nathanw delay(100); 662 1.3.2.2 nathanw /* reset Digital Controller */ 663 1.3.2.2 nathanw reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE); 664 1.3.2.4 nathanw pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x00040000); 665 1.3.2.2 nathanw delay(100); 666 1.3.2.2 nathanw /* release reset */ 667 1.3.2.2 nathanw reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE); 668 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00040000); 669 1.3.2.2 nathanw delay(100); 670 1.3.2.2 nathanw /* disable AC97 GPIO interrupt */ 671 1.3.2.2 nathanw TWRITE1(sc, AUTRI_SIS_ACGPIO, 0); 672 1.3.2.2 nathanw /* enable 64 channel mode */ 673 1.3.2.2 nathanw autri_reg_set_4(sc, AUTRI_LFO_GC_CIR, BANK_B_EN); 674 1.3.2.2 nathanw break; 675 1.3.2.2 nathanw case AUTRI_DEVICE_ID_ALI_M5451: 676 1.3.2.2 nathanw /* disable Legacy Control */ 677 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_DDMA_CFG,0); 678 1.3.2.2 nathanw reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE); 679 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000); 680 1.3.2.2 nathanw delay(100); 681 1.3.2.2 nathanw /* reset Digital Controller */ 682 1.3.2.2 nathanw reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE); 683 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x000c0000); 684 1.3.2.2 nathanw delay(100); 685 1.3.2.2 nathanw /* release reset */ 686 1.3.2.2 nathanw reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE); 687 1.3.2.2 nathanw pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00040000); 688 1.3.2.2 nathanw delay(100); 689 1.3.2.2 nathanw /* enable PCM input */ 690 1.3.2.2 nathanw autri_reg_set_4(sc, AUTRI_ALI_GCONTROL, AUTRI_ALI_GCONTROL_PCM_IN); 691 1.3.2.2 nathanw break; 692 1.3.2.2 nathanw } 693 1.3.2.2 nathanw 694 1.3.2.2 nathanw if (sc->sc_devid == AUTRI_DEVICE_ID_ALI_M5451) { 695 1.3.2.2 nathanw sc->sc_play.ch = 0; 696 1.3.2.2 nathanw sc->sc_play.ch_intr = 1; 697 1.3.2.2 nathanw sc->sc_rec.ch = 31; 698 1.3.2.2 nathanw sc->sc_rec.ch_intr = 2; 699 1.3.2.2 nathanw } else { 700 1.3.2.2 nathanw sc->sc_play.ch = 0x20; 701 1.3.2.2 nathanw sc->sc_play.ch_intr = 0x21; 702 1.3.2.2 nathanw sc->sc_rec.ch = 0x22; 703 1.3.2.2 nathanw sc->sc_rec.ch_intr = 0x23; 704 1.3.2.2 nathanw } 705 1.3.2.2 nathanw 706 1.3.2.2 nathanw /* clear channel status */ 707 1.3.2.2 nathanw TWRITE4(sc, AUTRI_STOP_A, 0xffffffff); 708 1.3.2.2 nathanw TWRITE4(sc, AUTRI_STOP_B, 0xffffffff); 709 1.3.2.2 nathanw 710 1.3.2.2 nathanw /* disable channel interrupt */ 711 1.3.2.2 nathanw TWRITE4(sc, AUTRI_AINTEN_A, 0); 712 1.3.2.2 nathanw TWRITE4(sc, AUTRI_AINTEN_B, 0); 713 1.3.2.2 nathanw 714 1.3.2.2 nathanw #if 0 715 1.3.2.2 nathanw /* TLB */ 716 1.3.2.2 nathanw if (sc->sc_devid == AUTRI_DEVICE_ID_4DWAVE_NX) { 717 1.3.2.2 nathanw TWRITE4(sc,AUTRI_NX_TLBC,0); 718 1.3.2.2 nathanw } 719 1.3.2.2 nathanw #endif 720 1.3.2.2 nathanw 721 1.3.2.2 nathanw autri_enable_loop_interrupt(sc); 722 1.3.2.2 nathanw 723 1.3.2.2 nathanw DPRINTF(("out autri_init()\n")); 724 1.3.2.2 nathanw return 0; 725 1.3.2.2 nathanw } 726 1.3.2.2 nathanw 727 1.3.2.2 nathanw static void 728 1.3.2.2 nathanw autri_enable_loop_interrupt(void *sc_) 729 1.3.2.2 nathanw { 730 1.3.2.2 nathanw struct autri_softc *sc = sc_; 731 1.3.2.2 nathanw u_int32_t reg; 732 1.3.2.2 nathanw 733 1.3.2.2 nathanw /*reg = (ENDLP_IE | MIDLP_IE);*/ 734 1.3.2.2 nathanw reg = ENDLP_IE; 735 1.3.2.4 nathanw 736 1.3.2.2 nathanw if (sc->sc_devid == AUTRI_DEVICE_ID_SIS_7018) 737 1.3.2.2 nathanw reg |= BANK_B_EN; 738 1.3.2.4 nathanw 739 1.3.2.2 nathanw autri_reg_set_4(sc,AUTRI_LFO_GC_CIR,reg); 740 1.3.2.2 nathanw } 741 1.3.2.2 nathanw 742 1.3.2.2 nathanw #if 0 743 1.3.2.2 nathanw static void 744 1.3.2.2 nathanw autri_disable_loop_interrupt(void *sc_) 745 1.3.2.2 nathanw { 746 1.3.2.2 nathanw struct autri_softc *sc = sc_; 747 1.3.2.2 nathanw u_int32_t reg; 748 1.3.2.2 nathanw 749 1.3.2.2 nathanw reg = (ENDLP_IE | MIDLP_IE); 750 1.3.2.2 nathanw autri_reg_clear_4(sc,AUTRI_LFO_GC_CIR,reg); 751 1.3.2.2 nathanw } 752 1.3.2.2 nathanw #endif 753 1.3.2.2 nathanw 754 1.3.2.2 nathanw int 755 1.3.2.2 nathanw autri_intr(void *p) 756 1.3.2.2 nathanw { 757 1.3.2.2 nathanw struct autri_softc *sc = p; 758 1.3.2.2 nathanw u_int32_t intsrc; 759 1.3.2.2 nathanw u_int32_t mask, active[2]; 760 1.3.2.2 nathanw int ch, endch; 761 1.3.2.2 nathanw /* 762 1.3.2.2 nathanw u_int32_t reg; 763 1.3.2.2 nathanw u_int32_t cso,eso; 764 1.3.2.2 nathanw */ 765 1.3.2.2 nathanw 766 1.3.2.2 nathanw intsrc = TREAD4(sc,AUTRI_MISCINT); 767 1.3.2.2 nathanw if ((intsrc & (ADDRESS_IRQ|MPU401_IRQ)) == 0) 768 1.3.2.2 nathanw return 0; 769 1.3.2.2 nathanw 770 1.3.2.2 nathanw if (intsrc & ADDRESS_IRQ) { 771 1.3.2.2 nathanw 772 1.3.2.2 nathanw active[0] = TREAD4(sc,AUTRI_AIN_A); 773 1.3.2.2 nathanw active[1] = TREAD4(sc,AUTRI_AIN_B); 774 1.3.2.2 nathanw 775 1.3.2.2 nathanw if (sc->sc_devid == AUTRI_DEVICE_ID_ALI_M5451) { 776 1.3.2.2 nathanw endch = 32; 777 1.3.2.2 nathanw } else { 778 1.3.2.2 nathanw endch = 64; 779 1.3.2.2 nathanw } 780 1.3.2.2 nathanw 781 1.3.2.2 nathanw for (ch=0; ch<endch; ch++) { 782 1.3.2.2 nathanw mask = 1 << (ch & 0x1f); 783 1.3.2.2 nathanw if (active[(ch & 0x20) ? 1 : 0] & mask) { 784 1.3.2.2 nathanw 785 1.3.2.7 thorpej /* clear interrupt */ 786 1.3.2.2 nathanw TWRITE4(sc, (ch & 0x20) ? AUTRI_AIN_B : AUTRI_AIN_A, mask); 787 1.3.2.7 thorpej /* disable interrupt */ 788 1.3.2.2 nathanw autri_reg_clear_4(sc,(ch & 0x20) ? AUTRI_AINTEN_B : AUTRI_AINTEN_A, mask); 789 1.3.2.2 nathanw #if 0 790 1.3.2.2 nathanw reg = TREAD4(sc,AUTRI_LFO_GC_CIR) & ~0x0000003f; 791 1.3.2.2 nathanw TWRITE4(sc,AUTRI_LFO_GC_CIR, reg | ch); 792 1.3.2.2 nathanw 793 1.3.2.2 nathanw if (sc->sc_devid == AUTRI_DEVICE_ID_4DWAVE_NX) { 794 1.3.2.2 nathanw cso = TREAD4(sc, 0xe0) & 0x00ffffff; 795 1.3.2.2 nathanw eso = TREAD4(sc, 0xe8) & 0x00ffffff; 796 1.3.2.2 nathanw } else { 797 1.3.2.2 nathanw cso = (TREAD4(sc, 0xe0) >> 16) & 0x0000ffff; 798 1.3.2.2 nathanw eso = (TREAD4(sc, 0xe8) >> 16) & 0x0000ffff; 799 1.3.2.2 nathanw } 800 1.3.2.2 nathanw /*printf("cso=%d, eso=%d\n",cso,eso);*/ 801 1.3.2.2 nathanw #endif 802 1.3.2.2 nathanw if (ch == sc->sc_play.ch_intr) { 803 1.3.2.2 nathanw if (sc->sc_play.intr) 804 1.3.2.2 nathanw sc->sc_play.intr(sc->sc_play.intr_arg); 805 1.3.2.2 nathanw } 806 1.3.2.2 nathanw 807 1.3.2.2 nathanw if (ch == sc->sc_rec.ch_intr) { 808 1.3.2.2 nathanw if (sc->sc_rec.intr) 809 1.3.2.2 nathanw sc->sc_rec.intr(sc->sc_rec.intr_arg); 810 1.3.2.2 nathanw } 811 1.3.2.2 nathanw 812 1.3.2.2 nathanw /* enable interrupt */ 813 1.3.2.2 nathanw autri_reg_set_4(sc, (ch & 0x20) ? AUTRI_AINTEN_B : AUTRI_AINTEN_A, mask); 814 1.3.2.2 nathanw } 815 1.3.2.2 nathanw } 816 1.3.2.2 nathanw } 817 1.3.2.2 nathanw 818 1.3.2.2 nathanw if (intsrc & MPU401_IRQ) { 819 1.3.2.2 nathanw /* XXX */ 820 1.3.2.2 nathanw } 821 1.3.2.2 nathanw 822 1.3.2.2 nathanw autri_reg_set_4(sc,AUTRI_MISCINT, 823 1.3.2.2 nathanw ST_TARGET_REACHED | MIXER_OVERFLOW | MIXER_UNDERFLOW); 824 1.3.2.2 nathanw 825 1.3.2.2 nathanw return 1; 826 1.3.2.2 nathanw } 827 1.3.2.2 nathanw 828 1.3.2.2 nathanw /* 829 1.3.2.2 nathanw * 830 1.3.2.2 nathanw */ 831 1.3.2.2 nathanw 832 1.3.2.2 nathanw int 833 1.3.2.2 nathanw autri_allocmem(struct autri_softc *sc, size_t size, size_t align, 834 1.3.2.2 nathanw struct autri_dma *p) 835 1.3.2.2 nathanw { 836 1.3.2.2 nathanw int error; 837 1.3.2.2 nathanw 838 1.3.2.2 nathanw p->size = size; 839 1.3.2.2 nathanw error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 840 1.3.2.2 nathanw p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 841 1.3.2.2 nathanw &p->nsegs, BUS_DMA_NOWAIT); 842 1.3.2.2 nathanw if (error) 843 1.3.2.2 nathanw return (error); 844 1.3.2.2 nathanw 845 1.3.2.2 nathanw error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 846 1.3.2.2 nathanw &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 847 1.3.2.2 nathanw if (error) 848 1.3.2.2 nathanw goto free; 849 1.3.2.2 nathanw 850 1.3.2.2 nathanw error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 851 1.3.2.2 nathanw 0, BUS_DMA_NOWAIT, &p->map); 852 1.3.2.2 nathanw if (error) 853 1.3.2.2 nathanw goto unmap; 854 1.3.2.2 nathanw 855 1.3.2.2 nathanw error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 856 1.3.2.2 nathanw BUS_DMA_NOWAIT); 857 1.3.2.2 nathanw if (error) 858 1.3.2.2 nathanw goto destroy; 859 1.3.2.2 nathanw return (0); 860 1.3.2.2 nathanw 861 1.3.2.2 nathanw destroy: 862 1.3.2.2 nathanw bus_dmamap_destroy(sc->sc_dmatag, p->map); 863 1.3.2.2 nathanw unmap: 864 1.3.2.2 nathanw bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 865 1.3.2.2 nathanw free: 866 1.3.2.2 nathanw bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 867 1.3.2.2 nathanw return (error); 868 1.3.2.2 nathanw } 869 1.3.2.2 nathanw 870 1.3.2.2 nathanw int 871 1.3.2.2 nathanw autri_freemem(struct autri_softc *sc, struct autri_dma *p) 872 1.3.2.2 nathanw { 873 1.3.2.2 nathanw bus_dmamap_unload(sc->sc_dmatag, p->map); 874 1.3.2.2 nathanw bus_dmamap_destroy(sc->sc_dmatag, p->map); 875 1.3.2.2 nathanw bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 876 1.3.2.2 nathanw bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 877 1.3.2.2 nathanw return 0; 878 1.3.2.2 nathanw } 879 1.3.2.2 nathanw 880 1.3.2.2 nathanw int 881 1.3.2.2 nathanw autri_open(void *addr, int flags) 882 1.3.2.2 nathanw { 883 1.3.2.2 nathanw DPRINTF(("autri_open()\n")); 884 1.3.2.2 nathanw DPRINTFN(5,("MISCINT : 0x%08X\n", 885 1.3.2.2 nathanw TREAD4((struct autri_softc *)addr, AUTRI_MISCINT))); 886 1.3.2.2 nathanw DPRINTFN(5,("LFO_GC_CIR : 0x%08X\n", 887 1.3.2.2 nathanw TREAD4((struct autri_softc *)addr, AUTRI_LFO_GC_CIR))); 888 1.3.2.2 nathanw return 0; 889 1.3.2.2 nathanw } 890 1.3.2.2 nathanw 891 1.3.2.2 nathanw void 892 1.3.2.2 nathanw autri_close(void *addr) 893 1.3.2.2 nathanw { 894 1.3.2.2 nathanw DPRINTF(("autri_close()\n")); 895 1.3.2.2 nathanw } 896 1.3.2.2 nathanw 897 1.3.2.2 nathanw int 898 1.3.2.2 nathanw autri_query_encoding(void *addr, struct audio_encoding *fp) 899 1.3.2.2 nathanw { 900 1.3.2.2 nathanw switch (fp->index) { 901 1.3.2.2 nathanw case 0: 902 1.3.2.2 nathanw strcpy(fp->name, AudioEulinear); 903 1.3.2.2 nathanw fp->encoding = AUDIO_ENCODING_ULINEAR; 904 1.3.2.2 nathanw fp->precision = 8; 905 1.3.2.2 nathanw fp->flags = 0; 906 1.3.2.2 nathanw break; 907 1.3.2.2 nathanw case 1: 908 1.3.2.2 nathanw strcpy(fp->name, AudioEmulaw); 909 1.3.2.2 nathanw fp->encoding = AUDIO_ENCODING_ULAW; 910 1.3.2.2 nathanw fp->precision = 8; 911 1.3.2.2 nathanw fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 912 1.3.2.2 nathanw break; 913 1.3.2.2 nathanw case 2: 914 1.3.2.2 nathanw strcpy(fp->name, AudioEalaw); 915 1.3.2.2 nathanw fp->encoding = AUDIO_ENCODING_ALAW; 916 1.3.2.2 nathanw fp->precision = 8; 917 1.3.2.2 nathanw fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 918 1.3.2.2 nathanw break; 919 1.3.2.2 nathanw case 3: 920 1.3.2.2 nathanw strcpy(fp->name, AudioEslinear); 921 1.3.2.2 nathanw fp->encoding = AUDIO_ENCODING_SLINEAR; 922 1.3.2.2 nathanw fp->precision = 8; 923 1.3.2.2 nathanw fp->flags = 0; 924 1.3.2.2 nathanw break; 925 1.3.2.2 nathanw case 4: 926 1.3.2.2 nathanw strcpy(fp->name, AudioEslinear_le); 927 1.3.2.2 nathanw fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 928 1.3.2.2 nathanw fp->precision = 16; 929 1.3.2.2 nathanw fp->flags = 0; 930 1.3.2.2 nathanw break; 931 1.3.2.2 nathanw case 5: 932 1.3.2.2 nathanw strcpy(fp->name, AudioEulinear_le); 933 1.3.2.2 nathanw fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 934 1.3.2.2 nathanw fp->precision = 16; 935 1.3.2.2 nathanw fp->flags = 0; 936 1.3.2.2 nathanw break; 937 1.3.2.2 nathanw case 6: 938 1.3.2.2 nathanw strcpy(fp->name, AudioEslinear_be); 939 1.3.2.2 nathanw fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 940 1.3.2.2 nathanw fp->precision = 16; 941 1.3.2.2 nathanw fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 942 1.3.2.2 nathanw break; 943 1.3.2.2 nathanw case 7: 944 1.3.2.2 nathanw strcpy(fp->name, AudioEulinear_be); 945 1.3.2.2 nathanw fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 946 1.3.2.2 nathanw fp->precision = 16; 947 1.3.2.2 nathanw fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 948 1.3.2.2 nathanw break; 949 1.3.2.2 nathanw default: 950 1.3.2.2 nathanw return (EINVAL); 951 1.3.2.2 nathanw } 952 1.3.2.2 nathanw 953 1.3.2.2 nathanw return 0; 954 1.3.2.2 nathanw } 955 1.3.2.2 nathanw 956 1.3.2.2 nathanw int 957 1.3.2.2 nathanw autri_set_params(void *addr, int setmode, int usemode, 958 1.3.2.2 nathanw struct audio_params *play, struct audio_params *rec) 959 1.3.2.2 nathanw { 960 1.3.2.2 nathanw struct audio_params *p; 961 1.3.2.2 nathanw int mode; 962 1.3.2.2 nathanw 963 1.3.2.2 nathanw for (mode = AUMODE_RECORD; mode != -1; 964 1.3.2.2 nathanw mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 965 1.3.2.2 nathanw if ((setmode & mode) == 0) 966 1.3.2.2 nathanw continue; 967 1.3.2.2 nathanw 968 1.3.2.2 nathanw p = mode == AUMODE_PLAY ? play : rec; 969 1.3.2.2 nathanw 970 1.3.2.2 nathanw if (p->sample_rate < 4000 || p->sample_rate > 48000 || 971 1.3.2.2 nathanw (p->precision != 8 && p->precision != 16) || 972 1.3.2.2 nathanw (p->channels != 1 && p->channels != 2)) 973 1.3.2.2 nathanw return (EINVAL); 974 1.3.2.2 nathanw 975 1.3.2.2 nathanw p->factor = 1; 976 1.3.2.2 nathanw p->sw_code = 0; 977 1.3.2.2 nathanw switch (p->encoding) { 978 1.3.2.2 nathanw case AUDIO_ENCODING_SLINEAR_BE: 979 1.3.2.2 nathanw case AUDIO_ENCODING_ULINEAR_BE: 980 1.3.2.2 nathanw if (p->precision == 16) 981 1.3.2.2 nathanw p->sw_code = swap_bytes; 982 1.3.2.2 nathanw break; 983 1.3.2.2 nathanw case AUDIO_ENCODING_SLINEAR_LE: 984 1.3.2.2 nathanw case AUDIO_ENCODING_ULINEAR_LE: 985 1.3.2.2 nathanw break; 986 1.3.2.2 nathanw case AUDIO_ENCODING_ULAW: 987 1.3.2.2 nathanw if (mode == AUMODE_PLAY) 988 1.3.2.2 nathanw p->sw_code = mulaw_to_ulinear8; 989 1.3.2.2 nathanw else 990 1.3.2.2 nathanw p->sw_code = ulinear8_to_mulaw; 991 1.3.2.2 nathanw 992 1.3.2.2 nathanw break; 993 1.3.2.2 nathanw case AUDIO_ENCODING_ALAW: 994 1.3.2.2 nathanw if (mode == AUMODE_PLAY) 995 1.3.2.2 nathanw p->sw_code = alaw_to_ulinear8; 996 1.3.2.2 nathanw else 997 1.3.2.2 nathanw p->sw_code = ulinear8_to_alaw; 998 1.3.2.2 nathanw 999 1.3.2.2 nathanw break; 1000 1.3.2.2 nathanw default: 1001 1.3.2.2 nathanw return (EINVAL); 1002 1.3.2.2 nathanw } 1003 1.3.2.2 nathanw } 1004 1.3.2.2 nathanw 1005 1.3.2.2 nathanw return 0; 1006 1.3.2.2 nathanw } 1007 1.3.2.2 nathanw 1008 1.3.2.2 nathanw int 1009 1.3.2.2 nathanw autri_round_blocksize(void *addr, int block) 1010 1.3.2.2 nathanw { 1011 1.3.2.2 nathanw return (block & -4); 1012 1.3.2.2 nathanw } 1013 1.3.2.2 nathanw 1014 1.3.2.2 nathanw int 1015 1.3.2.2 nathanw autri_halt_output(void *addr) 1016 1.3.2.2 nathanw { 1017 1.3.2.2 nathanw struct autri_softc *sc = addr; 1018 1.3.2.2 nathanw 1019 1.3.2.2 nathanw DPRINTF(("autri_halt_output()\n")); 1020 1.3.2.2 nathanw 1021 1.3.2.2 nathanw sc->sc_play.intr = NULL; 1022 1.3.2.2 nathanw autri_stopch(sc, sc->sc_play.ch, sc->sc_play.ch_intr); 1023 1.3.2.2 nathanw autri_disable_interrupt(sc, sc->sc_play.ch_intr); 1024 1.3.2.2 nathanw 1025 1.3.2.2 nathanw return 0; 1026 1.3.2.2 nathanw } 1027 1.3.2.2 nathanw 1028 1.3.2.2 nathanw int 1029 1.3.2.2 nathanw autri_halt_input(void *addr) 1030 1.3.2.2 nathanw { 1031 1.3.2.2 nathanw struct autri_softc *sc = addr; 1032 1.3.2.2 nathanw 1033 1.3.2.2 nathanw DPRINTF(("autri_halt_input()\n")); 1034 1.3.2.2 nathanw 1035 1.3.2.2 nathanw sc->sc_rec.intr = NULL; 1036 1.3.2.2 nathanw autri_stopch(sc, sc->sc_rec.ch, sc->sc_rec.ch_intr); 1037 1.3.2.2 nathanw autri_disable_interrupt(sc, sc->sc_rec.ch_intr); 1038 1.3.2.2 nathanw 1039 1.3.2.2 nathanw return 0; 1040 1.3.2.2 nathanw } 1041 1.3.2.2 nathanw 1042 1.3.2.2 nathanw int 1043 1.3.2.2 nathanw autri_getdev(void *addr, struct audio_device *retp) 1044 1.3.2.2 nathanw { 1045 1.3.2.2 nathanw struct autri_softc *sc = addr; 1046 1.3.2.2 nathanw 1047 1.3.2.2 nathanw DPRINTF(("autri_getdev().\n")); 1048 1.3.2.2 nathanw 1049 1.3.2.2 nathanw strncpy(retp->name, "Trident 4DWAVE", sizeof(retp->name)); 1050 1.3.2.2 nathanw snprintf(retp->version, sizeof(retp->version), "0x%02x", 1051 1.3.2.2 nathanw PCI_REVISION(sc->sc_class)); 1052 1.3.2.2 nathanw 1053 1.3.2.2 nathanw switch (sc->sc_devid) { 1054 1.3.2.2 nathanw case AUTRI_DEVICE_ID_4DWAVE_DX: 1055 1.3.2.2 nathanw strncpy(retp->config, "4DWAVE-DX", sizeof(retp->config)); 1056 1.3.2.2 nathanw break; 1057 1.3.2.2 nathanw case AUTRI_DEVICE_ID_4DWAVE_NX: 1058 1.3.2.2 nathanw strncpy(retp->config, "4DWAVE-NX", sizeof(retp->config)); 1059 1.3.2.2 nathanw break; 1060 1.3.2.2 nathanw case AUTRI_DEVICE_ID_SIS_7018: 1061 1.3.2.2 nathanw strncpy(retp->config, "SiS 7018", sizeof(retp->config)); 1062 1.3.2.2 nathanw break; 1063 1.3.2.2 nathanw case AUTRI_DEVICE_ID_ALI_M5451: 1064 1.3.2.2 nathanw strncpy(retp->config, "ALi M5451", sizeof(retp->config)); 1065 1.3.2.2 nathanw break; 1066 1.3.2.2 nathanw default: 1067 1.3.2.2 nathanw strncpy(retp->config, "unknown", sizeof(retp->config)); 1068 1.3.2.2 nathanw } 1069 1.3.2.2 nathanw 1070 1.3.2.2 nathanw return 0; 1071 1.3.2.2 nathanw } 1072 1.3.2.2 nathanw 1073 1.3.2.2 nathanw int 1074 1.3.2.2 nathanw autri_mixer_set_port(void *addr, mixer_ctrl_t *cp) 1075 1.3.2.2 nathanw { 1076 1.3.2.2 nathanw struct autri_softc *sc = addr; 1077 1.3.2.2 nathanw 1078 1.3.2.2 nathanw return (sc->sc_codec.codec_if->vtbl->mixer_set_port( 1079 1.3.2.2 nathanw sc->sc_codec.codec_if, cp)); 1080 1.3.2.2 nathanw } 1081 1.3.2.2 nathanw 1082 1.3.2.2 nathanw int 1083 1.3.2.2 nathanw autri_mixer_get_port(void *addr, mixer_ctrl_t *cp) 1084 1.3.2.2 nathanw { 1085 1.3.2.2 nathanw struct autri_softc *sc = addr; 1086 1.3.2.2 nathanw 1087 1.3.2.2 nathanw return (sc->sc_codec.codec_if->vtbl->mixer_get_port( 1088 1.3.2.2 nathanw sc->sc_codec.codec_if, cp)); 1089 1.3.2.2 nathanw } 1090 1.3.2.2 nathanw 1091 1.3.2.2 nathanw int 1092 1.3.2.2 nathanw autri_query_devinfo(void *addr, mixer_devinfo_t *dip) 1093 1.3.2.2 nathanw { 1094 1.3.2.2 nathanw struct autri_softc *sc = addr; 1095 1.3.2.2 nathanw 1096 1.3.2.2 nathanw return (sc->sc_codec.codec_if->vtbl->query_devinfo( 1097 1.3.2.2 nathanw sc->sc_codec.codec_if, dip)); 1098 1.3.2.2 nathanw } 1099 1.3.2.2 nathanw 1100 1.3.2.2 nathanw int 1101 1.3.2.2 nathanw autri_get_portnum_by_name(struct autri_softc *sc, char *class, 1102 1.3.2.2 nathanw char *device, char *qualifier) 1103 1.3.2.2 nathanw { 1104 1.3.2.2 nathanw return (sc->sc_codec.codec_if->vtbl->get_portnum_by_name( 1105 1.3.2.2 nathanw sc->sc_codec.codec_if, class, device, qualifier)); 1106 1.3.2.2 nathanw } 1107 1.3.2.2 nathanw 1108 1.3.2.2 nathanw void * 1109 1.3.2.2 nathanw autri_malloc(void *addr, int direction, size_t size, int pool, int flags) 1110 1.3.2.2 nathanw { 1111 1.3.2.2 nathanw struct autri_softc *sc = addr; 1112 1.3.2.2 nathanw struct autri_dma *p; 1113 1.3.2.2 nathanw int error; 1114 1.3.2.2 nathanw 1115 1.3.2.2 nathanw p = malloc(sizeof(*p), pool, flags); 1116 1.3.2.2 nathanw if (!p) 1117 1.3.2.2 nathanw return NULL; 1118 1.3.2.2 nathanw 1119 1.3.2.2 nathanw #if 0 1120 1.3.2.2 nathanw error = autri_allocmem(sc, size, 16, p); 1121 1.3.2.2 nathanw #endif 1122 1.3.2.2 nathanw error = autri_allocmem(sc, size, 0x10000, p); 1123 1.3.2.2 nathanw if (error) { 1124 1.3.2.2 nathanw free(p, pool); 1125 1.3.2.2 nathanw return NULL; 1126 1.3.2.2 nathanw } 1127 1.3.2.2 nathanw 1128 1.3.2.2 nathanw p->next = sc->sc_dmas; 1129 1.3.2.2 nathanw sc->sc_dmas = p; 1130 1.3.2.2 nathanw return KERNADDR(p); 1131 1.3.2.2 nathanw } 1132 1.3.2.2 nathanw 1133 1.3.2.2 nathanw void 1134 1.3.2.2 nathanw autri_free(void *addr, void *ptr, int pool) 1135 1.3.2.2 nathanw { 1136 1.3.2.2 nathanw struct autri_softc *sc = addr; 1137 1.3.2.2 nathanw struct autri_dma **pp, *p; 1138 1.3.2.2 nathanw 1139 1.3.2.2 nathanw for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1140 1.3.2.2 nathanw if (KERNADDR(p) == ptr) { 1141 1.3.2.2 nathanw autri_freemem(sc, p); 1142 1.3.2.2 nathanw *pp = p->next; 1143 1.3.2.2 nathanw free(p, pool); 1144 1.3.2.2 nathanw return; 1145 1.3.2.2 nathanw } 1146 1.3.2.2 nathanw } 1147 1.3.2.2 nathanw } 1148 1.3.2.2 nathanw 1149 1.3.2.2 nathanw static struct autri_dma * 1150 1.3.2.2 nathanw autri_find_dma(struct autri_softc *sc, void *addr) 1151 1.3.2.2 nathanw { 1152 1.3.2.2 nathanw struct autri_dma *p; 1153 1.3.2.2 nathanw 1154 1.3.2.2 nathanw for (p = sc->sc_dmas; p && KERNADDR(p) != addr; p = p->next) 1155 1.3.2.2 nathanw ; 1156 1.3.2.2 nathanw 1157 1.3.2.2 nathanw return p; 1158 1.3.2.2 nathanw } 1159 1.3.2.2 nathanw 1160 1.3.2.2 nathanw size_t 1161 1.3.2.2 nathanw autri_round_buffersize(void *addr, int direction, size_t size) 1162 1.3.2.2 nathanw { 1163 1.3.2.2 nathanw return size; 1164 1.3.2.2 nathanw } 1165 1.3.2.2 nathanw 1166 1.3.2.2 nathanw paddr_t 1167 1.3.2.2 nathanw autri_mappage(void *addr, void *mem, off_t off, int prot) 1168 1.3.2.2 nathanw { 1169 1.3.2.2 nathanw struct autri_softc *sc = addr; 1170 1.3.2.2 nathanw struct autri_dma *p; 1171 1.3.2.2 nathanw 1172 1.3.2.2 nathanw if (off < 0) 1173 1.3.2.2 nathanw return (-1); 1174 1.3.2.2 nathanw 1175 1.3.2.2 nathanw p = autri_find_dma(sc, mem); 1176 1.3.2.2 nathanw if (!p) 1177 1.3.2.2 nathanw return (-1); 1178 1.3.2.2 nathanw 1179 1.3.2.2 nathanw return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1180 1.3.2.2 nathanw off, prot, BUS_DMA_WAITOK)); 1181 1.3.2.2 nathanw } 1182 1.3.2.2 nathanw 1183 1.3.2.2 nathanw int 1184 1.3.2.2 nathanw autri_get_props(void *addr) 1185 1.3.2.2 nathanw { 1186 1.3.2.2 nathanw return (AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | 1187 1.3.2.2 nathanw AUDIO_PROP_FULLDUPLEX); 1188 1.3.2.2 nathanw } 1189 1.3.2.2 nathanw 1190 1.3.2.2 nathanw static void 1191 1.3.2.2 nathanw autri_setup_channel(struct autri_softc *sc, int mode, 1192 1.3.2.2 nathanw struct audio_params *param) 1193 1.3.2.2 nathanw { 1194 1.3.2.2 nathanw int i, ch, channel; 1195 1.3.2.2 nathanw u_int32_t reg, cr[5]; 1196 1.3.2.2 nathanw u_int32_t cso, eso; 1197 1.3.2.2 nathanw u_int32_t delta, dch[2], ctrl; 1198 1.3.2.2 nathanw u_int32_t alpha_fms, fm_vol, attribute; 1199 1.3.2.2 nathanw 1200 1.3.2.2 nathanw u_int32_t dmaaddr, dmalen; 1201 1.3.2.2 nathanw int factor, rvol, cvol; 1202 1.3.2.2 nathanw struct autri_chstatus *chst; 1203 1.3.2.2 nathanw 1204 1.3.2.2 nathanw ctrl = AUTRI_CTRL_LOOPMODE; 1205 1.3.2.2 nathanw switch (param->encoding) { 1206 1.3.2.2 nathanw case AUDIO_ENCODING_SLINEAR_BE: 1207 1.3.2.2 nathanw case AUDIO_ENCODING_SLINEAR_LE: 1208 1.3.2.2 nathanw ctrl |= AUTRI_CTRL_SIGNED; 1209 1.3.2.2 nathanw break; 1210 1.3.2.2 nathanw } 1211 1.3.2.2 nathanw 1212 1.3.2.2 nathanw factor = 0; 1213 1.3.2.2 nathanw if (param->precision == 16) { 1214 1.3.2.2 nathanw ctrl |= AUTRI_CTRL_16BIT; 1215 1.3.2.2 nathanw factor++; 1216 1.3.2.2 nathanw } 1217 1.3.2.2 nathanw 1218 1.3.2.2 nathanw if (param->channels == 2) { 1219 1.3.2.2 nathanw ctrl |= AUTRI_CTRL_STEREO; 1220 1.3.2.2 nathanw factor++; 1221 1.3.2.2 nathanw } 1222 1.3.2.2 nathanw 1223 1.3.2.2 nathanw delta = (u_int32_t)param->sample_rate; 1224 1.3.2.2 nathanw if (delta < 4000) 1225 1.3.2.2 nathanw delta = 4000; 1226 1.3.2.2 nathanw if (delta > 48000) 1227 1.3.2.2 nathanw delta = 48000; 1228 1.3.2.2 nathanw 1229 1.3.2.6 nathanw attribute = 0; 1230 1.3.2.6 nathanw 1231 1.3.2.2 nathanw dch[1] = ((delta << 12) / 48000) & 0x0000ffff; 1232 1.3.2.2 nathanw if (mode == AUMODE_PLAY) { 1233 1.3.2.2 nathanw chst = &sc->sc_play; 1234 1.3.2.2 nathanw dch[0] = ((delta << 12) / 48000) & 0x0000ffff; 1235 1.3.2.4 nathanw ctrl |= AUTRI_CTRL_WAVEVOL; 1236 1.3.2.2 nathanw } else { 1237 1.3.2.2 nathanw chst = &sc->sc_rec; 1238 1.3.2.2 nathanw dch[0] = ((48000 << 12) / delta) & 0x0000ffff; 1239 1.3.2.6 nathanw if (sc->sc_devid == AUTRI_DEVICE_ID_SIS_7018) { 1240 1.3.2.4 nathanw ctrl |= AUTRI_CTRL_MUTEVOL_SIS; 1241 1.3.2.6 nathanw attribute = AUTRI_ATTR_PCMREC_SIS; 1242 1.3.2.6 nathanw if (delta != 48000) 1243 1.3.2.6 nathanw attribute |= AUTRI_ATTR_ENASRC_SIS; 1244 1.3.2.6 nathanw } else 1245 1.3.2.4 nathanw ctrl |= AUTRI_CTRL_MUTEVOL; 1246 1.3.2.2 nathanw } 1247 1.3.2.2 nathanw 1248 1.3.2.2 nathanw dmaaddr = DMAADDR(chst->dma); 1249 1.3.2.2 nathanw cso = alpha_fms = 0; 1250 1.3.2.2 nathanw rvol = cvol = 0x7f; 1251 1.3.2.2 nathanw fm_vol = 0x0 | ((rvol & 0x7f) << 7) | (cvol & 0x7f); 1252 1.3.2.2 nathanw 1253 1.3.2.2 nathanw for (ch=0; ch<2; ch++) { 1254 1.3.2.2 nathanw 1255 1.3.2.2 nathanw if (ch == 0) 1256 1.3.2.2 nathanw dmalen = (chst->length >> factor); 1257 1.3.2.2 nathanw else { 1258 1.3.2.2 nathanw /* channel for interrupt */ 1259 1.3.2.2 nathanw dmalen = (chst->blksize >> factor); 1260 1.3.2.4 nathanw if (sc->sc_devid == AUTRI_DEVICE_ID_SIS_7018) 1261 1.3.2.4 nathanw ctrl |= AUTRI_CTRL_MUTEVOL_SIS; 1262 1.3.2.4 nathanw else 1263 1.3.2.4 nathanw ctrl |= AUTRI_CTRL_MUTEVOL; 1264 1.3.2.6 nathanw attribute = 0; 1265 1.3.2.2 nathanw } 1266 1.3.2.2 nathanw 1267 1.3.2.2 nathanw eso = dmalen - 1; 1268 1.3.2.2 nathanw 1269 1.3.2.2 nathanw switch (sc->sc_devid) { 1270 1.3.2.2 nathanw case AUTRI_DEVICE_ID_4DWAVE_DX: 1271 1.3.2.2 nathanw cr[0] = (cso << 16) | (alpha_fms & 0x0000ffff); 1272 1.3.2.2 nathanw cr[1] = dmaaddr; 1273 1.3.2.2 nathanw cr[2] = (eso << 16) | (dch[ch] & 0x0000ffff); 1274 1.3.2.2 nathanw cr[3] = fm_vol; 1275 1.3.2.2 nathanw cr[4] = ctrl; 1276 1.3.2.2 nathanw break; 1277 1.3.2.2 nathanw case AUTRI_DEVICE_ID_4DWAVE_NX: 1278 1.3.2.2 nathanw cr[0] = (dch[ch] << 24) | (cso & 0x00ffffff); 1279 1.3.2.2 nathanw cr[1] = dmaaddr; 1280 1.3.2.2 nathanw cr[2] = ((dch[ch] << 16) & 0xff000000) | (eso & 0x00ffffff); 1281 1.3.2.2 nathanw cr[3] = (alpha_fms << 16) | (fm_vol & 0x0000ffff); 1282 1.3.2.2 nathanw cr[4] = ctrl; 1283 1.3.2.2 nathanw break; 1284 1.3.2.2 nathanw case AUTRI_DEVICE_ID_SIS_7018: 1285 1.3.2.2 nathanw cr[0] = (cso << 16) | (alpha_fms & 0x0000ffff); 1286 1.3.2.2 nathanw cr[1] = dmaaddr; 1287 1.3.2.2 nathanw cr[2] = (eso << 16) | (dch[ch] & 0x0000ffff); 1288 1.3.2.6 nathanw cr[3] = attribute; 1289 1.3.2.2 nathanw cr[4] = ctrl; 1290 1.3.2.2 nathanw break; 1291 1.3.2.2 nathanw case AUTRI_DEVICE_ID_ALI_M5451: 1292 1.3.2.2 nathanw cr[0] = (cso << 16) | (alpha_fms & 0x0000ffff); 1293 1.3.2.2 nathanw cr[1] = dmaaddr; 1294 1.3.2.2 nathanw cr[2] = (eso << 16) | (dch[ch] & 0x0000ffff); 1295 1.3.2.2 nathanw cr[3] = 0; 1296 1.3.2.2 nathanw cr[4] = ctrl; 1297 1.3.2.2 nathanw break; 1298 1.3.2.2 nathanw } 1299 1.3.2.2 nathanw 1300 1.3.2.2 nathanw /* write channel data */ 1301 1.3.2.2 nathanw channel = (ch == 0) ? chst->ch : chst->ch_intr; 1302 1.3.2.2 nathanw 1303 1.3.2.2 nathanw reg = TREAD4(sc,AUTRI_LFO_GC_CIR) & ~0x0000003f; 1304 1.3.2.2 nathanw TWRITE4(sc,AUTRI_LFO_GC_CIR, reg | channel); 1305 1.3.2.2 nathanw 1306 1.3.2.2 nathanw for (i=0; i<5; i++) { 1307 1.3.2.2 nathanw TWRITE4(sc, AUTRI_ARAM_CR + i*sizeof(cr[0]), cr[i]); 1308 1.3.2.2 nathanw DPRINTFN(5,("cr[%d] : 0x%08X\n", i, cr[i])); 1309 1.3.2.2 nathanw } 1310 1.3.2.2 nathanw 1311 1.3.2.2 nathanw /* Bank A only */ 1312 1.3.2.2 nathanw if (channel < 0x20) { 1313 1.3.2.2 nathanw TWRITE4(sc, AUTRI_EBUF1, AUTRI_EMOD_STILL); 1314 1.3.2.2 nathanw TWRITE4(sc, AUTRI_EBUF2, AUTRI_EMOD_STILL); 1315 1.3.2.2 nathanw } 1316 1.3.2.2 nathanw } 1317 1.3.2.2 nathanw 1318 1.3.2.2 nathanw } 1319 1.3.2.2 nathanw 1320 1.3.2.2 nathanw int 1321 1.3.2.2 nathanw autri_trigger_output(void *addr, void *start, void *end, int blksize, 1322 1.3.2.2 nathanw void (*intr)(void *), void *arg, 1323 1.3.2.2 nathanw struct audio_params *param) 1324 1.3.2.2 nathanw { 1325 1.3.2.2 nathanw struct autri_softc *sc = addr; 1326 1.3.2.2 nathanw struct autri_dma *p; 1327 1.3.2.2 nathanw 1328 1.3.2.2 nathanw DPRINTFN(5,("autri_trigger_output: sc=%p start=%p end=%p " 1329 1.3.2.2 nathanw "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1330 1.3.2.2 nathanw 1331 1.3.2.2 nathanw sc->sc_play.intr = intr; 1332 1.3.2.2 nathanw sc->sc_play.intr_arg = arg; 1333 1.3.2.2 nathanw sc->sc_play.offset = 0; 1334 1.3.2.2 nathanw sc->sc_play.blksize = blksize; 1335 1.3.2.2 nathanw sc->sc_play.length = (char *)end - (char *)start; 1336 1.3.2.2 nathanw 1337 1.3.2.2 nathanw p = autri_find_dma(sc, start); 1338 1.3.2.2 nathanw if (!p) { 1339 1.3.2.2 nathanw printf("autri_trigger_output: bad addr %p\n", start); 1340 1.3.2.2 nathanw return (EINVAL); 1341 1.3.2.2 nathanw } 1342 1.3.2.2 nathanw 1343 1.3.2.2 nathanw sc->sc_play.dma = p; 1344 1.3.2.2 nathanw 1345 1.3.2.2 nathanw /* */ 1346 1.3.2.2 nathanw autri_setup_channel(sc, AUMODE_PLAY, param); 1347 1.3.2.2 nathanw 1348 1.3.2.2 nathanw /* volume set to no attenuation */ 1349 1.3.2.2 nathanw TWRITE4(sc, AUTRI_MUSICVOL_WAVEVOL, 0); 1350 1.3.2.2 nathanw 1351 1.3.2.2 nathanw /* enable interrupt */ 1352 1.3.2.2 nathanw autri_enable_interrupt(sc, sc->sc_play.ch_intr); 1353 1.3.2.2 nathanw 1354 1.3.2.2 nathanw /* start channel */ 1355 1.3.2.2 nathanw autri_startch(sc, sc->sc_play.ch, sc->sc_play.ch_intr); 1356 1.3.2.2 nathanw 1357 1.3.2.2 nathanw return 0; 1358 1.3.2.2 nathanw } 1359 1.3.2.2 nathanw 1360 1.3.2.2 nathanw int 1361 1.3.2.2 nathanw autri_trigger_input(void *addr, void *start, void *end, int blksize, 1362 1.3.2.2 nathanw void (*intr)(void *), void *arg, 1363 1.3.2.2 nathanw struct audio_params *param) 1364 1.3.2.2 nathanw { 1365 1.3.2.2 nathanw struct autri_softc *sc = addr; 1366 1.3.2.2 nathanw struct autri_dma *p; 1367 1.3.2.2 nathanw 1368 1.3.2.2 nathanw DPRINTFN(5,("autri_trigger_input: sc=%p start=%p end=%p " 1369 1.3.2.2 nathanw "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1370 1.3.2.2 nathanw 1371 1.3.2.2 nathanw sc->sc_rec.intr = intr; 1372 1.3.2.2 nathanw sc->sc_rec.intr_arg = arg; 1373 1.3.2.2 nathanw sc->sc_rec.offset = 0; 1374 1.3.2.2 nathanw sc->sc_rec.blksize = blksize; 1375 1.3.2.2 nathanw sc->sc_rec.length = (char *)end - (char *)start; 1376 1.3.2.2 nathanw 1377 1.3.2.2 nathanw /* */ 1378 1.3.2.2 nathanw p = autri_find_dma(sc, start); 1379 1.3.2.2 nathanw if (!p) { 1380 1.3.2.2 nathanw printf("autri_trigger_input: bad addr %p\n", start); 1381 1.3.2.2 nathanw return (EINVAL); 1382 1.3.2.2 nathanw } 1383 1.3.2.2 nathanw 1384 1.3.2.2 nathanw sc->sc_rec.dma = p; 1385 1.3.2.2 nathanw 1386 1.3.2.2 nathanw /* */ 1387 1.3.2.2 nathanw if (sc->sc_devid == AUTRI_DEVICE_ID_4DWAVE_NX) { 1388 1.3.2.2 nathanw autri_reg_set_4(sc, AUTRI_NX_ACR0, AUTRI_NX_ACR0_PSB_CAPTURE); 1389 1.3.2.2 nathanw TWRITE1(sc, AUTRI_NX_RCI3, AUTRI_NX_RCI3_ENABLE | sc->sc_rec.ch); 1390 1.3.2.2 nathanw } 1391 1.3.2.2 nathanw 1392 1.3.2.2 nathanw #if 0 1393 1.3.2.2 nathanw /* 4DWAVE only allows capturing at a 48KHz rate */ 1394 1.3.2.2 nathanw if (sc->sc_devid == AUTRI_DEVICE_ID_4DWAVE_DX || 1395 1.3.2.2 nathanw sc->sc_devid == AUTRI_DEVICE_ID_4DWAVE_NX) 1396 1.3.2.2 nathanw param->sample_rate = 48000; 1397 1.3.2.2 nathanw #endif 1398 1.3.2.2 nathanw 1399 1.3.2.2 nathanw autri_setup_channel(sc, AUMODE_RECORD, param); 1400 1.3.2.2 nathanw 1401 1.3.2.2 nathanw /* enable interrupt */ 1402 1.3.2.2 nathanw autri_enable_interrupt(sc, sc->sc_rec.ch_intr); 1403 1.3.2.2 nathanw 1404 1.3.2.2 nathanw /* start channel */ 1405 1.3.2.2 nathanw autri_startch(sc, sc->sc_rec.ch, sc->sc_rec.ch_intr); 1406 1.3.2.2 nathanw 1407 1.3.2.2 nathanw return 0; 1408 1.3.2.2 nathanw } 1409 1.3.2.2 nathanw 1410 1.3.2.2 nathanw #if 0 1411 1.3.2.2 nathanw static int 1412 1.3.2.2 nathanw autri_halt(struct autri_softc *sc) 1413 1.3.2.2 nathanw { 1414 1.3.2.2 nathanw DPRINTF(("autri_halt().\n")); 1415 1.3.2.2 nathanw /*autri_stopch(sc);*/ 1416 1.3.2.2 nathanw autri_disable_interrupt(sc, sc->sc_play.channel); 1417 1.3.2.2 nathanw autri_disable_interrupt(sc, sc->sc_rec.channel); 1418 1.3.2.2 nathanw return 0; 1419 1.3.2.2 nathanw } 1420 1.3.2.2 nathanw #endif 1421 1.3.2.2 nathanw 1422 1.3.2.2 nathanw static void 1423 1.3.2.2 nathanw autri_enable_interrupt(struct autri_softc *sc, int ch) 1424 1.3.2.2 nathanw { 1425 1.3.2.2 nathanw int reg; 1426 1.3.2.2 nathanw 1427 1.3.2.2 nathanw reg = (ch & 0x20) ? AUTRI_AINTEN_B : AUTRI_AINTEN_A; 1428 1.3.2.2 nathanw ch &= 0x1f; 1429 1.3.2.2 nathanw 1430 1.3.2.2 nathanw autri_reg_set_4(sc, reg, 1 << ch); 1431 1.3.2.2 nathanw } 1432 1.3.2.2 nathanw 1433 1.3.2.2 nathanw static void 1434 1.3.2.2 nathanw autri_disable_interrupt(struct autri_softc *sc, int ch) 1435 1.3.2.2 nathanw { 1436 1.3.2.2 nathanw int reg; 1437 1.3.2.2 nathanw 1438 1.3.2.2 nathanw reg = (ch & 0x20) ? AUTRI_AINTEN_B : AUTRI_AINTEN_A; 1439 1.3.2.2 nathanw ch &= 0x1f; 1440 1.3.2.2 nathanw 1441 1.3.2.2 nathanw autri_reg_clear_4(sc, reg, 1 << ch); 1442 1.3.2.2 nathanw } 1443 1.3.2.2 nathanw 1444 1.3.2.2 nathanw static void 1445 1.3.2.2 nathanw autri_startch(struct autri_softc *sc, int ch, int ch_intr) 1446 1.3.2.2 nathanw { 1447 1.3.2.2 nathanw int reg; 1448 1.3.2.2 nathanw u_int32_t chmask; 1449 1.3.2.2 nathanw 1450 1.3.2.2 nathanw reg = (ch & 0x20) ? AUTRI_START_B : AUTRI_START_A; 1451 1.3.2.2 nathanw ch &= 0x1f; 1452 1.3.2.6 nathanw ch_intr &= 0x1f; 1453 1.3.2.2 nathanw chmask = (1 << ch) | (1 << ch_intr); 1454 1.3.2.2 nathanw 1455 1.3.2.2 nathanw autri_reg_set_4(sc, reg, chmask); 1456 1.3.2.2 nathanw } 1457 1.3.2.2 nathanw 1458 1.3.2.2 nathanw static void 1459 1.3.2.2 nathanw autri_stopch(struct autri_softc *sc, int ch, int ch_intr) 1460 1.3.2.2 nathanw { 1461 1.3.2.2 nathanw int reg; 1462 1.3.2.2 nathanw u_int32_t chmask; 1463 1.3.2.2 nathanw 1464 1.3.2.2 nathanw reg = (ch & 0x20) ? AUTRI_STOP_B : AUTRI_STOP_A; 1465 1.3.2.2 nathanw ch &= 0x1f; 1466 1.3.2.6 nathanw ch_intr &= 0x1f; 1467 1.3.2.2 nathanw chmask = (1 << ch) | (1 << ch_intr); 1468 1.3.2.2 nathanw 1469 1.3.2.2 nathanw autri_reg_set_4(sc, reg, chmask); 1470 1.3.2.2 nathanw } 1471 1.3.2.2 nathanw 1472 1.3.2.2 nathanw #if NMIDI > 0 1473 1.3.2.2 nathanw int 1474 1.3.2.2 nathanw autri_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1475 1.3.2.2 nathanw void (*ointr)(void *), void *arg) 1476 1.3.2.2 nathanw { 1477 1.3.2.2 nathanw struct autri_softc *sc = addr; 1478 1.3.2.2 nathanw 1479 1.3.2.2 nathanw DPRINTF(("autri_midi_open()\n")); 1480 1.3.2.2 nathanw 1481 1.3.2.2 nathanw DPRINTFN(5,("MPUR1 : 0x%02X\n",TREAD1(sc,AUTRI_MPUR1))); 1482 1.3.2.2 nathanw DPRINTFN(5,("MPUR2 : 0x%02X\n",TREAD1(sc,AUTRI_MPUR2))); 1483 1.3.2.2 nathanw 1484 1.3.2.2 nathanw sc->sc_iintr = iintr; 1485 1.3.2.2 nathanw sc->sc_ointr = ointr; 1486 1.3.2.2 nathanw sc->sc_arg = arg; 1487 1.3.2.2 nathanw 1488 1.3.2.2 nathanw if (flags & FREAD) 1489 1.3.2.2 nathanw autri_reg_clear_1(sc, AUTRI_MPUR2, AUTRI_MIDIIN_ENABLE_INTR); 1490 1.3.2.2 nathanw 1491 1.3.2.2 nathanw if (flags & FWRITE) 1492 1.3.2.2 nathanw autri_reg_set_1(sc, AUTRI_MPUR2, AUTRI_MIDIOUT_CONNECT); 1493 1.3.2.2 nathanw 1494 1.3.2.2 nathanw return (0); 1495 1.3.2.2 nathanw } 1496 1.3.2.2 nathanw 1497 1.3.2.2 nathanw void 1498 1.3.2.2 nathanw autri_midi_close(void *addr) 1499 1.3.2.2 nathanw { 1500 1.3.2.2 nathanw struct autri_softc *sc = addr; 1501 1.3.2.2 nathanw 1502 1.3.2.2 nathanw DPRINTF(("autri_midi_close()\n")); 1503 1.3.2.2 nathanw 1504 1.3.2.2 nathanw tsleep(sc, PWAIT, "autri", hz/10); /* give uart a chance to drain */ 1505 1.3.2.2 nathanw 1506 1.3.2.2 nathanw sc->sc_iintr = NULL; 1507 1.3.2.2 nathanw sc->sc_ointr = NULL; 1508 1.3.2.2 nathanw } 1509 1.3.2.2 nathanw 1510 1.3.2.2 nathanw int 1511 1.3.2.2 nathanw autri_midi_output(void *addr, int d) 1512 1.3.2.2 nathanw { 1513 1.3.2.2 nathanw struct autri_softc *sc = addr; 1514 1.3.2.2 nathanw int x; 1515 1.3.2.2 nathanw 1516 1.3.2.2 nathanw for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1517 1.3.2.2 nathanw if ((TREAD1(sc, AUTRI_MPUR1) & AUTRI_MIDIOUT_READY) == 0) { 1518 1.3.2.2 nathanw TWRITE1(sc, AUTRI_MPUR0, d); 1519 1.3.2.2 nathanw return (0); 1520 1.3.2.2 nathanw } 1521 1.3.2.2 nathanw delay(MIDI_BUSY_DELAY); 1522 1.3.2.2 nathanw } 1523 1.3.2.2 nathanw return (EIO); 1524 1.3.2.2 nathanw } 1525 1.3.2.2 nathanw 1526 1.3.2.2 nathanw void 1527 1.3.2.2 nathanw autri_midi_getinfo(void *addr, struct midi_info *mi) 1528 1.3.2.2 nathanw { 1529 1.3.2.2 nathanw mi->name = "4DWAVE MIDI UART"; 1530 1.3.2.2 nathanw mi->props = MIDI_PROP_CAN_INPUT; 1531 1.3.2.2 nathanw } 1532 1.3.2.2 nathanw 1533 1.3.2.2 nathanw #endif 1534
Indexes created Fri Oct 03 02:09:57 GMT 2025