autrireg.h revision 1.1.2.3
1 1.1.2.3 nathanw /* $NetBSD: autrireg.h,v 1.1.2.3 2002/06/20 03:45:20 nathanw Exp $ */ 2 1.1.2.2 nathanw 3 1.1.2.2 nathanw /* 4 1.1.2.2 nathanw * Copyright (c) 2001 SOMEYA Yoshihiko and KUROSAWA Takahiro. 5 1.1.2.2 nathanw * All rights reserved. 6 1.1.2.2 nathanw * 7 1.1.2.2 nathanw * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 nathanw * modification, are permitted provided that the following conditions 9 1.1.2.2 nathanw * are met: 10 1.1.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 nathanw * documentation and/or other materials provided with the distribution. 15 1.1.2.2 nathanw * 16 1.1.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1.2.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1.2.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1.2.2 nathanw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1.2.2 nathanw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 1.1.2.2 nathanw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 1.1.2.2 nathanw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 1.1.2.2 nathanw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 1.1.2.2 nathanw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 1.1.2.2 nathanw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 1.1.2.2 nathanw */ 27 1.1.2.2 nathanw 28 1.1.2.2 nathanw /* 29 1.1.2.2 nathanw * Trident 4DWAVE registers 30 1.1.2.2 nathanw */ 31 1.1.2.2 nathanw 32 1.1.2.2 nathanw #ifndef _DEV_PCI_AUTRIREG_H_ 33 1.1.2.2 nathanw #define _DEV_PCI_AUTRIREG_H_ 34 1.1.2.2 nathanw 35 1.1.2.2 nathanw 36 1.1.2.2 nathanw #define AUTRI_DEVICE_ID_4DWAVE_DX \ 37 1.1.2.2 nathanw ((PCI_PRODUCT_TRIDENT_4DWAVE_DX << 16) | PCI_VENDOR_TRIDENT) 38 1.1.2.2 nathanw #define AUTRI_DEVICE_ID_4DWAVE_NX \ 39 1.1.2.2 nathanw ((PCI_PRODUCT_TRIDENT_4DWAVE_NX << 16) | PCI_VENDOR_TRIDENT) 40 1.1.2.2 nathanw #define AUTRI_DEVICE_ID_SIS_7018 \ 41 1.1.2.2 nathanw ((PCI_PRODUCT_SIS_7018 << 16) | PCI_VENDOR_SIS) 42 1.1.2.2 nathanw #define AUTRI_DEVICE_ID_ALI_M5451 \ 43 1.1.2.2 nathanw ((PCI_PRODUCT_ALI_M5451 << 16) | PCI_VENDOR_ALI) 44 1.1.2.2 nathanw 45 1.1.2.2 nathanw /* 46 1.1.2.2 nathanw * PCI Config Registers 47 1.1.2.2 nathanw */ 48 1.1.2.2 nathanw #define AUTRI_PCI_MEMORY_BASE 0x14 49 1.1.2.2 nathanw #define AUTRI_PCI_DDMA_CFG 0x40 50 1.1.2.2 nathanw #define AUTRI_PCI_LEGACY_IOBASE 0x44 51 1.1.2.2 nathanw 52 1.1.2.2 nathanw /* 53 1.1.2.2 nathanw * AC'97 Registers 54 1.1.2.2 nathanw */ 55 1.1.2.2 nathanw #define AUTRI_DX_ACR0 0x40 56 1.1.2.2 nathanw # define AUTRI_DX_ACR0_CMD_WRITE 0x00008000 57 1.1.2.2 nathanw # define AUTRI_DX_ACR0_BUSY_WRITE 0x00008000 58 1.1.2.2 nathanw #define AUTRI_DX_ACR1 0x44 59 1.1.2.2 nathanw # define AUTRI_DX_ACR1_CMD_READ 0x00008000 60 1.1.2.2 nathanw # define AUTRI_DX_ACR1_BUSY_READ 0x00008000 61 1.1.2.2 nathanw #define AUTRI_DX_ACR2 0x48 62 1.1.2.2 nathanw # define AUTRI_DX_ACR2_CODEC_READY 0x00000010 63 1.1.2.2 nathanw 64 1.1.2.2 nathanw #define AUTRI_NX_ACR0 0x40 65 1.1.2.2 nathanw # define AUTRI_NX_ACR0_PSB_CAPTURE 0x00000200 66 1.1.2.2 nathanw # define AUTRI_NX_ACR0_CODEC_READY 0x00000008 67 1.1.2.2 nathanw #define AUTRI_NX_ACR1 0x44 68 1.1.2.2 nathanw # define AUTRI_NX_ACR1_CMD_WRITE 0x00000800 69 1.1.2.2 nathanw # define AUTRI_NX_ACR1_BUSY_WRITE 0x00000800 70 1.1.2.2 nathanw #define AUTRI_NX_ACR2 0x48 71 1.1.2.2 nathanw # define AUTRI_NX_ACR2_CMD_READ 0x00000800 72 1.1.2.2 nathanw # define AUTRI_NX_ACR2_BUSY_READ 0x00000800 73 1.1.2.2 nathanw # define AUTRI_NX_ACR2_RECV_WAIT 0x00000400 74 1.1.2.2 nathanw #define AUTRI_NX_ACR3 0x4c 75 1.1.2.2 nathanw 76 1.1.2.2 nathanw #define AUTRI_SIS_ACWR 0x40 77 1.1.2.2 nathanw # define AUTRI_SIS_ACWR_CMD_WRITE 0x00008000 78 1.1.2.2 nathanw # define AUTRI_SIS_ACWR_BUSY_WRITE 0x00008000 79 1.1.2.2 nathanw # define AUTRI_SIS_ACWR_AUDIO_BUSY 0x00004000 80 1.1.2.2 nathanw #define AUTRI_SIS_ACRD 0x44 81 1.1.2.2 nathanw # define AUTRI_SIS_ACRD_CMD_READ 0x00008000 82 1.1.2.2 nathanw # define AUTRI_SIS_ACRD_BUSY_READ 0x00008000 83 1.1.2.2 nathanw # define AUTRI_SIS_ACRD_AUDIO_BUSY 0x00004000 84 1.1.2.2 nathanw #define AUTRI_SIS_SCTRL 0x48 85 1.1.2.2 nathanw # define AUTRI_SIS_SCTRL_CODEC_READY 0x01000000 86 1.1.2.2 nathanw #define AUTRI_SIS_ACGPIO 0x4c 87 1.1.2.2 nathanw 88 1.1.2.2 nathanw #define AUTRI_ALI_ACWR 0x40 89 1.1.2.2 nathanw # define AUTRI_ALI_ACWR_CMD_WRITE 0x00008000 90 1.1.2.2 nathanw # define AUTRI_ALI_ACWR_BUSY_WRITE 0x00008000 91 1.1.2.2 nathanw #define AUTRI_ALI_ACRD 0x44 92 1.1.2.2 nathanw # define AUTRI_ALI_ACRD_CMD_READ 0x00008000 93 1.1.2.2 nathanw # define AUTRI_ALI_ACRD_BUSY_READ 0x00008000 94 1.1.2.2 nathanw #define AUTRI_ALI_SCTRL 0x48 95 1.1.2.2 nathanw # define AUTRI_ALI_SCTRL_CODEC_READY 0x01000000 96 1.1.2.2 nathanw #define AUTRI_ALI_ACGPIO 0x4c 97 1.1.2.2 nathanw /* 98 1.1.2.2 nathanw # define AUTRI_ALI_AC97_BUSY_READ 0x00008000 99 1.1.2.2 nathanw # define AUTRI_ALI_AC97_BUSY_WRITE 0x00008000 100 1.1.2.2 nathanw # define AUTRI_ALI_AC97_CMD_WRITE 0x00008000 101 1.1.2.2 nathanw */ 102 1.1.2.2 nathanw 103 1.1.2.2 nathanw /* 104 1.1.2.2 nathanw * MPU-401 UART 105 1.1.2.2 nathanw */ 106 1.1.2.2 nathanw #define AUTRI_MPUR0 0x20 107 1.1.2.2 nathanw #define AUTRI_MPUR1 0x21 108 1.1.2.2 nathanw # define AUTRI_MIDIOUT_READY 0x40 109 1.1.2.2 nathanw #define AUTRI_MPUR2 0x22 110 1.1.2.2 nathanw # define AUTRI_MIDIOUT_CONNECT 0x10 111 1.1.2.2 nathanw # define AUTRI_MIDIIN_ENABLE_INTR 0x08 112 1.1.2.2 nathanw 113 1.1.2.2 nathanw #define MIDI_BUSY_WAIT 100 114 1.1.2.2 nathanw #define MIDI_BUSY_DELAY 100 115 1.1.2.2 nathanw 116 1.1.2.2 nathanw /* 117 1.1.2.2 nathanw * Channel Registers 118 1.1.2.2 nathanw */ 119 1.1.2.2 nathanw #define AUTRI_START_A 0x80 120 1.1.2.2 nathanw #define AUTRI_STOP_A 0x84 121 1.1.2.2 nathanw #define AUTRI_DLY_A 0x88 122 1.1.2.2 nathanw #define AUTRI_SIGN_CSO_A 0x8c 123 1.1.2.2 nathanw #define AUTRI_CSPF_A 0x90 124 1.1.2.2 nathanw #define AUTRI_CEBC_A 0x94 125 1.1.2.2 nathanw #define AUTRI_AIN_A 0x98 126 1.1.2.2 nathanw #define AUTRI_EINT_A 0x9c 127 1.1.2.2 nathanw #define AUTRI_LFO_GC_CIR 0xa0 128 1.1.2.2 nathanw # define ENDLP_IE 0x00001000 129 1.1.2.2 nathanw # define MIDLP_IE 0x00002000 130 1.1.2.2 nathanw # define BANK_B_EN 0x00010000 131 1.1.2.2 nathanw #define AUTRI_AINTEN_A 0xa4 132 1.1.2.2 nathanw #define AUTRI_MUSICVOL_WAVEVOL 0xa8 133 1.1.2.2 nathanw #define AUTRI_MISCINT 0xb0 134 1.1.2.2 nathanw # define ST_TARGET_REACHED 0x00008000 135 1.1.2.2 nathanw # define MIXER_OVERFLOW 0x00000800 136 1.1.2.2 nathanw # define MIXER_UNDERFLOW 0x00000800 137 1.1.2.2 nathanw # define ADDRESS_IRQ 0x00000020 138 1.1.2.2 nathanw # define MPU401_IRQ 0x00000008 139 1.1.2.2 nathanw #define AUTRI_START_B 0xb4 140 1.1.2.2 nathanw #define AUTRI_STOP_B 0xb8 141 1.1.2.2 nathanw #define AUTRI_CSPF_B 0xbc 142 1.1.2.2 nathanw #define AUTRI_AIN_B 0xd8 143 1.1.2.2 nathanw #define AUTRI_AINTEN_B 0xdc 144 1.1.2.2 nathanw 145 1.1.2.2 nathanw /* 146 1.1.2.2 nathanw * Indexed Channel Registers 147 1.1.2.2 nathanw */ 148 1.1.2.2 nathanw #define AUTRI_ARAM_CR 0xe0 149 1.1.2.2 nathanw # define AUTRI_CTRL_WAVEVOL 0x80000000 150 1.1.2.3 nathanw # define AUTRI_CTRL_MUTEVOL 0x3fff0000 151 1.1.2.3 nathanw # define AUTRI_CTRL_MUTEVOL_SIS 0x3f000fff 152 1.1.2.2 nathanw # define AUTRI_CTRL_16BIT 0x00008000 153 1.1.2.2 nathanw # define AUTRI_CTRL_STEREO 0x00004000 154 1.1.2.2 nathanw # define AUTRI_CTRL_SIGNED 0x00002000 155 1.1.2.2 nathanw # define AUTRI_CTRL_LOOPMODE 0x00001000 156 1.1.2.2 nathanw #define AUTRI_EBUF1 0xf4 157 1.1.2.2 nathanw #define AUTRI_EBUF2 0xf8 158 1.1.2.2 nathanw # define AUTRI_EMOD_STILL 0x30000000 159 1.1.2.2 nathanw 160 1.1.2.2 nathanw /* 161 1.1.2.2 nathanw * Others 162 1.1.2.2 nathanw */ 163 1.1.2.2 nathanw #define AUTRI_NX_RCI3 0x73 164 1.1.2.2 nathanw # define AUTRI_NX_RCI3_ENABLE 0x80 165 1.1.2.2 nathanw 166 1.1.2.2 nathanw #define AUTRI_ALI_GCONTROL 0xd4 167 1.1.2.2 nathanw # define AUTRI_ALI_GCONTROL_PCM_IN 0x80000000 168 1.1.2.2 nathanw 169 1.1.2.2 nathanw 170 1.1.2.2 nathanw #endif /* _DEV_PCI_AUTRIREG_H_ */ 171
Indexes created Thu Oct 23 22:10:10 GMT 2025