cac_pci.c revision 1.8.2.2
1 /* $NetBSD: cac_pci.c,v 1.8.2.2 2000/11/20 11:42:15 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * PCI front-end for cac(4) driver. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/queue.h> 48 49 #include <machine/endian.h> 50 #include <machine/bus.h> 51 52 #include <dev/pci/pcidevs.h> 53 #include <dev/pci/pcivar.h> 54 55 #include <dev/ic/cacreg.h> 56 #include <dev/ic/cacvar.h> 57 58 #define PCI_CBIO 0x10 /* Configuration base I/O address */ 59 #define PCI_CBMA 0x14 /* Configuration base memory address */ 60 61 static void cac_pci_attach(struct device *, struct device *, void *); 62 static int cac_pci_match(struct device *, struct cfdata *, void *); 63 64 static struct cac_ccb *cac_pci_l0_completed(struct cac_softc *); 65 static int cac_pci_l0_fifo_full(struct cac_softc *); 66 static void cac_pci_l0_intr_enable(struct cac_softc *, int); 67 static int cac_pci_l0_intr_pending(struct cac_softc *); 68 static void cac_pci_l0_submit(struct cac_softc *, struct cac_ccb *); 69 70 struct cfattach cac_pci_ca = { 71 sizeof(struct cac_softc), cac_pci_match, cac_pci_attach 72 }; 73 74 static struct cac_linkage cac_pci_l0 = { 75 cac_pci_l0_completed, 76 cac_pci_l0_fifo_full, 77 cac_pci_l0_intr_enable, 78 cac_pci_l0_intr_pending, 79 cac_pci_l0_submit 80 }; 81 82 #define CT_IOMAP 0x01 /* Use I/O port access */ 83 #define CT_STARTFW 0x02 /* Need to start controller firmware */ 84 85 struct cac_pci_type { 86 int ct_subsysid; 87 int ct_flags; 88 struct cac_linkage *ct_linkage; 89 char *ct_typestr; 90 } static cac_pci_type[] = { 91 { 0x3040110e, CT_IOMAP, &cac_l0, "SMART-2/E" }, 92 { 0x40300e11, 0, &cac_l0, "SMART-2/P" }, 93 { 0x40310e11, 0, &cac_l0, "SMART-2SL" }, 94 { 0x40320e11, 0, &cac_l0, "Smart Array 3200" }, 95 { 0x40330e11, 0, &cac_l0, "Smart Array 3100ES" }, 96 { 0x40340e11, 0, &cac_l0, "Smart Array 221" }, 97 { 0x40400e11, CT_STARTFW, &cac_pci_l0, "Integrated Array" }, 98 { 0x40480e11, CT_STARTFW, &cac_pci_l0, "RAID LC2" }, 99 { 0x40500e11, 0, &cac_pci_l0, "Smart Array 4200" }, 100 { 0x40510e11, 0, &cac_pci_l0, "Smart Array 4200ES" }, 101 { 0x40580e11, 0, &cac_pci_l0, "Smart Array 431" }, 102 { 0, 0, &cac_l0, NULL }, 103 }; 104 105 static int 106 cac_pci_match(struct device *parent, struct cfdata *match, void *aux) 107 { 108 struct pci_attach_args *pa; 109 110 pa = (struct pci_attach_args *)aux; 111 112 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_COMPAQ && 113 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_COMPAQ_SMART2P) 114 return (1); 115 116 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_DEC && 117 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_DEC_CPQ42XX) 118 return (1); 119 120 return (0); 121 } 122 123 static void 124 cac_pci_attach(struct device *parent, struct device *self, void *aux) 125 { 126 struct pci_attach_args *pa; 127 struct cac_pci_type *ct; 128 struct cac_softc *sc; 129 pci_chipset_tag_t pc; 130 pci_intr_handle_t ih; 131 const char *intrstr; 132 pcireg_t csr, subsysid; 133 int flags; 134 135 sc = (struct cac_softc *)self; 136 pa = (struct pci_attach_args *)aux; 137 pc = pa->pa_pc; 138 139 subsysid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 140 141 for (ct = cac_pci_type; ct->ct_subsysid != 0; ct++) 142 if (subsysid == ct->ct_subsysid) 143 break; 144 145 if (((flags = ct->ct_flags) & CT_IOMAP) == 0) 146 if (pci_mapreg_map(pa, PCI_CBMA, PCI_MAPREG_TYPE_MEM, 0, 147 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) 148 flags |= CT_IOMAP; 149 150 if ((flags & CT_IOMAP) != 0) 151 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 152 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 153 printf("can't map i/o space\n"); 154 return; 155 } 156 157 sc->sc_dmat = pa->pa_dmat; 158 159 /* Enable the device. */ 160 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 161 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 162 csr | PCI_COMMAND_MASTER_ENABLE); 163 164 /* Map and establish the interrupt. */ 165 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 166 pa->pa_intrline, &ih)) { 167 printf("can't map interrupt\n"); 168 return; 169 } 170 intrstr = pci_intr_string(pc, ih); 171 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, cac_intr, sc); 172 if (sc->sc_ih == NULL) { 173 printf("can't establish interrupt"); 174 if (intrstr != NULL) 175 printf(" at %s", intrstr); 176 printf("\n"); 177 return; 178 } 179 180 printf(": Compaq "); 181 if (ct->ct_typestr == NULL) { 182 printf("array controller\n%s: unknown subsystem ID: 0x%08x\n", 183 sc->sc_dv.dv_xname, (u_int)subsysid); 184 } else 185 printf("%s\n", ct->ct_typestr); 186 187 /* Now attach to the bus-independent code. */ 188 sc->sc_cl = ct->ct_linkage; 189 cac_init(sc, intrstr, (flags & CT_STARTFW) != 0); 190 } 191 192 static void 193 cac_pci_l0_submit(struct cac_softc *sc, struct cac_ccb *ccb) 194 { 195 196 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, (caddr_t)ccb - sc->sc_ccbs, 197 sizeof(struct cac_ccb), BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 198 cac_outl(sc, CAC_42REG_CMD_FIFO, ccb->ccb_paddr); 199 } 200 201 static struct cac_ccb * 202 cac_pci_l0_completed(struct cac_softc *sc) 203 { 204 struct cac_ccb *ccb; 205 u_int32_t off; 206 207 if ((off = cac_inl(sc, CAC_42REG_DONE_FIFO)) == 0xffffffffU) 208 return (0); 209 210 cac_outl(sc, CAC_42REG_DONE_FIFO, 0); 211 off = (off & ~3) - sc->sc_ccbs_paddr; 212 ccb = (struct cac_ccb *)(sc->sc_ccbs + off); 213 214 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, off, sizeof(struct cac_ccb), 215 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 216 217 return (ccb); 218 } 219 220 static int 221 cac_pci_l0_intr_pending(struct cac_softc *sc) 222 { 223 224 return (cac_inl(sc, CAC_42REG_INTR_PENDING) & 225 cac_inl(sc, CAC_42REG_STATUS)); 226 } 227 228 static void 229 cac_pci_l0_intr_enable(struct cac_softc *sc, int state) 230 { 231 232 cac_outl(sc, CAC_42REG_INTR_MASK, (state ? 0 : 8)); /* XXX */ 233 } 234 235 static int 236 cac_pci_l0_fifo_full(struct cac_softc *sc) 237 { 238 239 return (~cac_inl(sc, CAC_42REG_CMD_FIFO)); 240 } 241
Indexes created Tue Sep 30 20:09:53 GMT 2025