ciss_pci.c revision 1.1.12.2 1 1.1.12.2 simonb /* $NetBSD: ciss_pci.c,v 1.1.12.2 2006/04/22 11:39:13 simonb Exp $ */
2 1.1.12.2 simonb /* $OpenBSD: ciss_pci.c,v 1.9 2005/12/13 15:56:01 brad Exp $ */
3 1.1.12.2 simonb
4 1.1.12.2 simonb /*
5 1.1.12.2 simonb * Copyright (c) 2005 Michael Shalayeff
6 1.1.12.2 simonb * All rights reserved.
7 1.1.12.2 simonb *
8 1.1.12.2 simonb * Permission to use, copy, modify, and distribute this software for any
9 1.1.12.2 simonb * purpose with or without fee is hereby granted, provided that the above
10 1.1.12.2 simonb * copyright notice and this permission notice appear in all copies.
11 1.1.12.2 simonb *
12 1.1.12.2 simonb * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 1.1.12.2 simonb * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 1.1.12.2 simonb * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 1.1.12.2 simonb * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 1.1.12.2 simonb * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
17 1.1.12.2 simonb * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
18 1.1.12.2 simonb * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 1.1.12.2 simonb */
20 1.1.12.2 simonb
21 1.1.12.2 simonb #include <sys/cdefs.h>
22 1.1.12.2 simonb __KERNEL_RCSID(0, "$NetBSD: ciss_pci.c,v 1.1.12.2 2006/04/22 11:39:13 simonb Exp $");
23 1.1.12.2 simonb
24 1.1.12.2 simonb #include <sys/param.h>
25 1.1.12.2 simonb #include <sys/systm.h>
26 1.1.12.2 simonb #include <sys/kernel.h>
27 1.1.12.2 simonb #include <sys/malloc.h>
28 1.1.12.2 simonb #include <sys/device.h>
29 1.1.12.2 simonb
30 1.1.12.2 simonb #include <dev/pci/pcidevs.h>
31 1.1.12.2 simonb #include <dev/pci/pcivar.h>
32 1.1.12.2 simonb
33 1.1.12.2 simonb #include <machine/bus.h>
34 1.1.12.2 simonb
35 1.1.12.2 simonb #include <dev/scsipi/scsipi_all.h>
36 1.1.12.2 simonb #include <dev/scsipi/scsipi_disk.h>
37 1.1.12.2 simonb #include <dev/scsipi/scsipiconf.h>
38 1.1.12.2 simonb
39 1.1.12.2 simonb #include <dev/ic/cissreg.h>
40 1.1.12.2 simonb #include <dev/ic/cissvar.h>
41 1.1.12.2 simonb
42 1.1.12.2 simonb #define CISS_BAR 0x10
43 1.1.12.2 simonb
44 1.1.12.2 simonb int ciss_pci_match(struct device *, struct cfdata *, void *);
45 1.1.12.2 simonb void ciss_pci_attach(struct device *, struct device *, void *);
46 1.1.12.2 simonb
47 1.1.12.2 simonb CFATTACH_DECL(ciss_pci, sizeof(struct ciss_softc),
48 1.1.12.2 simonb ciss_pci_match, ciss_pci_attach, NULL, NULL);
49 1.1.12.2 simonb
50 1.1.12.2 simonb const struct {
51 1.1.12.2 simonb int vendor;
52 1.1.12.2 simonb int product;
53 1.1.12.2 simonb const char *name;
54 1.1.12.2 simonb } ciss_pci_devices[] = {
55 1.1.12.2 simonb {
56 1.1.12.2 simonb PCI_VENDOR_COMPAQ,
57 1.1.12.2 simonb PCI_PRODUCT_COMPAQ_CSA532,
58 1.1.12.2 simonb "Compaq Smart Array 532"
59 1.1.12.2 simonb },
60 1.1.12.2 simonb {
61 1.1.12.2 simonb PCI_VENDOR_COMPAQ,
62 1.1.12.2 simonb PCI_PRODUCT_COMPAQ_CSA5300,
63 1.1.12.2 simonb "Compaq Smart Array 5300 V1"
64 1.1.12.2 simonb },
65 1.1.12.2 simonb {
66 1.1.12.2 simonb PCI_VENDOR_COMPAQ,
67 1.1.12.2 simonb PCI_PRODUCT_COMPAQ_CSA5300_2,
68 1.1.12.2 simonb "Compaq Smart Array 5300 V2"
69 1.1.12.2 simonb },
70 1.1.12.2 simonb {
71 1.1.12.2 simonb PCI_VENDOR_COMPAQ,
72 1.1.12.2 simonb PCI_PRODUCT_COMPAQ_CSA5312,
73 1.1.12.2 simonb "Compaq Smart Array 5312"
74 1.1.12.2 simonb },
75 1.1.12.2 simonb {
76 1.1.12.2 simonb PCI_VENDOR_COMPAQ,
77 1.1.12.2 simonb PCI_PRODUCT_COMPAQ_CSA5i,
78 1.1.12.2 simonb "Compaq Smart Array 5i"
79 1.1.12.2 simonb },
80 1.1.12.2 simonb {
81 1.1.12.2 simonb PCI_VENDOR_COMPAQ,
82 1.1.12.2 simonb PCI_PRODUCT_COMPAQ_CSA5i_2,
83 1.1.12.2 simonb "Compaq Smart Array 5i V2"
84 1.1.12.2 simonb },
85 1.1.12.2 simonb {
86 1.1.12.2 simonb PCI_VENDOR_COMPAQ,
87 1.1.12.2 simonb PCI_PRODUCT_COMPAQ_CSA6i,
88 1.1.12.2 simonb "Compaq Smart Array 6i"
89 1.1.12.2 simonb },
90 1.1.12.2 simonb {
91 1.1.12.2 simonb PCI_VENDOR_COMPAQ,
92 1.1.12.2 simonb PCI_PRODUCT_COMPAQ_CSA641,
93 1.1.12.2 simonb "Compaq Smart Array 641"
94 1.1.12.2 simonb },
95 1.1.12.2 simonb {
96 1.1.12.2 simonb PCI_VENDOR_COMPAQ,
97 1.1.12.2 simonb PCI_PRODUCT_COMPAQ_CSA642,
98 1.1.12.2 simonb "Compaq Smart Array 642"
99 1.1.12.2 simonb },
100 1.1.12.2 simonb {
101 1.1.12.2 simonb PCI_VENDOR_COMPAQ,
102 1.1.12.2 simonb PCI_PRODUCT_COMPAQ_CSA6400,
103 1.1.12.2 simonb "Compaq Smart Array 6400"
104 1.1.12.2 simonb },
105 1.1.12.2 simonb {
106 1.1.12.2 simonb PCI_VENDOR_COMPAQ,
107 1.1.12.2 simonb PCI_PRODUCT_COMPAQ_CSA6400EM,
108 1.1.12.2 simonb "Compaq Smart Array 6400EM"
109 1.1.12.2 simonb },
110 1.1.12.2 simonb {
111 1.1.12.2 simonb PCI_VENDOR_COMPAQ,
112 1.1.12.2 simonb PCI_PRODUCT_COMPAQ_CSA6422,
113 1.1.12.2 simonb "Compaq Smart Array 6422"
114 1.1.12.2 simonb },
115 1.1.12.2 simonb {
116 1.1.12.2 simonb PCI_VENDOR_COMPAQ,
117 1.1.12.2 simonb PCI_PRODUCT_COMPAQ_CSA64XX,
118 1.1.12.2 simonb "Compaq Smart Array 64XX"
119 1.1.12.2 simonb },
120 1.1.12.2 simonb {
121 1.1.12.2 simonb PCI_VENDOR_HP,
122 1.1.12.2 simonb PCI_PRODUCT_HP_HPSAE200,
123 1.1.12.2 simonb "Smart Array E200"
124 1.1.12.2 simonb },
125 1.1.12.2 simonb {
126 1.1.12.2 simonb PCI_VENDOR_HP,
127 1.1.12.2 simonb PCI_PRODUCT_HP_HPSAE200I_1,
128 1.1.12.2 simonb "HP Smart Array E200I-1"
129 1.1.12.2 simonb },
130 1.1.12.2 simonb {
131 1.1.12.2 simonb PCI_VENDOR_HP,
132 1.1.12.2 simonb PCI_PRODUCT_HP_HPSAE200I_2,
133 1.1.12.2 simonb "HP Smart Array E200I-2"
134 1.1.12.2 simonb },
135 1.1.12.2 simonb {
136 1.1.12.2 simonb PCI_VENDOR_HP,
137 1.1.12.2 simonb PCI_PRODUCT_HP_HPSAE200I_3,
138 1.1.12.2 simonb "HP Smart Array E200I-3"
139 1.1.12.2 simonb },
140 1.1.12.2 simonb {
141 1.1.12.2 simonb PCI_VENDOR_HP,
142 1.1.12.2 simonb PCI_PRODUCT_HP_HPSAP600,
143 1.1.12.2 simonb "HP Smart Array P600"
144 1.1.12.2 simonb },
145 1.1.12.2 simonb {
146 1.1.12.2 simonb PCI_VENDOR_HP,
147 1.1.12.2 simonb PCI_PRODUCT_HP_HPSAP800,
148 1.1.12.2 simonb "HP Smart Array P800"
149 1.1.12.2 simonb },
150 1.1.12.2 simonb {
151 1.1.12.2 simonb PCI_VENDOR_HP,
152 1.1.12.2 simonb PCI_PRODUCT_HP_HPSAV100,
153 1.1.12.2 simonb "HP Smart Array V100"
154 1.1.12.2 simonb },
155 1.1.12.2 simonb {
156 1.1.12.2 simonb PCI_VENDOR_HP,
157 1.1.12.2 simonb PCI_PRODUCT_HP_HPSA_1,
158 1.1.12.2 simonb "HP Smart Array 1"
159 1.1.12.2 simonb },
160 1.1.12.2 simonb {
161 1.1.12.2 simonb PCI_VENDOR_HP,
162 1.1.12.2 simonb PCI_PRODUCT_HP_HPSA_2,
163 1.1.12.2 simonb "HP Smart Array 2"
164 1.1.12.2 simonb },
165 1.1.12.2 simonb {
166 1.1.12.2 simonb PCI_VENDOR_HP,
167 1.1.12.2 simonb PCI_PRODUCT_HP_HPSA_3,
168 1.1.12.2 simonb "HP Smart Array 3"
169 1.1.12.2 simonb },
170 1.1.12.2 simonb {
171 1.1.12.2 simonb PCI_VENDOR_HP,
172 1.1.12.2 simonb PCI_PRODUCT_HP_HPSA_4,
173 1.1.12.2 simonb "HP Smart Array 4"
174 1.1.12.2 simonb },
175 1.1.12.2 simonb {
176 1.1.12.2 simonb PCI_VENDOR_HP,
177 1.1.12.2 simonb PCI_PRODUCT_HP_HPSA_5,
178 1.1.12.2 simonb "HP Smart Array 5"
179 1.1.12.2 simonb },
180 1.1.12.2 simonb {
181 1.1.12.2 simonb PCI_VENDOR_HP,
182 1.1.12.2 simonb PCI_PRODUCT_HP_HPSA_6,
183 1.1.12.2 simonb "HP Smart Array 6"
184 1.1.12.2 simonb },
185 1.1.12.2 simonb {
186 1.1.12.2 simonb PCI_VENDOR_HP,
187 1.1.12.2 simonb PCI_PRODUCT_HP_HPSA_7,
188 1.1.12.2 simonb "HP Smart Array 7"
189 1.1.12.2 simonb },
190 1.1.12.2 simonb {
191 1.1.12.2 simonb PCI_VENDOR_HP,
192 1.1.12.2 simonb PCI_PRODUCT_HP_HPSA_8,
193 1.1.12.2 simonb "HP Smart Array 8"
194 1.1.12.2 simonb },
195 1.1.12.2 simonb {
196 1.1.12.2 simonb PCI_VENDOR_HP,
197 1.1.12.2 simonb PCI_PRODUCT_HP_HPSA_9,
198 1.1.12.2 simonb "HP Smart Array 9"
199 1.1.12.2 simonb },
200 1.1.12.2 simonb {
201 1.1.12.2 simonb PCI_VENDOR_HP,
202 1.1.12.2 simonb PCI_PRODUCT_HP_HPSA_10,
203 1.1.12.2 simonb "HP Smart Array 10"
204 1.1.12.2 simonb },
205 1.1.12.2 simonb {
206 1.1.12.2 simonb PCI_VENDOR_HP,
207 1.1.12.2 simonb PCI_PRODUCT_HP_HPSA_11,
208 1.1.12.2 simonb "HP Smart Array 11"
209 1.1.12.2 simonb },
210 1.1.12.2 simonb {
211 1.1.12.2 simonb PCI_VENDOR_HP,
212 1.1.12.2 simonb PCI_PRODUCT_HP_HPSA_12,
213 1.1.12.2 simonb "HP Smart Array 12"
214 1.1.12.2 simonb },
215 1.1.12.2 simonb {
216 1.1.12.2 simonb PCI_VENDOR_HP,
217 1.1.12.2 simonb PCI_PRODUCT_HP_HPSA_13,
218 1.1.12.2 simonb "HP Smart Array 13"
219 1.1.12.2 simonb },
220 1.1.12.2 simonb {
221 1.1.12.2 simonb 0,
222 1.1.12.2 simonb 0,
223 1.1.12.2 simonb NULL
224 1.1.12.2 simonb }
225 1.1.12.2 simonb };
226 1.1.12.2 simonb
227 1.1.12.2 simonb int
228 1.1.12.2 simonb ciss_pci_match(struct device *parent, struct cfdata *match, void *aux)
229 1.1.12.2 simonb {
230 1.1.12.2 simonb struct pci_attach_args *pa = aux;
231 1.1.12.2 simonb pcireg_t reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
232 1.1.12.2 simonb int i;
233 1.1.12.2 simonb
234 1.1.12.2 simonb for (i = 0; ciss_pci_devices[i].vendor; i++)
235 1.1.12.2 simonb {
236 1.1.12.2 simonb if ((PCI_VENDOR(pa->pa_id) == ciss_pci_devices[i].vendor &&
237 1.1.12.2 simonb PCI_PRODUCT(pa->pa_id) == ciss_pci_devices[i].product) ||
238 1.1.12.2 simonb (PCI_VENDOR(reg) == ciss_pci_devices[i].vendor &&
239 1.1.12.2 simonb PCI_PRODUCT(reg) == ciss_pci_devices[i].product))
240 1.1.12.2 simonb return 1;
241 1.1.12.2 simonb }
242 1.1.12.2 simonb
243 1.1.12.2 simonb return 0;
244 1.1.12.2 simonb }
245 1.1.12.2 simonb
246 1.1.12.2 simonb void
247 1.1.12.2 simonb ciss_pci_attach(struct device *parent, struct device *self, void *aux)
248 1.1.12.2 simonb {
249 1.1.12.2 simonb struct ciss_softc *sc = (struct ciss_softc *)self;
250 1.1.12.2 simonb struct pci_attach_args *pa = aux;
251 1.1.12.2 simonb bus_size_t size, cfgsz;
252 1.1.12.2 simonb pci_intr_handle_t ih;
253 1.1.12.2 simonb const char *intrstr;
254 1.1.12.2 simonb int cfg_bar, memtype;
255 1.1.12.2 simonb pcireg_t reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
256 1.1.12.2 simonb int i;
257 1.1.12.2 simonb
258 1.1.12.2 simonb for (i = 0; ciss_pci_devices[i].vendor; i++)
259 1.1.12.2 simonb {
260 1.1.12.2 simonb if ((PCI_VENDOR(pa->pa_id) == ciss_pci_devices[i].vendor &&
261 1.1.12.2 simonb PCI_PRODUCT(pa->pa_id) == ciss_pci_devices[i].product) ||
262 1.1.12.2 simonb (PCI_VENDOR(reg) == ciss_pci_devices[i].vendor &&
263 1.1.12.2 simonb PCI_PRODUCT(reg) == ciss_pci_devices[i].product))
264 1.1.12.2 simonb {
265 1.1.12.2 simonb printf(": %s\n", ciss_pci_devices[i].name);
266 1.1.12.2 simonb break;
267 1.1.12.2 simonb }
268 1.1.12.2 simonb }
269 1.1.12.2 simonb
270 1.1.12.2 simonb memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, CISS_BAR);
271 1.1.12.2 simonb if (memtype != (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT) &&
272 1.1.12.2 simonb memtype != (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT)) {
273 1.1.12.2 simonb printf(": wrong BAR type\n");
274 1.1.12.2 simonb return;
275 1.1.12.2 simonb }
276 1.1.12.2 simonb if (pci_mapreg_map(pa, CISS_BAR, memtype, 0,
277 1.1.12.2 simonb &sc->sc_iot, &sc->sc_ioh, NULL, &size)) {
278 1.1.12.2 simonb printf(": can't map controller i/o space\n");
279 1.1.12.2 simonb return;
280 1.1.12.2 simonb }
281 1.1.12.2 simonb sc->sc_dmat = pa->pa_dmat;
282 1.1.12.2 simonb
283 1.1.12.2 simonb sc->iem = CISS_READYENA;
284 1.1.12.2 simonb reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
285 1.1.12.2 simonb if (PCI_VENDOR(reg) == PCI_VENDOR_COMPAQ &&
286 1.1.12.2 simonb (PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA5i ||
287 1.1.12.2 simonb PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA532 ||
288 1.1.12.2 simonb PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA5312))
289 1.1.12.2 simonb sc->iem = CISS_READYENAB;
290 1.1.12.2 simonb
291 1.1.12.2 simonb cfg_bar = bus_space_read_2(sc->sc_iot, sc->sc_ioh, CISS_CFG_BAR);
292 1.1.12.2 simonb sc->cfgoff = bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_CFG_OFF);
293 1.1.12.2 simonb if (cfg_bar != CISS_BAR) {
294 1.1.12.2 simonb if (pci_mapreg_map(pa, cfg_bar, PCI_MAPREG_TYPE_MEM, 0,
295 1.1.12.2 simonb NULL, &sc->cfg_ioh, NULL, &cfgsz)) {
296 1.1.12.2 simonb printf(": can't map controller config space\n");
297 1.1.12.2 simonb bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
298 1.1.12.2 simonb return;
299 1.1.12.2 simonb }
300 1.1.12.2 simonb } else {
301 1.1.12.2 simonb sc->cfg_ioh = sc->sc_ioh;
302 1.1.12.2 simonb cfgsz = size;
303 1.1.12.2 simonb }
304 1.1.12.2 simonb
305 1.1.12.2 simonb if (sc->cfgoff + sizeof(struct ciss_config) > cfgsz) {
306 1.1.12.2 simonb printf(": unfit config space\n");
307 1.1.12.2 simonb bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
308 1.1.12.2 simonb if (cfg_bar != CISS_BAR)
309 1.1.12.2 simonb bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
310 1.1.12.2 simonb return;
311 1.1.12.2 simonb }
312 1.1.12.2 simonb
313 1.1.12.2 simonb /* disable interrupts until ready */
314 1.1.12.2 simonb bus_space_write_4(sc->sc_iot, sc->sc_ioh, CISS_IMR,
315 1.1.12.2 simonb bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IMR) | sc->iem);
316 1.1.12.2 simonb
317 1.1.12.2 simonb if (pci_intr_map(pa, &ih)) {
318 1.1.12.2 simonb printf(": can't map interrupt\n");
319 1.1.12.2 simonb bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
320 1.1.12.2 simonb if (cfg_bar != CISS_BAR)
321 1.1.12.2 simonb bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
322 1.1.12.2 simonb return;
323 1.1.12.2 simonb }
324 1.1.12.2 simonb intrstr = pci_intr_string(pa->pa_pc, ih);
325 1.1.12.2 simonb sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ciss_intr, sc);
326 1.1.12.2 simonb if (!sc->sc_ih) {
327 1.1.12.2 simonb printf("%s: can't establish interrupt", sc->sc_dev.dv_xname);
328 1.1.12.2 simonb if (intrstr)
329 1.1.12.2 simonb printf(" at %s", intrstr);
330 1.1.12.2 simonb printf("\n");
331 1.1.12.2 simonb bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
332 1.1.12.2 simonb if (cfg_bar != CISS_BAR)
333 1.1.12.2 simonb bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
334 1.1.12.2 simonb }
335 1.1.12.2 simonb
336 1.1.12.2 simonb printf("%s: interrupting at %s\n%s", sc->sc_dev.dv_xname, intrstr,
337 1.1.12.2 simonb sc->sc_dev.dv_xname);
338 1.1.12.2 simonb
339 1.1.12.2 simonb if (ciss_attach(sc)) {
340 1.1.12.2 simonb pci_intr_disestablish(pa->pa_pc, sc->sc_ih);
341 1.1.12.2 simonb sc->sc_ih = NULL;
342 1.1.12.2 simonb bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
343 1.1.12.2 simonb if (cfg_bar != CISS_BAR)
344 1.1.12.2 simonb bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
345 1.1.12.2 simonb return;
346 1.1.12.2 simonb }
347 1.1.12.2 simonb
348 1.1.12.2 simonb /* enable interrupts now */
349 1.1.12.2 simonb bus_space_write_4(sc->sc_iot, sc->sc_ioh, CISS_IMR,
350 1.1.12.2 simonb bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IMR) & ~sc->iem);
351 1.1.12.2 simonb }
352