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ciss_pci.c revision 1.9.22.1
      1  1.9.22.1     tls /*	$NetBSD: ciss_pci.c,v 1.9.22.1 2012/11/20 03:02:14 tls Exp $	*/
      2       1.1      he /*	$OpenBSD: ciss_pci.c,v 1.9 2005/12/13 15:56:01 brad Exp $	*/
      3       1.1      he 
      4       1.1      he /*
      5       1.1      he  * Copyright (c) 2005 Michael Shalayeff
      6       1.1      he  * All rights reserved.
      7       1.1      he  *
      8       1.1      he  * Permission to use, copy, modify, and distribute this software for any
      9       1.1      he  * purpose with or without fee is hereby granted, provided that the above
     10       1.1      he  * copyright notice and this permission notice appear in all copies.
     11       1.1      he  *
     12       1.1      he  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     13       1.1      he  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     14       1.1      he  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     15       1.1      he  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     16       1.1      he  * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
     17       1.1      he  * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
     18       1.1      he  * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     19       1.1      he  */
     20       1.1      he 
     21       1.1      he #include <sys/cdefs.h>
     22  1.9.22.1     tls __KERNEL_RCSID(0, "$NetBSD: ciss_pci.c,v 1.9.22.1 2012/11/20 03:02:14 tls Exp $");
     23       1.1      he 
     24       1.1      he #include <sys/param.h>
     25       1.1      he #include <sys/systm.h>
     26       1.1      he #include <sys/kernel.h>
     27       1.1      he #include <sys/malloc.h>
     28       1.1      he #include <sys/device.h>
     29       1.1      he 
     30       1.1      he #include <dev/pci/pcidevs.h>
     31       1.1      he #include <dev/pci/pcivar.h>
     32       1.1      he 
     33       1.4      ad #include <sys/bus.h>
     34       1.1      he 
     35       1.1      he #include <dev/scsipi/scsipi_all.h>
     36       1.1      he #include <dev/scsipi/scsipi_disk.h>
     37       1.1      he #include <dev/scsipi/scsipiconf.h>
     38       1.1      he 
     39       1.1      he #include <dev/ic/cissreg.h>
     40       1.1      he #include <dev/ic/cissvar.h>
     41       1.1      he 
     42       1.1      he #define	CISS_BAR	0x10
     43       1.1      he 
     44       1.7  cegger int	ciss_pci_match(device_t, cfdata_t, void *);
     45       1.7  cegger void	ciss_pci_attach(device_t, device_t, void *);
     46       1.1      he 
     47  1.9.22.1     tls CFATTACH_DECL_NEW(ciss_pci, sizeof(struct ciss_softc),
     48       1.1      he 	ciss_pci_match, ciss_pci_attach, NULL, NULL);
     49       1.1      he 
     50       1.1      he const struct {
     51       1.1      he 	int vendor;
     52       1.1      he 	int product;
     53       1.1      he 	const char *name;
     54       1.1      he } ciss_pci_devices[] = {
     55       1.1      he 	{
     56       1.1      he 		PCI_VENDOR_COMPAQ,
     57       1.1      he 		PCI_PRODUCT_COMPAQ_CSA532,
     58       1.1      he 		"Compaq Smart Array 532"
     59       1.1      he 	},
     60       1.1      he 	{
     61       1.1      he 		PCI_VENDOR_COMPAQ,
     62       1.1      he 		PCI_PRODUCT_COMPAQ_CSA5300,
     63       1.1      he 		"Compaq Smart Array 5300 V1"
     64       1.1      he 	},
     65       1.1      he 	{
     66       1.1      he 		PCI_VENDOR_COMPAQ,
     67       1.1      he 		PCI_PRODUCT_COMPAQ_CSA5300_2,
     68       1.1      he 		"Compaq Smart Array 5300 V2"
     69       1.1      he 	},
     70       1.1      he 	{
     71       1.1      he 		PCI_VENDOR_COMPAQ,
     72       1.1      he 		PCI_PRODUCT_COMPAQ_CSA5312,
     73       1.1      he 		"Compaq Smart Array 5312"
     74       1.1      he 	},
     75       1.1      he 	{
     76       1.1      he 		PCI_VENDOR_COMPAQ,
     77       1.1      he 		PCI_PRODUCT_COMPAQ_CSA5i,
     78       1.1      he 		"Compaq Smart Array 5i"
     79       1.1      he 	},
     80       1.1      he 	{
     81       1.1      he 		PCI_VENDOR_COMPAQ,
     82       1.1      he 		PCI_PRODUCT_COMPAQ_CSA5i_2,
     83       1.1      he 		"Compaq Smart Array 5i V2"
     84       1.1      he 	},
     85       1.1      he 	{
     86       1.1      he 		PCI_VENDOR_COMPAQ,
     87       1.1      he 		PCI_PRODUCT_COMPAQ_CSA6i,
     88       1.1      he 		"Compaq Smart Array 6i"
     89       1.1      he 	},
     90       1.1      he 	{
     91       1.1      he 		PCI_VENDOR_COMPAQ,
     92       1.1      he 		PCI_PRODUCT_COMPAQ_CSA641,
     93       1.1      he 		"Compaq Smart Array 641"
     94       1.1      he 	},
     95       1.1      he 	{
     96       1.1      he 		PCI_VENDOR_COMPAQ,
     97       1.1      he 		PCI_PRODUCT_COMPAQ_CSA642,
     98       1.1      he 		"Compaq Smart Array 642"
     99       1.1      he 	},
    100       1.1      he 	{
    101       1.1      he 		PCI_VENDOR_COMPAQ,
    102       1.1      he 		PCI_PRODUCT_COMPAQ_CSA6400,
    103       1.1      he 		"Compaq Smart Array 6400"
    104       1.1      he 	},
    105       1.1      he 	{
    106       1.1      he 		PCI_VENDOR_COMPAQ,
    107       1.1      he 		PCI_PRODUCT_COMPAQ_CSA6400EM,
    108       1.1      he 		"Compaq Smart Array 6400EM"
    109       1.1      he 	},
    110       1.1      he 	{
    111       1.1      he 		PCI_VENDOR_COMPAQ,
    112       1.1      he 		PCI_PRODUCT_COMPAQ_CSA6422,
    113       1.1      he 		"Compaq Smart Array 6422"
    114       1.1      he 	},
    115       1.1      he 	{
    116       1.1      he 		PCI_VENDOR_COMPAQ,
    117       1.1      he 		PCI_PRODUCT_COMPAQ_CSA64XX,
    118       1.1      he 		"Compaq Smart Array 64XX"
    119       1.1      he 	},
    120       1.1      he 	{
    121       1.1      he 		PCI_VENDOR_HP,
    122       1.1      he 		PCI_PRODUCT_HP_HPSAE200,
    123       1.1      he 		"Smart Array E200"
    124       1.1      he 	},
    125       1.1      he 	{
    126       1.1      he 		PCI_VENDOR_HP,
    127       1.1      he 		PCI_PRODUCT_HP_HPSAE200I_1,
    128       1.1      he 		"HP Smart Array E200I-1"
    129       1.1      he 	},
    130       1.1      he 	{
    131       1.1      he 		PCI_VENDOR_HP,
    132       1.1      he 		PCI_PRODUCT_HP_HPSAE200I_2,
    133       1.1      he 		"HP Smart Array E200I-2"
    134       1.1      he 	},
    135       1.1      he 	{
    136       1.1      he 		PCI_VENDOR_HP,
    137       1.1      he 		PCI_PRODUCT_HP_HPSAE200I_3,
    138       1.1      he 		"HP Smart Array E200I-3"
    139       1.1      he 	},
    140       1.1      he 	{
    141       1.1      he 		PCI_VENDOR_HP,
    142       1.1      he 		PCI_PRODUCT_HP_HPSAP600,
    143       1.1      he 		"HP Smart Array P600"
    144       1.1      he 	},
    145       1.1      he 	{
    146       1.1      he 		PCI_VENDOR_HP,
    147       1.1      he 		PCI_PRODUCT_HP_HPSAP800,
    148       1.1      he 		"HP Smart Array P800"
    149       1.1      he 	},
    150       1.1      he 	{
    151       1.1      he 		PCI_VENDOR_HP,
    152       1.1      he 		PCI_PRODUCT_HP_HPSAV100,
    153       1.1      he 		"HP Smart Array V100"
    154       1.1      he 	},
    155       1.1      he 	{
    156       1.1      he 		PCI_VENDOR_HP,
    157       1.1      he 		PCI_PRODUCT_HP_HPSA_1,
    158       1.1      he 		"HP Smart Array 1"
    159       1.1      he 	},
    160       1.1      he 	{
    161       1.1      he 		PCI_VENDOR_HP,
    162       1.1      he 		PCI_PRODUCT_HP_HPSA_2,
    163       1.1      he 		"HP Smart Array 2"
    164       1.1      he 	},
    165       1.1      he 	{
    166       1.1      he 		PCI_VENDOR_HP,
    167       1.1      he 		PCI_PRODUCT_HP_HPSA_3,
    168       1.1      he 		"HP Smart Array 3"
    169       1.1      he 	},
    170       1.1      he 	{
    171       1.1      he 		PCI_VENDOR_HP,
    172       1.1      he 		PCI_PRODUCT_HP_HPSA_4,
    173       1.1      he 		"HP Smart Array 4"
    174       1.1      he 	},
    175       1.1      he 	{
    176       1.1      he 		PCI_VENDOR_HP,
    177       1.1      he 		PCI_PRODUCT_HP_HPSA_5,
    178       1.1      he 		"HP Smart Array 5"
    179       1.1      he 	},
    180       1.1      he 	{
    181       1.1      he 		PCI_VENDOR_HP,
    182       1.1      he 		PCI_PRODUCT_HP_HPSA_6,
    183       1.1      he 		"HP Smart Array 6"
    184       1.1      he 	},
    185       1.1      he 	{
    186       1.1      he 		PCI_VENDOR_HP,
    187       1.1      he 		PCI_PRODUCT_HP_HPSA_7,
    188       1.1      he 		"HP Smart Array 7"
    189       1.1      he 	},
    190       1.1      he 	{
    191       1.1      he 		PCI_VENDOR_HP,
    192       1.1      he 		PCI_PRODUCT_HP_HPSA_8,
    193       1.1      he 		"HP Smart Array 8"
    194       1.1      he 	},
    195       1.1      he 	{
    196       1.1      he 		PCI_VENDOR_HP,
    197       1.1      he 		PCI_PRODUCT_HP_HPSA_9,
    198       1.1      he 		"HP Smart Array 9"
    199       1.1      he 	},
    200       1.1      he 	{
    201       1.1      he 		PCI_VENDOR_HP,
    202       1.1      he 		PCI_PRODUCT_HP_HPSA_10,
    203       1.1      he 		"HP Smart Array 10"
    204       1.1      he 	},
    205       1.1      he 	{
    206       1.1      he 		PCI_VENDOR_HP,
    207       1.1      he 		PCI_PRODUCT_HP_HPSA_11,
    208       1.1      he 		"HP Smart Array 11"
    209       1.1      he 	},
    210       1.1      he 	{
    211       1.1      he 		PCI_VENDOR_HP,
    212       1.1      he 		PCI_PRODUCT_HP_HPSA_12,
    213       1.1      he 		"HP Smart Array 12"
    214       1.1      he 	},
    215       1.1      he 	{
    216       1.1      he 		PCI_VENDOR_HP,
    217       1.1      he 		PCI_PRODUCT_HP_HPSA_13,
    218       1.1      he 		"HP Smart Array 13"
    219       1.1      he 	},
    220       1.1      he 	{
    221       1.1      he 		0,
    222       1.1      he 		0,
    223       1.1      he 		NULL
    224       1.1      he 	}
    225       1.1      he };
    226       1.1      he 
    227       1.1      he int
    228       1.7  cegger ciss_pci_match(device_t parent, cfdata_t match, void *aux)
    229       1.1      he {
    230       1.1      he 	struct pci_attach_args *pa = aux;
    231       1.1      he 	pcireg_t reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
    232       1.1      he 	int i;
    233       1.1      he 
    234       1.1      he 	for (i = 0; ciss_pci_devices[i].vendor; i++)
    235       1.1      he 	{
    236       1.1      he 		if ((PCI_VENDOR(pa->pa_id) == ciss_pci_devices[i].vendor &&
    237       1.1      he 		     PCI_PRODUCT(pa->pa_id) == ciss_pci_devices[i].product) ||
    238       1.1      he 		    (PCI_VENDOR(reg) == ciss_pci_devices[i].vendor &&
    239       1.1      he 		     PCI_PRODUCT(reg) == ciss_pci_devices[i].product))
    240       1.1      he 			return 1;
    241       1.1      he 	}
    242       1.1      he 
    243       1.1      he 	return 0;
    244       1.1      he }
    245       1.1      he 
    246       1.1      he void
    247       1.7  cegger ciss_pci_attach(device_t parent, device_t self, void *aux)
    248       1.1      he {
    249       1.8  cegger 	struct ciss_softc *sc = device_private(self);
    250       1.1      he 	struct pci_attach_args *pa = aux;
    251       1.1      he 	bus_size_t size, cfgsz;
    252       1.1      he 	pci_intr_handle_t ih;
    253       1.1      he 	const char *intrstr;
    254       1.1      he 	int cfg_bar, memtype;
    255       1.1      he 	pcireg_t reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
    256       1.1      he 	int i;
    257       1.1      he 
    258  1.9.22.1     tls 	sc->sc_dev = self;
    259  1.9.22.1     tls 
    260       1.1      he 	for (i = 0; ciss_pci_devices[i].vendor; i++)
    261       1.1      he 	{
    262       1.1      he 		if ((PCI_VENDOR(pa->pa_id) == ciss_pci_devices[i].vendor &&
    263       1.1      he 		     PCI_PRODUCT(pa->pa_id) == ciss_pci_devices[i].product) ||
    264       1.1      he 		    (PCI_VENDOR(reg) == ciss_pci_devices[i].vendor &&
    265       1.1      he 		     PCI_PRODUCT(reg) == ciss_pci_devices[i].product))
    266       1.1      he 		{
    267       1.1      he 			printf(": %s\n", ciss_pci_devices[i].name);
    268       1.1      he 			break;
    269       1.1      he 		}
    270       1.1      he 	}
    271       1.1      he 
    272       1.1      he 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, CISS_BAR);
    273       1.1      he 	if (memtype != (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT) &&
    274       1.1      he 	    memtype != (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT)) {
    275       1.1      he 		printf(": wrong BAR type\n");
    276       1.1      he 		return;
    277       1.1      he 	}
    278       1.1      he 	if (pci_mapreg_map(pa, CISS_BAR, memtype, 0,
    279       1.1      he 	    &sc->sc_iot, &sc->sc_ioh, NULL, &size)) {
    280       1.1      he 		printf(": can't map controller i/o space\n");
    281       1.1      he 		return;
    282       1.1      he 	}
    283       1.1      he 	sc->sc_dmat = pa->pa_dmat;
    284       1.1      he 
    285       1.1      he 	sc->iem = CISS_READYENA;
    286       1.1      he 	reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
    287       1.1      he 	if (PCI_VENDOR(reg) == PCI_VENDOR_COMPAQ &&
    288       1.1      he 	    (PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA5i ||
    289       1.1      he 	     PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA532 ||
    290       1.1      he 	     PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA5312))
    291       1.1      he 		sc->iem = CISS_READYENAB;
    292       1.1      he 
    293       1.1      he 	cfg_bar = bus_space_read_2(sc->sc_iot, sc->sc_ioh, CISS_CFG_BAR);
    294       1.1      he 	sc->cfgoff = bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_CFG_OFF);
    295       1.1      he 	if (cfg_bar != CISS_BAR) {
    296       1.1      he 		if (pci_mapreg_map(pa, cfg_bar, PCI_MAPREG_TYPE_MEM, 0,
    297       1.1      he 		    NULL, &sc->cfg_ioh, NULL, &cfgsz)) {
    298       1.1      he 			printf(": can't map controller config space\n");
    299       1.1      he 			bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
    300       1.1      he 			return;
    301       1.1      he 		}
    302       1.1      he 	} else {
    303       1.1      he 		sc->cfg_ioh = sc->sc_ioh;
    304       1.1      he 		cfgsz = size;
    305       1.1      he 	}
    306       1.1      he 
    307       1.1      he 	if (sc->cfgoff + sizeof(struct ciss_config) > cfgsz) {
    308       1.1      he 		printf(": unfit config space\n");
    309       1.1      he 		bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
    310       1.1      he 		if (cfg_bar != CISS_BAR)
    311       1.1      he 			bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
    312       1.1      he 		return;
    313       1.1      he 	}
    314       1.1      he 
    315       1.1      he 	/* disable interrupts until ready */
    316       1.1      he 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, CISS_IMR,
    317       1.1      he 	    bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IMR) | sc->iem);
    318       1.1      he 
    319       1.1      he 	if (pci_intr_map(pa, &ih)) {
    320       1.1      he 		printf(": can't map interrupt\n");
    321       1.1      he 		bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
    322       1.1      he 		if (cfg_bar != CISS_BAR)
    323       1.1      he 			bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
    324       1.1      he 		return;
    325       1.1      he 	}
    326       1.1      he 	intrstr = pci_intr_string(pa->pa_pc, ih);
    327       1.1      he 	sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ciss_intr, sc);
    328       1.1      he 	if (!sc->sc_ih) {
    329  1.9.22.1     tls 		aprint_error_dev(sc->sc_dev, "can't establish interrupt");
    330       1.1      he 		if (intrstr)
    331       1.9   njoly 			aprint_error(" at %s", intrstr);
    332       1.9   njoly 		aprint_error("\n");
    333       1.1      he 		bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
    334       1.1      he 		if (cfg_bar != CISS_BAR)
    335       1.1      he 			bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
    336       1.1      he 	}
    337       1.1      he 
    338  1.9.22.1     tls 	printf("%s: interrupting at %s\n%s", device_xname(sc->sc_dev), intrstr,
    339  1.9.22.1     tls 	       device_xname(sc->sc_dev));
    340       1.1      he 
    341       1.1      he 	if (ciss_attach(sc)) {
    342       1.1      he 		pci_intr_disestablish(pa->pa_pc, sc->sc_ih);
    343       1.1      he 		sc->sc_ih = NULL;
    344       1.1      he 		bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
    345       1.1      he 		if (cfg_bar != CISS_BAR)
    346       1.1      he 			bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
    347       1.1      he 		return;
    348       1.1      he 	}
    349       1.1      he 
    350       1.1      he 	/* enable interrupts now */
    351       1.1      he 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, CISS_IMR,
    352       1.1      he 	    bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IMR) & ~sc->iem);
    353       1.1      he }
    354