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cmdide.c revision 1.42
      1  1.42  jdolecek /*	$NetBSD: cmdide.c,v 1.42 2017/10/20 21:51:29 jdolecek Exp $	*/
      2   1.1    bouyer 
      3   1.1    bouyer /*
      4   1.1    bouyer  * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
      5   1.1    bouyer  *
      6   1.1    bouyer  * Redistribution and use in source and binary forms, with or without
      7   1.1    bouyer  * modification, are permitted provided that the following conditions
      8   1.1    bouyer  * are met:
      9   1.1    bouyer  * 1. Redistributions of source code must retain the above copyright
     10   1.1    bouyer  *    notice, this list of conditions and the following disclaimer.
     11   1.1    bouyer  * 2. Redistributions in binary form must reproduce the above copyright
     12   1.1    bouyer  *    notice, this list of conditions and the following disclaimer in the
     13   1.1    bouyer  *    documentation and/or other materials provided with the distribution.
     14   1.1    bouyer  *
     15   1.1    bouyer  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16   1.1    bouyer  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     17   1.1    bouyer  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     18  1.18     perry  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     19   1.1    bouyer  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     20   1.1    bouyer  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     21   1.1    bouyer  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     22   1.1    bouyer  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     23   1.1    bouyer  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     24   1.1    bouyer  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     25   1.1    bouyer  */
     26   1.1    bouyer 
     27  1.19     lukem #include <sys/cdefs.h>
     28  1.42  jdolecek __KERNEL_RCSID(0, "$NetBSD: cmdide.c,v 1.42 2017/10/20 21:51:29 jdolecek Exp $");
     29  1.19     lukem 
     30   1.1    bouyer #include <sys/param.h>
     31   1.1    bouyer #include <sys/systm.h>
     32   1.1    bouyer 
     33   1.1    bouyer #include <dev/pci/pcivar.h>
     34   1.1    bouyer #include <dev/pci/pcidevs.h>
     35   1.1    bouyer #include <dev/pci/pciidereg.h>
     36   1.1    bouyer #include <dev/pci/pciidevar.h>
     37   1.1    bouyer #include <dev/pci/pciide_cmd_reg.h>
     38   1.1    bouyer 
     39   1.1    bouyer 
     40  1.28      cube static int  cmdide_match(device_t, cfdata_t, void *);
     41  1.28      cube static void cmdide_attach(device_t, device_t, void *);
     42   1.1    bouyer 
     43  1.28      cube CFATTACH_DECL_NEW(cmdide, sizeof(struct pciide_softc),
     44  1.31  jakllsch     cmdide_match, cmdide_attach, pciide_detach, NULL);
     45   1.1    bouyer 
     46  1.32    dyoung static void cmd_chip_map(struct pciide_softc*, const struct pci_attach_args*);
     47  1.32    dyoung static void cmd0643_9_chip_map(struct pciide_softc*,
     48  1.32    dyoung 			       const struct pci_attach_args*);
     49  1.14   thorpej static void cmd0643_9_setup_channel(struct ata_channel*);
     50  1.32    dyoung static void cmd_channel_map(const struct pci_attach_args *,
     51  1.32    dyoung 			    struct pciide_softc *, int);
     52   1.2   thorpej static int  cmd_pci_intr(void *);
     53  1.14   thorpej static void cmd646_9_irqack(struct ata_channel *);
     54  1.32    dyoung static void cmd680_chip_map(struct pciide_softc*,
     55  1.32    dyoung 			    const struct pci_attach_args*);
     56  1.14   thorpej static void cmd680_setup_channel(struct ata_channel*);
     57  1.32    dyoung static void cmd680_channel_map(const struct pci_attach_args *,
     58  1.32    dyoung 			       struct pciide_softc *, int);
     59   1.1    bouyer 
     60  1.40  jdolecek /* Older CMD64X doesn't have independent channels */
     61   1.2   thorpej static const struct pciide_product_desc pciide_cmd_products[] =  {
     62   1.1    bouyer 	{ PCI_PRODUCT_CMDTECH_640,
     63  1.40  jdolecek 	  IDE_SHARED_CHANNELS,
     64   1.1    bouyer 	  "CMD Technology PCI0640",
     65   1.1    bouyer 	  cmd_chip_map
     66   1.1    bouyer 	},
     67   1.1    bouyer 	{ PCI_PRODUCT_CMDTECH_643,
     68  1.40  jdolecek 	  IDE_SHARED_CHANNELS,
     69   1.1    bouyer 	  "CMD Technology PCI0643",
     70   1.1    bouyer 	  cmd0643_9_chip_map,
     71   1.1    bouyer 	},
     72   1.1    bouyer 	{ PCI_PRODUCT_CMDTECH_646,
     73  1.40  jdolecek 	  IDE_SHARED_CHANNELS,
     74   1.1    bouyer 	  "CMD Technology PCI0646",
     75   1.1    bouyer 	  cmd0643_9_chip_map,
     76   1.1    bouyer 	},
     77   1.1    bouyer 	{ PCI_PRODUCT_CMDTECH_648,
     78  1.40  jdolecek 	  IDE_SHARED_CHANNELS,
     79   1.1    bouyer 	  "CMD Technology PCI0648",
     80   1.1    bouyer 	  cmd0643_9_chip_map,
     81   1.1    bouyer 	},
     82   1.1    bouyer 	{ PCI_PRODUCT_CMDTECH_649,
     83   1.3   mycroft 	  0,
     84   1.1    bouyer 	  "CMD Technology PCI0649",
     85   1.1    bouyer 	  cmd0643_9_chip_map,
     86   1.1    bouyer 	},
     87   1.1    bouyer 	{ PCI_PRODUCT_CMDTECH_680,
     88  1.42  jdolecek 	  0,
     89   1.1    bouyer 	  "Silicon Image 0680",
     90   1.1    bouyer 	  cmd680_chip_map,
     91   1.1    bouyer 	},
     92   1.1    bouyer 	{ 0,
     93   1.1    bouyer 	  0,
     94   1.1    bouyer 	  NULL,
     95   1.1    bouyer 	  NULL
     96   1.1    bouyer 	}
     97   1.1    bouyer };
     98   1.1    bouyer 
     99   1.2   thorpej static int
    100  1.28      cube cmdide_match(device_t parent, cfdata_t match, void *aux)
    101   1.1    bouyer {
    102   1.1    bouyer 	struct pci_attach_args *pa = aux;
    103   1.1    bouyer 
    104   1.1    bouyer 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) {
    105   1.1    bouyer 		if (pciide_lookup_product(pa->pa_id, pciide_cmd_products))
    106   1.1    bouyer 			return (2);
    107   1.1    bouyer 	}
    108   1.1    bouyer 	return (0);
    109   1.1    bouyer }
    110   1.1    bouyer 
    111   1.2   thorpej static void
    112  1.28      cube cmdide_attach(device_t parent, device_t self, void *aux)
    113   1.1    bouyer {
    114   1.1    bouyer 	struct pci_attach_args *pa = aux;
    115  1.28      cube 	struct pciide_softc *sc = device_private(self);
    116  1.28      cube 
    117  1.28      cube 	sc->sc_wdcdev.sc_atac.atac_dev = self;
    118   1.1    bouyer 
    119   1.1    bouyer 	pciide_common_attach(sc, pa,
    120   1.1    bouyer 	    pciide_lookup_product(pa->pa_id, pciide_cmd_products));
    121   1.1    bouyer 
    122   1.1    bouyer }
    123   1.1    bouyer 
    124   1.2   thorpej static void
    125  1.32    dyoung cmd_channel_map(const struct pci_attach_args *pa, struct pciide_softc *sc,
    126   1.2   thorpej     int channel)
    127   1.1    bouyer {
    128   1.1    bouyer 	struct pciide_channel *cp = &sc->pciide_channels[channel];
    129   1.1    bouyer 	u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL);
    130  1.40  jdolecek 	int interface;
    131  1.40  jdolecek 	bool one_channel = ISSET(sc->sc_pp->ide_flags, IDE_SHARED_CHANNELS);
    132   1.1    bouyer 
    133  1.18     perry 	/*
    134   1.1    bouyer 	 * The 0648/0649 can be told to identify as a RAID controller.
    135   1.1    bouyer 	 * In this case, we have to fake interface
    136   1.1    bouyer 	 */
    137   1.1    bouyer 	if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) {
    138   1.1    bouyer 		interface = PCIIDE_INTERFACE_SETTABLE(0) |
    139   1.1    bouyer 		    PCIIDE_INTERFACE_SETTABLE(1);
    140   1.1    bouyer 		if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) &
    141   1.1    bouyer 		    CMD_CONF_DSA1)
    142   1.1    bouyer 			interface |= PCIIDE_INTERFACE_PCI(0) |
    143   1.1    bouyer 			    PCIIDE_INTERFACE_PCI(1);
    144   1.1    bouyer 	} else {
    145   1.1    bouyer 		interface = PCI_INTERFACE(pa->pa_class);
    146   1.1    bouyer 	}
    147   1.1    bouyer 
    148  1.14   thorpej 	sc->wdc_chanarray[channel] = &cp->ata_channel;
    149   1.1    bouyer 	cp->name = PCIIDE_CHANNEL_NAME(channel);
    150  1.14   thorpej 	cp->ata_channel.ch_channel = channel;
    151  1.16   thorpej 	cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
    152   1.1    bouyer 
    153   1.1    bouyer 	if (channel > 0 && one_channel) {
    154  1.14   thorpej 		cp->ata_channel.ch_queue =
    155  1.14   thorpej 		    sc->pciide_channels[0].ata_channel.ch_queue;
    156   1.1    bouyer 	} else {
    157  1.41  jdolecek 		/* XXX */
    158  1.39  jdolecek 		cp->ata_channel.ch_queue = ata_queue_alloc(1);
    159   1.1    bouyer 	}
    160   1.1    bouyer 
    161  1.28      cube 	aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    162  1.40  jdolecek 	    "%s channel %s to %s mode%s\n", cp->name,
    163   1.1    bouyer 	    (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ?
    164   1.1    bouyer 	    "configured" : "wired",
    165   1.1    bouyer 	    (interface & PCIIDE_INTERFACE_PCI(channel)) ?
    166  1.40  jdolecek 	    "native-PCI" : "compatibility",
    167  1.40  jdolecek 	    one_channel ? ", channel non-independant" : "");
    168   1.1    bouyer 
    169   1.1    bouyer 	/*
    170   1.1    bouyer 	 * with a CMD PCI64x, if we get here, the first channel is enabled:
    171   1.1    bouyer 	 * there's no way to disable the first channel without disabling
    172   1.1    bouyer 	 * the whole device
    173   1.1    bouyer 	 */
    174   1.1    bouyer 	if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) {
    175  1.28      cube 		aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    176  1.28      cube 		    "%s channel ignored (disabled)\n", cp->name);
    177  1.14   thorpej 		cp->ata_channel.ch_flags |= ATACH_DISABLED;
    178   1.1    bouyer 		return;
    179   1.1    bouyer 	}
    180   1.1    bouyer 
    181  1.30  jakllsch 	pciide_mapchan(pa, cp, interface, cmd_pci_intr);
    182   1.1    bouyer }
    183   1.1    bouyer 
    184   1.2   thorpej static int
    185   1.2   thorpej cmd_pci_intr(void *arg)
    186   1.1    bouyer {
    187   1.1    bouyer 	struct pciide_softc *sc = arg;
    188   1.1    bouyer 	struct pciide_channel *cp;
    189  1.14   thorpej 	struct ata_channel *wdc_cp;
    190  1.18     perry 	int i, rv, crv;
    191   1.1    bouyer 	u_int32_t priirq, secirq;
    192   1.1    bouyer 
    193   1.1    bouyer 	rv = 0;
    194   1.1    bouyer 	priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF);
    195   1.1    bouyer 	secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23);
    196  1.16   thorpej 	for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
    197   1.1    bouyer 		cp = &sc->pciide_channels[i];
    198  1.14   thorpej 		wdc_cp = &cp->ata_channel;
    199   1.1    bouyer 		/* If a compat channel skip. */
    200   1.1    bouyer 		if (cp->compat)
    201   1.1    bouyer 			continue;
    202   1.1    bouyer 		if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) ||
    203   1.1    bouyer 		    (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) {
    204   1.1    bouyer 			crv = wdcintr(wdc_cp);
    205  1.11    bouyer 			if (crv == 0) {
    206  1.28      cube 				aprint_error("%s:%d: bogus intr\n",
    207  1.28      cube 				    device_xname(
    208  1.28      cube 				      sc->sc_wdcdev.sc_atac.atac_dev), i);
    209  1.11    bouyer 				sc->sc_wdcdev.irqack(wdc_cp);
    210  1.11    bouyer 			} else
    211   1.1    bouyer 				rv = 1;
    212   1.1    bouyer 		}
    213   1.1    bouyer 	}
    214   1.1    bouyer 	return rv;
    215   1.1    bouyer }
    216   1.1    bouyer 
    217   1.2   thorpej static void
    218  1.32    dyoung cmd_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
    219   1.1    bouyer {
    220   1.1    bouyer 	int channel;
    221   1.1    bouyer 
    222   1.1    bouyer 	/*
    223   1.1    bouyer 	 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE
    224   1.5       wiz 	 * and base addresses registers can be disabled at
    225   1.1    bouyer 	 * hardware level. In this case, the device is wired
    226   1.1    bouyer 	 * in compat mode and its first channel is always enabled,
    227   1.1    bouyer 	 * but we can't rely on PCI_COMMAND_IO_ENABLE.
    228   1.1    bouyer 	 * In fact, it seems that the first channel of the CMD PCI0640
    229   1.1    bouyer 	 * can't be disabled.
    230   1.1    bouyer 	 */
    231   1.1    bouyer 
    232   1.1    bouyer #ifdef PCIIDE_CMD064x_DISABLE
    233   1.1    bouyer 	if (pciide_chipen(sc, pa) == 0)
    234   1.1    bouyer 		return;
    235   1.1    bouyer #endif
    236   1.1    bouyer 
    237  1.28      cube 	aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    238  1.28      cube 	    "hardware does not support DMA\n");
    239   1.1    bouyer 	sc->sc_dma_ok = 0;
    240   1.1    bouyer 
    241  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    242  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
    243  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
    244  1.37    bouyer 	sc->sc_wdcdev.wdc_maxdrives = 2;
    245   1.1    bouyer 
    246  1.14   thorpej 	wdc_allocate_regs(&sc->sc_wdcdev);
    247  1.14   thorpej 
    248  1.16   thorpej 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    249  1.16   thorpej 	     channel++) {
    250   1.1    bouyer 		cmd_channel_map(pa, sc, channel);
    251   1.1    bouyer 	}
    252   1.1    bouyer }
    253   1.1    bouyer 
    254   1.2   thorpej static void
    255  1.32    dyoung cmd0643_9_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
    256  1.18     perry {
    257   1.1    bouyer 	int channel;
    258   1.1    bouyer 	pcireg_t rev = PCI_REVISION(pa->pa_class);
    259   1.1    bouyer 
    260   1.1    bouyer 	/*
    261   1.1    bouyer 	 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE
    262   1.5       wiz 	 * and base addresses registers can be disabled at
    263   1.1    bouyer 	 * hardware level. In this case, the device is wired
    264   1.1    bouyer 	 * in compat mode and its first channel is always enabled,
    265   1.1    bouyer 	 * but we can't rely on PCI_COMMAND_IO_ENABLE.
    266   1.1    bouyer 	 * In fact, it seems that the first channel of the CMD PCI0640
    267   1.1    bouyer 	 * can't be disabled.
    268   1.1    bouyer 	 */
    269   1.1    bouyer 
    270   1.1    bouyer #ifdef PCIIDE_CMD064x_DISABLE
    271   1.1    bouyer 	if (pciide_chipen(sc, pa) == 0)
    272   1.1    bouyer 		return;
    273   1.1    bouyer #endif
    274   1.1    bouyer 
    275  1.28      cube 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    276  1.28      cube 	    "bus-master DMA support present");
    277   1.1    bouyer 	pciide_mapreg_dma(sc, pa);
    278  1.27        ad 	aprint_verbose("\n");
    279  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    280   1.1    bouyer 	if (sc->sc_dma_ok) {
    281  1.16   thorpej 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
    282   1.1    bouyer 		switch (sc->sc_pp->ide_product) {
    283   1.1    bouyer 		case PCI_PRODUCT_CMDTECH_649:
    284  1.16   thorpej 			sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
    285  1.16   thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    286   1.1    bouyer 			sc->sc_wdcdev.irqack = cmd646_9_irqack;
    287   1.1    bouyer 			break;
    288   1.1    bouyer 		case PCI_PRODUCT_CMDTECH_648:
    289  1.16   thorpej 			sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
    290  1.16   thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
    291   1.1    bouyer 			sc->sc_wdcdev.irqack = cmd646_9_irqack;
    292   1.1    bouyer 			break;
    293   1.1    bouyer 		case PCI_PRODUCT_CMDTECH_646:
    294   1.1    bouyer 			if (rev >= CMD0646U2_REV) {
    295  1.16   thorpej 				sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
    296  1.16   thorpej 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
    297   1.1    bouyer 			} else if (rev >= CMD0646U_REV) {
    298   1.1    bouyer 			/*
    299   1.1    bouyer 			 * Linux's driver claims that the 646U is broken
    300   1.1    bouyer 			 * with UDMA. Only enable it if we know what we're
    301   1.1    bouyer 			 * doing
    302   1.1    bouyer 			 */
    303   1.1    bouyer #ifdef PCIIDE_CMD0646U_ENABLEUDMA
    304  1.16   thorpej 				sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
    305  1.16   thorpej 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
    306   1.1    bouyer #endif
    307   1.1    bouyer 				/* explicitly disable UDMA */
    308   1.1    bouyer 				pciide_pci_write(sc->sc_pc, sc->sc_tag,
    309   1.1    bouyer 				    CMD_UDMATIM(0), 0);
    310   1.1    bouyer 				pciide_pci_write(sc->sc_pc, sc->sc_tag,
    311   1.1    bouyer 				    CMD_UDMATIM(1), 0);
    312   1.1    bouyer 			}
    313   1.1    bouyer 			sc->sc_wdcdev.irqack = cmd646_9_irqack;
    314   1.1    bouyer 			break;
    315   1.1    bouyer 		default:
    316   1.1    bouyer 			sc->sc_wdcdev.irqack = pciide_irqack;
    317   1.1    bouyer 		}
    318   1.1    bouyer 	}
    319   1.1    bouyer 
    320  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    321  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
    322  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    323  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    324  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_set_modes = cmd0643_9_setup_channel;
    325  1.38  kiyohara 	sc->sc_wdcdev.wdc_maxdrives = 2;
    326   1.1    bouyer 
    327  1.13   thorpej 	ATADEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n",
    328   1.1    bouyer 		pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54),
    329   1.1    bouyer 		pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)),
    330   1.1    bouyer 		DEBUG_PROBE);
    331   1.1    bouyer 
    332  1.14   thorpej 	wdc_allocate_regs(&sc->sc_wdcdev);
    333  1.14   thorpej 
    334  1.16   thorpej 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    335  1.16   thorpej 	     channel++)
    336   1.1    bouyer 		cmd_channel_map(pa, sc, channel);
    337   1.4    simonb 
    338   1.1    bouyer 	/*
    339   1.1    bouyer 	 * note - this also makes sure we clear the irq disable and reset
    340   1.1    bouyer 	 * bits
    341   1.1    bouyer 	 */
    342   1.1    bouyer 	pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE);
    343  1.13   thorpej 	ATADEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n",
    344   1.1    bouyer 	    pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54),
    345   1.1    bouyer 	    pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)),
    346   1.1    bouyer 	    DEBUG_PROBE);
    347   1.1    bouyer }
    348   1.1    bouyer 
    349   1.2   thorpej static void
    350  1.14   thorpej cmd0643_9_setup_channel(struct ata_channel *chp)
    351   1.1    bouyer {
    352   1.1    bouyer 	struct ata_drive_datas *drvp;
    353   1.1    bouyer 	u_int8_t tim;
    354   1.1    bouyer 	u_int32_t idedma_ctl, udma_reg;
    355  1.17   thorpej 	int drive, s;
    356  1.15   thorpej 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
    357  1.15   thorpej 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
    358   1.1    bouyer 
    359   1.1    bouyer 	idedma_ctl = 0;
    360   1.1    bouyer 	/* setup DMA if needed */
    361   1.1    bouyer 	pciide_channel_dma_setup(cp);
    362   1.1    bouyer 
    363   1.1    bouyer 	for (drive = 0; drive < 2; drive++) {
    364   1.1    bouyer 		drvp = &chp->ch_drive[drive];
    365   1.1    bouyer 		/* If no drive, skip */
    366  1.37    bouyer 		if (drvp->drive_type == ATA_DRIVET_NONE)
    367   1.1    bouyer 			continue;
    368   1.1    bouyer 		/* add timing values, setup DMA if needed */
    369   1.1    bouyer 		tim = cmd0643_9_data_tim_pio[drvp->PIO_mode];
    370  1.37    bouyer 		if (drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) {
    371  1.37    bouyer 			if (drvp->drive_flags & ATA_DRIVE_UDMA) {
    372   1.1    bouyer 				/* UltraDMA on a 646U2, 0648 or 0649 */
    373  1.17   thorpej 				s = splbio();
    374  1.37    bouyer 				drvp->drive_flags &= ~ATA_DRIVE_DMA;
    375  1.17   thorpej 				splx(s);
    376   1.1    bouyer 				udma_reg = pciide_pci_read(sc->sc_pc,
    377  1.10   thorpej 				    sc->sc_tag, CMD_UDMATIM(chp->ch_channel));
    378   1.1    bouyer 				if (drvp->UDMA_mode > 2 &&
    379   1.1    bouyer 				    (pciide_pci_read(sc->sc_pc, sc->sc_tag,
    380   1.1    bouyer 				    CMD_BICSR) &
    381  1.10   thorpej 				    CMD_BICSR_80(chp->ch_channel)) == 0)
    382   1.1    bouyer 					drvp->UDMA_mode = 2;
    383   1.1    bouyer 				if (drvp->UDMA_mode > 2)
    384   1.1    bouyer 					udma_reg &= ~CMD_UDMATIM_UDMA33(drive);
    385  1.18     perry 				else if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 2)
    386   1.1    bouyer 					udma_reg |= CMD_UDMATIM_UDMA33(drive);
    387   1.1    bouyer 				udma_reg |= CMD_UDMATIM_UDMA(drive);
    388   1.1    bouyer 				udma_reg &= ~(CMD_UDMATIM_TIM_MASK <<
    389   1.1    bouyer 				    CMD_UDMATIM_TIM_OFF(drive));
    390   1.1    bouyer 				udma_reg |=
    391   1.1    bouyer 				    (cmd0646_9_tim_udma[drvp->UDMA_mode] <<
    392   1.1    bouyer 				    CMD_UDMATIM_TIM_OFF(drive));
    393   1.1    bouyer 				pciide_pci_write(sc->sc_pc, sc->sc_tag,
    394  1.10   thorpej 				    CMD_UDMATIM(chp->ch_channel), udma_reg);
    395   1.1    bouyer 			} else {
    396   1.1    bouyer 				/*
    397   1.1    bouyer 				 * use Multiword DMA.
    398   1.1    bouyer 				 * Timings will be used for both PIO and DMA,
    399   1.1    bouyer 				 * so adjust DMA mode if needed
    400   1.1    bouyer 				 * if we have a 0646U2/8/9, turn off UDMA
    401   1.1    bouyer 				 */
    402  1.16   thorpej 				if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
    403   1.1    bouyer 					udma_reg = pciide_pci_read(sc->sc_pc,
    404   1.1    bouyer 					    sc->sc_tag,
    405  1.10   thorpej 					    CMD_UDMATIM(chp->ch_channel));
    406   1.1    bouyer 					udma_reg &= ~CMD_UDMATIM_UDMA(drive);
    407   1.1    bouyer 					pciide_pci_write(sc->sc_pc, sc->sc_tag,
    408  1.10   thorpej 					    CMD_UDMATIM(chp->ch_channel),
    409   1.1    bouyer 					    udma_reg);
    410   1.1    bouyer 				}
    411   1.1    bouyer 				if (drvp->PIO_mode >= 3 &&
    412   1.1    bouyer 				    (drvp->DMA_mode + 2) > drvp->PIO_mode) {
    413   1.1    bouyer 					drvp->DMA_mode = drvp->PIO_mode - 2;
    414   1.1    bouyer 				}
    415   1.1    bouyer 				tim = cmd0643_9_data_tim_dma[drvp->DMA_mode];
    416   1.1    bouyer 			}
    417   1.1    bouyer 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    418   1.1    bouyer 		}
    419   1.1    bouyer 		pciide_pci_write(sc->sc_pc, sc->sc_tag,
    420  1.10   thorpej 		    CMD_DATA_TIM(chp->ch_channel, drive), tim);
    421   1.1    bouyer 	}
    422   1.1    bouyer 	if (idedma_ctl != 0) {
    423   1.1    bouyer 		/* Add software bits in status register */
    424   1.6      fvdl 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
    425   1.1    bouyer 		    idedma_ctl);
    426   1.1    bouyer 	}
    427   1.1    bouyer }
    428   1.1    bouyer 
    429   1.2   thorpej static void
    430  1.14   thorpej cmd646_9_irqack(struct ata_channel *chp)
    431   1.1    bouyer {
    432   1.1    bouyer 	u_int32_t priirq, secirq;
    433  1.15   thorpej 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
    434   1.1    bouyer 
    435  1.10   thorpej 	if (chp->ch_channel == 0) {
    436   1.1    bouyer 		priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF);
    437   1.1    bouyer 		pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq);
    438   1.1    bouyer 	} else {
    439   1.1    bouyer 		secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23);
    440   1.1    bouyer 		pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq);
    441   1.1    bouyer 	}
    442   1.1    bouyer 	pciide_irqack(chp);
    443   1.1    bouyer }
    444   1.1    bouyer 
    445   1.2   thorpej static void
    446  1.32    dyoung cmd680_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
    447  1.18     perry {
    448   1.1    bouyer 	int channel;
    449   1.1    bouyer 
    450   1.1    bouyer 	if (pciide_chipen(sc, pa) == 0)
    451   1.1    bouyer 		return;
    452   1.1    bouyer 
    453  1.28      cube 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    454  1.28      cube 	    "bus-master DMA support present");
    455   1.1    bouyer 	pciide_mapreg_dma(sc, pa);
    456  1.27        ad 	aprint_verbose("\n");
    457  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    458   1.1    bouyer 	if (sc->sc_dma_ok) {
    459  1.16   thorpej 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
    460  1.16   thorpej 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
    461  1.16   thorpej 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    462   1.1    bouyer 		sc->sc_wdcdev.irqack = pciide_irqack;
    463   1.1    bouyer 	}
    464   1.1    bouyer 
    465  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    466  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
    467  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    468  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    469  1.16   thorpej 	sc->sc_wdcdev.sc_atac.atac_set_modes = cmd680_setup_channel;
    470  1.38  kiyohara 	sc->sc_wdcdev.wdc_maxdrives = 2;
    471   1.1    bouyer 
    472   1.1    bouyer 	pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00);
    473   1.1    bouyer 	pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00);
    474   1.1    bouyer 	pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a,
    475   1.1    bouyer 	    pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01);
    476  1.14   thorpej 
    477  1.14   thorpej 	wdc_allocate_regs(&sc->sc_wdcdev);
    478  1.14   thorpej 
    479  1.16   thorpej 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    480  1.16   thorpej 	     channel++)
    481   1.1    bouyer 		cmd680_channel_map(pa, sc, channel);
    482   1.1    bouyer }
    483   1.1    bouyer 
    484   1.2   thorpej static void
    485  1.32    dyoung cmd680_channel_map(const struct pci_attach_args *pa, struct pciide_softc *sc,
    486   1.2   thorpej     int channel)
    487   1.1    bouyer {
    488   1.1    bouyer 	struct pciide_channel *cp = &sc->pciide_channels[channel];
    489   1.1    bouyer 	int interface, i, reg;
    490   1.1    bouyer 	static const u_int8_t init_val[] =
    491   1.1    bouyer 	    {             0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32,
    492   1.1    bouyer 	      0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 };
    493   1.1    bouyer 
    494   1.1    bouyer 	if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) {
    495   1.1    bouyer 		interface = PCIIDE_INTERFACE_SETTABLE(0) |
    496   1.1    bouyer 		    PCIIDE_INTERFACE_SETTABLE(1);
    497   1.1    bouyer 		interface |= PCIIDE_INTERFACE_PCI(0) |
    498   1.1    bouyer 		    PCIIDE_INTERFACE_PCI(1);
    499   1.1    bouyer 	} else {
    500   1.1    bouyer 		interface = PCI_INTERFACE(pa->pa_class);
    501   1.1    bouyer 	}
    502   1.1    bouyer 
    503  1.14   thorpej 	sc->wdc_chanarray[channel] = &cp->ata_channel;
    504   1.1    bouyer 	cp->name = PCIIDE_CHANNEL_NAME(channel);
    505  1.14   thorpej 	cp->ata_channel.ch_channel = channel;
    506  1.16   thorpej 	cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
    507   1.1    bouyer 
    508   1.1    bouyer 	/* XXX */
    509   1.1    bouyer 	reg = 0xa2 + channel * 16;
    510   1.1    bouyer 	for (i = 0; i < sizeof(init_val); i++)
    511   1.1    bouyer 		pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]);
    512   1.1    bouyer 
    513  1.28      cube 	aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
    514  1.28      cube 	    "%s channel %s to %s mode\n", cp->name,
    515   1.1    bouyer 	    (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ?
    516   1.1    bouyer 	    "configured" : "wired",
    517   1.1    bouyer 	    (interface & PCIIDE_INTERFACE_PCI(channel)) ?
    518   1.1    bouyer 	    "native-PCI" : "compatibility");
    519   1.1    bouyer 
    520  1.30  jakllsch 	pciide_mapchan(pa, cp, interface, pciide_pci_intr);
    521   1.1    bouyer }
    522   1.1    bouyer 
    523   1.2   thorpej static void
    524  1.14   thorpej cmd680_setup_channel(struct ata_channel *chp)
    525   1.1    bouyer {
    526   1.1    bouyer 	struct ata_drive_datas *drvp;
    527   1.1    bouyer 	u_int8_t mode, off, scsc;
    528   1.1    bouyer 	u_int16_t val;
    529   1.1    bouyer 	u_int32_t idedma_ctl;
    530  1.17   thorpej 	int drive, s;
    531  1.15   thorpej 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
    532  1.15   thorpej 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
    533   1.1    bouyer 	pci_chipset_tag_t pc = sc->sc_pc;
    534   1.1    bouyer 	pcitag_t pa = sc->sc_tag;
    535   1.1    bouyer 	static const u_int8_t udma2_tbl[] =
    536   1.1    bouyer 	    { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 };
    537   1.1    bouyer 	static const u_int8_t udma_tbl[] =
    538   1.1    bouyer 	    { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 };
    539   1.1    bouyer 	static const u_int16_t dma_tbl[] =
    540   1.1    bouyer 	    { 0x2208, 0x10c2, 0x10c1 };
    541   1.1    bouyer 	static const u_int16_t pio_tbl[] =
    542   1.1    bouyer 	    { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
    543   1.1    bouyer 
    544   1.1    bouyer 	idedma_ctl = 0;
    545   1.1    bouyer 	pciide_channel_dma_setup(cp);
    546  1.10   thorpej 	mode = pciide_pci_read(pc, pa, 0x80 + chp->ch_channel * 4);
    547   1.1    bouyer 
    548   1.1    bouyer 	for (drive = 0; drive < 2; drive++) {
    549   1.1    bouyer 		drvp = &chp->ch_drive[drive];
    550   1.1    bouyer 		/* If no drive, skip */
    551  1.37    bouyer 		if (drvp->drive_type == ATA_DRIVET_NONE)
    552   1.1    bouyer 			continue;
    553   1.1    bouyer 		mode &= ~(0x03 << (drive * 4));
    554  1.37    bouyer 		if (drvp->drive_flags & ATA_DRIVE_UDMA) {
    555  1.17   thorpej 			s = splbio();
    556  1.37    bouyer 			drvp->drive_flags &= ~ATA_DRIVE_DMA;
    557  1.17   thorpej 			splx(s);
    558  1.10   thorpej 			off = 0xa0 + chp->ch_channel * 16;
    559   1.1    bouyer 			if (drvp->UDMA_mode > 2 &&
    560   1.1    bouyer 			    (pciide_pci_read(pc, pa, off) & 0x01) == 0)
    561   1.1    bouyer 				drvp->UDMA_mode = 2;
    562   1.1    bouyer 			scsc = pciide_pci_read(pc, pa, 0x8a);
    563   1.1    bouyer 			if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) {
    564   1.1    bouyer 				pciide_pci_write(pc, pa, 0x8a, scsc | 0x01);
    565   1.1    bouyer 				scsc = pciide_pci_read(pc, pa, 0x8a);
    566   1.1    bouyer 				if ((scsc & 0x30) == 0)
    567   1.1    bouyer 					drvp->UDMA_mode = 5;
    568   1.1    bouyer 			}
    569   1.1    bouyer 			mode |= 0x03 << (drive * 4);
    570  1.10   thorpej 			off = 0xac + chp->ch_channel * 16 + drive * 2;
    571   1.1    bouyer 			val = pciide_pci_read(pc, pa, off) & ~0x3f;
    572   1.1    bouyer 			if (scsc & 0x30)
    573   1.1    bouyer 				val |= udma2_tbl[drvp->UDMA_mode];
    574   1.1    bouyer 			else
    575   1.1    bouyer 				val |= udma_tbl[drvp->UDMA_mode];
    576   1.1    bouyer 			pciide_pci_write(pc, pa, off, val);
    577   1.1    bouyer 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    578  1.37    bouyer 		} else if (drvp->drive_flags & ATA_DRIVE_DMA) {
    579   1.1    bouyer 			mode |= 0x02 << (drive * 4);
    580  1.10   thorpej 			off = 0xa8 + chp->ch_channel * 16 + drive * 2;
    581   1.1    bouyer 			val = dma_tbl[drvp->DMA_mode];
    582   1.1    bouyer 			pciide_pci_write(pc, pa, off, val & 0xff);
    583  1.20  christos 			pciide_pci_write(pc, pa, off+1, val >> 8);
    584   1.1    bouyer 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    585   1.1    bouyer 		} else {
    586   1.1    bouyer 			mode |= 0x01 << (drive * 4);
    587  1.10   thorpej 			off = 0xa4 + chp->ch_channel * 16 + drive * 2;
    588   1.1    bouyer 			val = pio_tbl[drvp->PIO_mode];
    589   1.1    bouyer 			pciide_pci_write(pc, pa, off, val & 0xff);
    590  1.20  christos 			pciide_pci_write(pc, pa, off+1, val >> 8);
    591   1.1    bouyer 		}
    592   1.1    bouyer 	}
    593   1.1    bouyer 
    594  1.10   thorpej 	pciide_pci_write(pc, pa, 0x80 + chp->ch_channel * 4, mode);
    595   1.1    bouyer 	if (idedma_ctl != 0) {
    596   1.1    bouyer 		/* Add software bits in status register */
    597   1.6      fvdl 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
    598   1.1    bouyer 		    idedma_ctl);
    599   1.1    bouyer 	}
    600   1.1    bouyer }
    601