cmdide.c revision 1.1
1 /* $NetBSD: cmdide.c,v 1.1 2003/10/08 11:51:59 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_cmd_reg.h> 44 #include <dev/pci/pciide_sii3112_reg.h> 45 46 47 int cmdide_match __P((struct device *, struct cfdata *, void *)); 48 void cmdide_attach __P((struct device *, struct device *, void *)); 49 50 CFATTACH_DECL(cmdide, sizeof(struct pciide_softc), 51 cmdide_match, cmdide_attach, NULL, NULL); 52 53 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 54 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 55 void cmd0643_9_setup_channel __P((struct channel_softc*)); 56 void cmd_channel_map __P((struct pci_attach_args *, 57 struct pciide_softc *, int)); 58 int cmd_pci_intr __P((void *)); 59 void cmd646_9_irqack __P((struct channel_softc *)); 60 void cmd680_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 61 void cmd680_setup_channel __P((struct channel_softc*)); 62 void cmd680_channel_map __P((struct pci_attach_args *, 63 struct pciide_softc *, int)); 64 65 void cmd3112_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 66 void cmd3112_setup_channel __P((struct channel_softc*)); 67 68 const struct pciide_product_desc pciide_cmd_products[] = { 69 { PCI_PRODUCT_CMDTECH_640, 70 0, 71 "CMD Technology PCI0640", 72 cmd_chip_map 73 }, 74 { PCI_PRODUCT_CMDTECH_643, 75 0, 76 "CMD Technology PCI0643", 77 cmd0643_9_chip_map, 78 }, 79 { PCI_PRODUCT_CMDTECH_646, 80 0, 81 "CMD Technology PCI0646", 82 cmd0643_9_chip_map, 83 }, 84 { PCI_PRODUCT_CMDTECH_648, 85 IDE_PCI_CLASS_OVERRIDE, 86 "CMD Technology PCI0648", 87 cmd0643_9_chip_map, 88 }, 89 { PCI_PRODUCT_CMDTECH_649, 90 IDE_PCI_CLASS_OVERRIDE, 91 "CMD Technology PCI0649", 92 cmd0643_9_chip_map, 93 }, 94 { PCI_PRODUCT_CMDTECH_680, 95 IDE_PCI_CLASS_OVERRIDE, 96 "Silicon Image 0680", 97 cmd680_chip_map, 98 }, 99 { PCI_PRODUCT_CMDTECH_3112, 100 IDE_PCI_CLASS_OVERRIDE, 101 "Silicon Image SATALink 3112", 102 cmd3112_chip_map, 103 }, 104 { 0, 105 0, 106 NULL, 107 NULL 108 } 109 }; 110 111 int 112 cmdide_match(parent, match, aux) 113 struct device *parent; 114 struct cfdata *match; 115 void *aux; 116 { 117 struct pci_attach_args *pa = aux; 118 119 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 120 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 121 return (2); 122 } 123 return (0); 124 } 125 126 void 127 cmdide_attach(parent, self, aux) 128 struct device *parent, *self; 129 void *aux; 130 { 131 struct pci_attach_args *pa = aux; 132 struct pciide_softc *sc = (struct pciide_softc *)self; 133 134 pciide_common_attach(sc, pa, 135 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 136 137 } 138 139 140 void 141 cmd_channel_map(pa, sc, channel) 142 struct pci_attach_args *pa; 143 struct pciide_softc *sc; 144 int channel; 145 { 146 struct pciide_channel *cp = &sc->pciide_channels[channel]; 147 bus_size_t cmdsize, ctlsize; 148 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 149 int interface, one_channel; 150 151 /* 152 * The 0648/0649 can be told to identify as a RAID controller. 153 * In this case, we have to fake interface 154 */ 155 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 156 interface = PCIIDE_INTERFACE_SETTABLE(0) | 157 PCIIDE_INTERFACE_SETTABLE(1); 158 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 159 CMD_CONF_DSA1) 160 interface |= PCIIDE_INTERFACE_PCI(0) | 161 PCIIDE_INTERFACE_PCI(1); 162 } else { 163 interface = PCI_INTERFACE(pa->pa_class); 164 } 165 166 sc->wdc_chanarray[channel] = &cp->wdc_channel; 167 cp->name = PCIIDE_CHANNEL_NAME(channel); 168 cp->wdc_channel.channel = channel; 169 cp->wdc_channel.wdc = &sc->sc_wdcdev; 170 171 /* 172 * Older CMD64X doesn't have independant channels 173 */ 174 switch (sc->sc_pp->ide_product) { 175 case PCI_PRODUCT_CMDTECH_649: 176 one_channel = 0; 177 break; 178 default: 179 one_channel = 1; 180 break; 181 } 182 183 if (channel > 0 && one_channel) { 184 cp->wdc_channel.ch_queue = 185 sc->pciide_channels[0].wdc_channel.ch_queue; 186 } else { 187 cp->wdc_channel.ch_queue = 188 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 189 } 190 if (cp->wdc_channel.ch_queue == NULL) { 191 aprint_error("%s %s channel: " 192 "can't allocate memory for command queue", 193 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 194 return; 195 } 196 197 aprint_normal("%s: %s channel %s to %s mode\n", 198 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 199 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 200 "configured" : "wired", 201 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 202 "native-PCI" : "compatibility"); 203 204 /* 205 * with a CMD PCI64x, if we get here, the first channel is enabled: 206 * there's no way to disable the first channel without disabling 207 * the whole device 208 */ 209 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 210 aprint_normal("%s: %s channel ignored (disabled)\n", 211 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 212 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 213 return; 214 } 215 216 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 217 } 218 219 int 220 cmd_pci_intr(arg) 221 void *arg; 222 { 223 struct pciide_softc *sc = arg; 224 struct pciide_channel *cp; 225 struct channel_softc *wdc_cp; 226 int i, rv, crv; 227 u_int32_t priirq, secirq; 228 229 rv = 0; 230 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 231 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 232 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 233 cp = &sc->pciide_channels[i]; 234 wdc_cp = &cp->wdc_channel; 235 /* If a compat channel skip. */ 236 if (cp->compat) 237 continue; 238 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 239 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 240 crv = wdcintr(wdc_cp); 241 if (crv == 0) 242 printf("%s:%d: bogus intr\n", 243 sc->sc_wdcdev.sc_dev.dv_xname, i); 244 else 245 rv = 1; 246 } 247 } 248 return rv; 249 } 250 251 void 252 cmd_chip_map(sc, pa) 253 struct pciide_softc *sc; 254 struct pci_attach_args *pa; 255 { 256 int channel; 257 258 /* 259 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 260 * and base adresses registers can be disabled at 261 * hardware level. In this case, the device is wired 262 * in compat mode and its first channel is always enabled, 263 * but we can't rely on PCI_COMMAND_IO_ENABLE. 264 * In fact, it seems that the first channel of the CMD PCI0640 265 * can't be disabled. 266 */ 267 268 #ifdef PCIIDE_CMD064x_DISABLE 269 if (pciide_chipen(sc, pa) == 0) 270 return; 271 #endif 272 273 aprint_normal("%s: hardware does not support DMA\n", 274 sc->sc_wdcdev.sc_dev.dv_xname); 275 sc->sc_dma_ok = 0; 276 277 sc->sc_wdcdev.channels = sc->wdc_chanarray; 278 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 279 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 280 281 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 282 cmd_channel_map(pa, sc, channel); 283 } 284 } 285 286 void 287 cmd0643_9_chip_map(sc, pa) 288 struct pciide_softc *sc; 289 struct pci_attach_args *pa; 290 { 291 struct pciide_channel *cp; 292 int channel; 293 pcireg_t rev = PCI_REVISION(pa->pa_class); 294 295 /* 296 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 297 * and base adresses registers can be disabled at 298 * hardware level. In this case, the device is wired 299 * in compat mode and its first channel is always enabled, 300 * but we can't rely on PCI_COMMAND_IO_ENABLE. 301 * In fact, it seems that the first channel of the CMD PCI0640 302 * can't be disabled. 303 */ 304 305 #ifdef PCIIDE_CMD064x_DISABLE 306 if (pciide_chipen(sc, pa) == 0) 307 return; 308 #endif 309 310 aprint_normal("%s: bus-master DMA support present", 311 sc->sc_wdcdev.sc_dev.dv_xname); 312 pciide_mapreg_dma(sc, pa); 313 aprint_normal("\n"); 314 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 315 WDC_CAPABILITY_MODE; 316 if (sc->sc_dma_ok) { 317 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 318 switch (sc->sc_pp->ide_product) { 319 case PCI_PRODUCT_CMDTECH_649: 320 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 321 sc->sc_wdcdev.UDMA_cap = 5; 322 sc->sc_wdcdev.irqack = cmd646_9_irqack; 323 break; 324 case PCI_PRODUCT_CMDTECH_648: 325 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 326 sc->sc_wdcdev.UDMA_cap = 4; 327 sc->sc_wdcdev.irqack = cmd646_9_irqack; 328 break; 329 case PCI_PRODUCT_CMDTECH_646: 330 if (rev >= CMD0646U2_REV) { 331 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 332 sc->sc_wdcdev.UDMA_cap = 2; 333 } else if (rev >= CMD0646U_REV) { 334 /* 335 * Linux's driver claims that the 646U is broken 336 * with UDMA. Only enable it if we know what we're 337 * doing 338 */ 339 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 340 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 341 sc->sc_wdcdev.UDMA_cap = 2; 342 #endif 343 /* explicitly disable UDMA */ 344 pciide_pci_write(sc->sc_pc, sc->sc_tag, 345 CMD_UDMATIM(0), 0); 346 pciide_pci_write(sc->sc_pc, sc->sc_tag, 347 CMD_UDMATIM(1), 0); 348 } 349 sc->sc_wdcdev.irqack = cmd646_9_irqack; 350 break; 351 default: 352 sc->sc_wdcdev.irqack = pciide_irqack; 353 } 354 } 355 356 sc->sc_wdcdev.channels = sc->wdc_chanarray; 357 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 358 sc->sc_wdcdev.PIO_cap = 4; 359 sc->sc_wdcdev.DMA_cap = 2; 360 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 361 362 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 363 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 364 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 365 DEBUG_PROBE); 366 367 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 368 cp = &sc->pciide_channels[channel]; 369 cmd_channel_map(pa, sc, channel); 370 } 371 /* 372 * note - this also makes sure we clear the irq disable and reset 373 * bits 374 */ 375 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 376 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 377 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 378 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 379 DEBUG_PROBE); 380 } 381 382 void 383 cmd0643_9_setup_channel(chp) 384 struct channel_softc *chp; 385 { 386 struct ata_drive_datas *drvp; 387 u_int8_t tim; 388 u_int32_t idedma_ctl, udma_reg; 389 int drive; 390 struct pciide_channel *cp = (struct pciide_channel*)chp; 391 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 392 393 idedma_ctl = 0; 394 /* setup DMA if needed */ 395 pciide_channel_dma_setup(cp); 396 397 for (drive = 0; drive < 2; drive++) { 398 drvp = &chp->ch_drive[drive]; 399 /* If no drive, skip */ 400 if ((drvp->drive_flags & DRIVE) == 0) 401 continue; 402 /* add timing values, setup DMA if needed */ 403 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 404 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 405 if (drvp->drive_flags & DRIVE_UDMA) { 406 /* UltraDMA on a 646U2, 0648 or 0649 */ 407 drvp->drive_flags &= ~DRIVE_DMA; 408 udma_reg = pciide_pci_read(sc->sc_pc, 409 sc->sc_tag, CMD_UDMATIM(chp->channel)); 410 if (drvp->UDMA_mode > 2 && 411 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 412 CMD_BICSR) & 413 CMD_BICSR_80(chp->channel)) == 0) 414 drvp->UDMA_mode = 2; 415 if (drvp->UDMA_mode > 2) 416 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 417 else if (sc->sc_wdcdev.UDMA_cap > 2) 418 udma_reg |= CMD_UDMATIM_UDMA33(drive); 419 udma_reg |= CMD_UDMATIM_UDMA(drive); 420 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 421 CMD_UDMATIM_TIM_OFF(drive)); 422 udma_reg |= 423 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 424 CMD_UDMATIM_TIM_OFF(drive)); 425 pciide_pci_write(sc->sc_pc, sc->sc_tag, 426 CMD_UDMATIM(chp->channel), udma_reg); 427 } else { 428 /* 429 * use Multiword DMA. 430 * Timings will be used for both PIO and DMA, 431 * so adjust DMA mode if needed 432 * if we have a 0646U2/8/9, turn off UDMA 433 */ 434 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 435 udma_reg = pciide_pci_read(sc->sc_pc, 436 sc->sc_tag, 437 CMD_UDMATIM(chp->channel)); 438 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 439 pciide_pci_write(sc->sc_pc, sc->sc_tag, 440 CMD_UDMATIM(chp->channel), 441 udma_reg); 442 } 443 if (drvp->PIO_mode >= 3 && 444 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 445 drvp->DMA_mode = drvp->PIO_mode - 2; 446 } 447 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 448 } 449 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 450 } 451 pciide_pci_write(sc->sc_pc, sc->sc_tag, 452 CMD_DATA_TIM(chp->channel, drive), tim); 453 } 454 if (idedma_ctl != 0) { 455 /* Add software bits in status register */ 456 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 457 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 458 idedma_ctl); 459 } 460 } 461 462 void 463 cmd646_9_irqack(chp) 464 struct channel_softc *chp; 465 { 466 u_int32_t priirq, secirq; 467 struct pciide_channel *cp = (struct pciide_channel*)chp; 468 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 469 470 if (chp->channel == 0) { 471 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 472 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 473 } else { 474 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 475 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 476 } 477 pciide_irqack(chp); 478 } 479 480 void 481 cmd680_chip_map(sc, pa) 482 struct pciide_softc *sc; 483 struct pci_attach_args *pa; 484 { 485 struct pciide_channel *cp; 486 int channel; 487 488 if (pciide_chipen(sc, pa) == 0) 489 return; 490 491 aprint_normal("%s: bus-master DMA support present", 492 sc->sc_wdcdev.sc_dev.dv_xname); 493 pciide_mapreg_dma(sc, pa); 494 aprint_normal("\n"); 495 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 496 WDC_CAPABILITY_MODE; 497 if (sc->sc_dma_ok) { 498 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 499 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 500 sc->sc_wdcdev.UDMA_cap = 6; 501 sc->sc_wdcdev.irqack = pciide_irqack; 502 } 503 504 sc->sc_wdcdev.channels = sc->wdc_chanarray; 505 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 506 sc->sc_wdcdev.PIO_cap = 4; 507 sc->sc_wdcdev.DMA_cap = 2; 508 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 509 510 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 511 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 512 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 513 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 514 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 515 cp = &sc->pciide_channels[channel]; 516 cmd680_channel_map(pa, sc, channel); 517 } 518 } 519 520 void 521 cmd680_channel_map(pa, sc, channel) 522 struct pci_attach_args *pa; 523 struct pciide_softc *sc; 524 int channel; 525 { 526 struct pciide_channel *cp = &sc->pciide_channels[channel]; 527 bus_size_t cmdsize, ctlsize; 528 int interface, i, reg; 529 static const u_int8_t init_val[] = 530 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 531 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 532 533 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 534 interface = PCIIDE_INTERFACE_SETTABLE(0) | 535 PCIIDE_INTERFACE_SETTABLE(1); 536 interface |= PCIIDE_INTERFACE_PCI(0) | 537 PCIIDE_INTERFACE_PCI(1); 538 } else { 539 interface = PCI_INTERFACE(pa->pa_class); 540 } 541 542 sc->wdc_chanarray[channel] = &cp->wdc_channel; 543 cp->name = PCIIDE_CHANNEL_NAME(channel); 544 cp->wdc_channel.channel = channel; 545 cp->wdc_channel.wdc = &sc->sc_wdcdev; 546 547 cp->wdc_channel.ch_queue = 548 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 549 if (cp->wdc_channel.ch_queue == NULL) { 550 aprint_error("%s %s channel: " 551 "can't allocate memory for command queue", 552 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 553 return; 554 } 555 556 /* XXX */ 557 reg = 0xa2 + channel * 16; 558 for (i = 0; i < sizeof(init_val); i++) 559 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 560 561 aprint_normal("%s: %s channel %s to %s mode\n", 562 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 563 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 564 "configured" : "wired", 565 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 566 "native-PCI" : "compatibility"); 567 568 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 569 } 570 571 void 572 cmd680_setup_channel(chp) 573 struct channel_softc *chp; 574 { 575 struct ata_drive_datas *drvp; 576 u_int8_t mode, off, scsc; 577 u_int16_t val; 578 u_int32_t idedma_ctl; 579 int drive; 580 struct pciide_channel *cp = (struct pciide_channel*)chp; 581 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 582 pci_chipset_tag_t pc = sc->sc_pc; 583 pcitag_t pa = sc->sc_tag; 584 static const u_int8_t udma2_tbl[] = 585 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 586 static const u_int8_t udma_tbl[] = 587 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 588 static const u_int16_t dma_tbl[] = 589 { 0x2208, 0x10c2, 0x10c1 }; 590 static const u_int16_t pio_tbl[] = 591 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 592 593 idedma_ctl = 0; 594 pciide_channel_dma_setup(cp); 595 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 596 597 for (drive = 0; drive < 2; drive++) { 598 drvp = &chp->ch_drive[drive]; 599 /* If no drive, skip */ 600 if ((drvp->drive_flags & DRIVE) == 0) 601 continue; 602 mode &= ~(0x03 << (drive * 4)); 603 if (drvp->drive_flags & DRIVE_UDMA) { 604 drvp->drive_flags &= ~DRIVE_DMA; 605 off = 0xa0 + chp->channel * 16; 606 if (drvp->UDMA_mode > 2 && 607 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 608 drvp->UDMA_mode = 2; 609 scsc = pciide_pci_read(pc, pa, 0x8a); 610 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 611 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 612 scsc = pciide_pci_read(pc, pa, 0x8a); 613 if ((scsc & 0x30) == 0) 614 drvp->UDMA_mode = 5; 615 } 616 mode |= 0x03 << (drive * 4); 617 off = 0xac + chp->channel * 16 + drive * 2; 618 val = pciide_pci_read(pc, pa, off) & ~0x3f; 619 if (scsc & 0x30) 620 val |= udma2_tbl[drvp->UDMA_mode]; 621 else 622 val |= udma_tbl[drvp->UDMA_mode]; 623 pciide_pci_write(pc, pa, off, val); 624 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 625 } else if (drvp->drive_flags & DRIVE_DMA) { 626 mode |= 0x02 << (drive * 4); 627 off = 0xa8 + chp->channel * 16 + drive * 2; 628 val = dma_tbl[drvp->DMA_mode]; 629 pciide_pci_write(pc, pa, off, val & 0xff); 630 pciide_pci_write(pc, pa, off, val >> 8); 631 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 632 } else { 633 mode |= 0x01 << (drive * 4); 634 off = 0xa4 + chp->channel * 16 + drive * 2; 635 val = pio_tbl[drvp->PIO_mode]; 636 pciide_pci_write(pc, pa, off, val & 0xff); 637 pciide_pci_write(pc, pa, off, val >> 8); 638 } 639 } 640 641 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 642 if (idedma_ctl != 0) { 643 /* Add software bits in status register */ 644 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 645 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 646 idedma_ctl); 647 } 648 } 649 650 void 651 cmd3112_chip_map(sc, pa) 652 struct pciide_softc *sc; 653 struct pci_attach_args *pa; 654 { 655 struct pciide_channel *cp; 656 bus_size_t cmdsize, ctlsize; 657 pcireg_t interface; 658 int channel; 659 660 if (pciide_chipen(sc, pa) == 0) 661 return; 662 663 aprint_normal("%s: bus-master DMA support present", 664 sc->sc_wdcdev.sc_dev.dv_xname); 665 pciide_mapreg_dma(sc, pa); 666 aprint_normal("\n"); 667 668 /* 669 * Rev. <= 0x01 of the 3112 have a bug that can cause data 670 * corruption if DMA transfers cross an 8K boundary. This is 671 * apparently hard to tickle, but we'll go ahead and play it 672 * safe. 673 */ 674 if (PCI_REVISION(pa->pa_class) <= 0x01) { 675 sc->sc_dma_maxsegsz = 8192; 676 sc->sc_dma_boundary = 8192; 677 } 678 679 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 680 WDC_CAPABILITY_MODE; 681 sc->sc_wdcdev.PIO_cap = 4; 682 if (sc->sc_dma_ok) { 683 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 684 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 685 sc->sc_wdcdev.irqack = pciide_irqack; 686 sc->sc_wdcdev.DMA_cap = 2; 687 sc->sc_wdcdev.UDMA_cap = 6; 688 } 689 sc->sc_wdcdev.set_modes = cmd3112_setup_channel; 690 691 sc->sc_wdcdev.channels = sc->wdc_chanarray; 692 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 693 694 /* 695 * The 3112 can be told to identify as a RAID controller. 696 * In this case, we have to fake interface 697 */ 698 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 699 interface = PCI_INTERFACE(pa->pa_class); 700 } else { 701 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 702 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 703 } 704 705 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 706 cp = &sc->pciide_channels[channel]; 707 if (pciide_chansetup(sc, channel, interface) == 0) 708 continue; 709 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 710 pciide_pci_intr); 711 } 712 } 713 714 void 715 cmd3112_setup_channel(chp) 716 struct channel_softc *chp; 717 { 718 struct ata_drive_datas *drvp; 719 int drive; 720 u_int32_t idedma_ctl, dtm; 721 struct pciide_channel *cp = (struct pciide_channel*)chp; 722 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 723 724 /* setup DMA if needed */ 725 pciide_channel_dma_setup(cp); 726 727 idedma_ctl = 0; 728 dtm = 0; 729 730 for (drive = 0; drive < 2; drive++) { 731 drvp = &chp->ch_drive[drive]; 732 /* If no drive, skip */ 733 if ((drvp->drive_flags & DRIVE) == 0) 734 continue; 735 if (drvp->drive_flags & DRIVE_UDMA) { 736 /* use Ultra/DMA */ 737 drvp->drive_flags &= ~DRIVE_DMA; 738 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 739 dtm |= DTM_IDEx_DMA; 740 } else if (drvp->drive_flags & DRIVE_DMA) { 741 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 742 dtm |= DTM_IDEx_DMA; 743 } else { 744 dtm |= DTM_IDEx_PIO; 745 } 746 } 747 748 /* 749 * Nothing to do to setup modes; it is meaningless in S-ATA 750 * (but many S-ATA drives still want to get the SET_FEATURE 751 * command). 752 */ 753 if (idedma_ctl != 0) { 754 /* Add software bits in status register */ 755 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 756 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 757 idedma_ctl); 758 } 759 pci_conf_write(sc->sc_pc, sc->sc_tag, 760 chp->channel == 0 ? SII3112_DTM_IDE0 : SII3112_DTM_IDE1, dtm); 761 } 762
Indexes created Tue Sep 23 14:10:03 GMT 2025