cmdide.c revision 1.11.2.3
1 /* $NetBSD: cmdide.c,v 1.11.2.3 2004/08/25 06:58:05 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 36 #include <dev/pci/pcivar.h> 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pciidereg.h> 39 #include <dev/pci/pciidevar.h> 40 #include <dev/pci/pciide_cmd_reg.h> 41 42 43 static int cmdide_match(struct device *, struct cfdata *, void *); 44 static void cmdide_attach(struct device *, struct device *, void *); 45 46 CFATTACH_DECL(cmdide, sizeof(struct pciide_softc), 47 cmdide_match, cmdide_attach, NULL, NULL); 48 49 static void cmd_chip_map(struct pciide_softc*, struct pci_attach_args*); 50 static void cmd0643_9_chip_map(struct pciide_softc*, struct pci_attach_args*); 51 static void cmd0643_9_setup_channel(struct ata_channel*); 52 static void cmd_channel_map(struct pci_attach_args *, struct pciide_softc *, 53 int); 54 static int cmd_pci_intr(void *); 55 static void cmd646_9_irqack(struct ata_channel *); 56 static void cmd680_chip_map(struct pciide_softc*, struct pci_attach_args*); 57 static void cmd680_setup_channel(struct ata_channel*); 58 static void cmd680_channel_map(struct pci_attach_args *, struct pciide_softc *, 59 int); 60 61 static const struct pciide_product_desc pciide_cmd_products[] = { 62 { PCI_PRODUCT_CMDTECH_640, 63 0, 64 "CMD Technology PCI0640", 65 cmd_chip_map 66 }, 67 { PCI_PRODUCT_CMDTECH_643, 68 0, 69 "CMD Technology PCI0643", 70 cmd0643_9_chip_map, 71 }, 72 { PCI_PRODUCT_CMDTECH_646, 73 0, 74 "CMD Technology PCI0646", 75 cmd0643_9_chip_map, 76 }, 77 { PCI_PRODUCT_CMDTECH_648, 78 0, 79 "CMD Technology PCI0648", 80 cmd0643_9_chip_map, 81 }, 82 { PCI_PRODUCT_CMDTECH_649, 83 0, 84 "CMD Technology PCI0649", 85 cmd0643_9_chip_map, 86 }, 87 { PCI_PRODUCT_CMDTECH_680, 88 0, 89 "Silicon Image 0680", 90 cmd680_chip_map, 91 }, 92 { 0, 93 0, 94 NULL, 95 NULL 96 } 97 }; 98 99 static int 100 cmdide_match(struct device *parent, struct cfdata *match, void *aux) 101 { 102 struct pci_attach_args *pa = aux; 103 104 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 105 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 106 return (2); 107 } 108 return (0); 109 } 110 111 static void 112 cmdide_attach(struct device *parent, struct device *self, void *aux) 113 { 114 struct pci_attach_args *pa = aux; 115 struct pciide_softc *sc = (struct pciide_softc *)self; 116 117 pciide_common_attach(sc, pa, 118 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 119 120 } 121 122 static void 123 cmd_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 124 int channel) 125 { 126 struct pciide_channel *cp = &sc->pciide_channels[channel]; 127 bus_size_t cmdsize, ctlsize; 128 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 129 int interface, one_channel; 130 131 /* 132 * The 0648/0649 can be told to identify as a RAID controller. 133 * In this case, we have to fake interface 134 */ 135 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 136 interface = PCIIDE_INTERFACE_SETTABLE(0) | 137 PCIIDE_INTERFACE_SETTABLE(1); 138 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 139 CMD_CONF_DSA1) 140 interface |= PCIIDE_INTERFACE_PCI(0) | 141 PCIIDE_INTERFACE_PCI(1); 142 } else { 143 interface = PCI_INTERFACE(pa->pa_class); 144 } 145 146 sc->wdc_chanarray[channel] = &cp->ata_channel; 147 cp->name = PCIIDE_CHANNEL_NAME(channel); 148 cp->ata_channel.ch_channel = channel; 149 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 150 151 /* 152 * Older CMD64X doesn't have independant channels 153 */ 154 switch (sc->sc_pp->ide_product) { 155 case PCI_PRODUCT_CMDTECH_649: 156 one_channel = 0; 157 break; 158 default: 159 one_channel = 1; 160 break; 161 } 162 163 if (channel > 0 && one_channel) { 164 cp->ata_channel.ch_queue = 165 sc->pciide_channels[0].ata_channel.ch_queue; 166 } else { 167 cp->ata_channel.ch_queue = 168 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 169 } 170 if (cp->ata_channel.ch_queue == NULL) { 171 aprint_error("%s %s channel: " 172 "can't allocate memory for command queue", 173 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 174 return; 175 } 176 177 aprint_normal("%s: %s channel %s to %s mode\n", 178 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name, 179 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 180 "configured" : "wired", 181 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 182 "native-PCI" : "compatibility"); 183 184 /* 185 * with a CMD PCI64x, if we get here, the first channel is enabled: 186 * there's no way to disable the first channel without disabling 187 * the whole device 188 */ 189 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 190 aprint_normal("%s: %s channel ignored (disabled)\n", 191 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 192 cp->ata_channel.ch_flags |= ATACH_DISABLED; 193 return; 194 } 195 196 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 197 } 198 199 static int 200 cmd_pci_intr(void *arg) 201 { 202 struct pciide_softc *sc = arg; 203 struct pciide_channel *cp; 204 struct ata_channel *wdc_cp; 205 int i, rv, crv; 206 u_int32_t priirq, secirq; 207 208 rv = 0; 209 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 210 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 211 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 212 cp = &sc->pciide_channels[i]; 213 wdc_cp = &cp->ata_channel; 214 /* If a compat channel skip. */ 215 if (cp->compat) 216 continue; 217 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 218 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 219 crv = wdcintr(wdc_cp); 220 if (crv == 0) { 221 printf("%s:%d: bogus intr\n", 222 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 223 sc->sc_wdcdev.irqack(wdc_cp); 224 } else 225 rv = 1; 226 } 227 } 228 return rv; 229 } 230 231 static void 232 cmd_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 233 { 234 int channel; 235 236 /* 237 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 238 * and base addresses registers can be disabled at 239 * hardware level. In this case, the device is wired 240 * in compat mode and its first channel is always enabled, 241 * but we can't rely on PCI_COMMAND_IO_ENABLE. 242 * In fact, it seems that the first channel of the CMD PCI0640 243 * can't be disabled. 244 */ 245 246 #ifdef PCIIDE_CMD064x_DISABLE 247 if (pciide_chipen(sc, pa) == 0) 248 return; 249 #endif 250 251 aprint_normal("%s: hardware does not support DMA\n", 252 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 253 sc->sc_dma_ok = 0; 254 255 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 256 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 257 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 258 259 wdc_allocate_regs(&sc->sc_wdcdev); 260 261 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 262 channel++) { 263 cmd_channel_map(pa, sc, channel); 264 } 265 } 266 267 static void 268 cmd0643_9_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 269 { 270 int channel; 271 pcireg_t rev = PCI_REVISION(pa->pa_class); 272 273 /* 274 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 275 * and base addresses registers can be disabled at 276 * hardware level. In this case, the device is wired 277 * in compat mode and its first channel is always enabled, 278 * but we can't rely on PCI_COMMAND_IO_ENABLE. 279 * In fact, it seems that the first channel of the CMD PCI0640 280 * can't be disabled. 281 */ 282 283 #ifdef PCIIDE_CMD064x_DISABLE 284 if (pciide_chipen(sc, pa) == 0) 285 return; 286 #endif 287 288 aprint_normal("%s: bus-master DMA support present", 289 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 290 pciide_mapreg_dma(sc, pa); 291 aprint_normal("\n"); 292 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 293 if (sc->sc_dma_ok) { 294 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 295 switch (sc->sc_pp->ide_product) { 296 case PCI_PRODUCT_CMDTECH_649: 297 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 298 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 299 sc->sc_wdcdev.irqack = cmd646_9_irqack; 300 break; 301 case PCI_PRODUCT_CMDTECH_648: 302 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 303 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 304 sc->sc_wdcdev.irqack = cmd646_9_irqack; 305 break; 306 case PCI_PRODUCT_CMDTECH_646: 307 if (rev >= CMD0646U2_REV) { 308 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 309 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 310 } else if (rev >= CMD0646U_REV) { 311 /* 312 * Linux's driver claims that the 646U is broken 313 * with UDMA. Only enable it if we know what we're 314 * doing 315 */ 316 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 317 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 318 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 319 #endif 320 /* explicitly disable UDMA */ 321 pciide_pci_write(sc->sc_pc, sc->sc_tag, 322 CMD_UDMATIM(0), 0); 323 pciide_pci_write(sc->sc_pc, sc->sc_tag, 324 CMD_UDMATIM(1), 0); 325 } 326 sc->sc_wdcdev.irqack = cmd646_9_irqack; 327 break; 328 default: 329 sc->sc_wdcdev.irqack = pciide_irqack; 330 } 331 } 332 333 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 334 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 335 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 336 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 337 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd0643_9_setup_channel; 338 339 ATADEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 340 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 341 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 342 DEBUG_PROBE); 343 344 wdc_allocate_regs(&sc->sc_wdcdev); 345 346 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 347 channel++) 348 cmd_channel_map(pa, sc, channel); 349 350 /* 351 * note - this also makes sure we clear the irq disable and reset 352 * bits 353 */ 354 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 355 ATADEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 356 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 357 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 358 DEBUG_PROBE); 359 } 360 361 static void 362 cmd0643_9_setup_channel(struct ata_channel *chp) 363 { 364 struct ata_drive_datas *drvp; 365 u_int8_t tim; 366 u_int32_t idedma_ctl, udma_reg; 367 int drive, s; 368 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 369 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 370 371 idedma_ctl = 0; 372 /* setup DMA if needed */ 373 pciide_channel_dma_setup(cp); 374 375 for (drive = 0; drive < 2; drive++) { 376 drvp = &chp->ch_drive[drive]; 377 /* If no drive, skip */ 378 if ((drvp->drive_flags & DRIVE) == 0) 379 continue; 380 /* add timing values, setup DMA if needed */ 381 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 382 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 383 if (drvp->drive_flags & DRIVE_UDMA) { 384 /* UltraDMA on a 646U2, 0648 or 0649 */ 385 s = splbio(); 386 drvp->drive_flags &= ~DRIVE_DMA; 387 splx(s); 388 udma_reg = pciide_pci_read(sc->sc_pc, 389 sc->sc_tag, CMD_UDMATIM(chp->ch_channel)); 390 if (drvp->UDMA_mode > 2 && 391 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 392 CMD_BICSR) & 393 CMD_BICSR_80(chp->ch_channel)) == 0) 394 drvp->UDMA_mode = 2; 395 if (drvp->UDMA_mode > 2) 396 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 397 else if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 2) 398 udma_reg |= CMD_UDMATIM_UDMA33(drive); 399 udma_reg |= CMD_UDMATIM_UDMA(drive); 400 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 401 CMD_UDMATIM_TIM_OFF(drive)); 402 udma_reg |= 403 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 404 CMD_UDMATIM_TIM_OFF(drive)); 405 pciide_pci_write(sc->sc_pc, sc->sc_tag, 406 CMD_UDMATIM(chp->ch_channel), udma_reg); 407 } else { 408 /* 409 * use Multiword DMA. 410 * Timings will be used for both PIO and DMA, 411 * so adjust DMA mode if needed 412 * if we have a 0646U2/8/9, turn off UDMA 413 */ 414 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 415 udma_reg = pciide_pci_read(sc->sc_pc, 416 sc->sc_tag, 417 CMD_UDMATIM(chp->ch_channel)); 418 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 419 pciide_pci_write(sc->sc_pc, sc->sc_tag, 420 CMD_UDMATIM(chp->ch_channel), 421 udma_reg); 422 } 423 if (drvp->PIO_mode >= 3 && 424 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 425 drvp->DMA_mode = drvp->PIO_mode - 2; 426 } 427 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 428 } 429 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 430 } 431 pciide_pci_write(sc->sc_pc, sc->sc_tag, 432 CMD_DATA_TIM(chp->ch_channel, drive), tim); 433 } 434 if (idedma_ctl != 0) { 435 /* Add software bits in status register */ 436 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 437 idedma_ctl); 438 } 439 } 440 441 static void 442 cmd646_9_irqack(struct ata_channel *chp) 443 { 444 u_int32_t priirq, secirq; 445 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 446 447 if (chp->ch_channel == 0) { 448 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 449 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 450 } else { 451 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 452 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 453 } 454 pciide_irqack(chp); 455 } 456 457 static void 458 cmd680_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 459 { 460 int channel; 461 462 if (pciide_chipen(sc, pa) == 0) 463 return; 464 465 aprint_normal("%s: bus-master DMA support present", 466 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 467 pciide_mapreg_dma(sc, pa); 468 aprint_normal("\n"); 469 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 470 if (sc->sc_dma_ok) { 471 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 472 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 473 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 474 sc->sc_wdcdev.irqack = pciide_irqack; 475 } 476 477 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 478 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 479 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 480 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 481 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd680_setup_channel; 482 483 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 484 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 485 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 486 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 487 488 wdc_allocate_regs(&sc->sc_wdcdev); 489 490 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 491 channel++) 492 cmd680_channel_map(pa, sc, channel); 493 } 494 495 static void 496 cmd680_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 497 int channel) 498 { 499 struct pciide_channel *cp = &sc->pciide_channels[channel]; 500 bus_size_t cmdsize, ctlsize; 501 int interface, i, reg; 502 static const u_int8_t init_val[] = 503 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 504 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 505 506 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 507 interface = PCIIDE_INTERFACE_SETTABLE(0) | 508 PCIIDE_INTERFACE_SETTABLE(1); 509 interface |= PCIIDE_INTERFACE_PCI(0) | 510 PCIIDE_INTERFACE_PCI(1); 511 } else { 512 interface = PCI_INTERFACE(pa->pa_class); 513 } 514 515 sc->wdc_chanarray[channel] = &cp->ata_channel; 516 cp->name = PCIIDE_CHANNEL_NAME(channel); 517 cp->ata_channel.ch_channel = channel; 518 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 519 520 cp->ata_channel.ch_queue = 521 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 522 if (cp->ata_channel.ch_queue == NULL) { 523 aprint_error("%s %s channel: " 524 "can't allocate memory for command queue", 525 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 526 return; 527 } 528 529 /* XXX */ 530 reg = 0xa2 + channel * 16; 531 for (i = 0; i < sizeof(init_val); i++) 532 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 533 534 aprint_normal("%s: %s channel %s to %s mode\n", 535 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name, 536 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 537 "configured" : "wired", 538 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 539 "native-PCI" : "compatibility"); 540 541 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 542 } 543 544 static void 545 cmd680_setup_channel(struct ata_channel *chp) 546 { 547 struct ata_drive_datas *drvp; 548 u_int8_t mode, off, scsc; 549 u_int16_t val; 550 u_int32_t idedma_ctl; 551 int drive, s; 552 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 553 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 554 pci_chipset_tag_t pc = sc->sc_pc; 555 pcitag_t pa = sc->sc_tag; 556 static const u_int8_t udma2_tbl[] = 557 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 558 static const u_int8_t udma_tbl[] = 559 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 560 static const u_int16_t dma_tbl[] = 561 { 0x2208, 0x10c2, 0x10c1 }; 562 static const u_int16_t pio_tbl[] = 563 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 564 565 idedma_ctl = 0; 566 pciide_channel_dma_setup(cp); 567 mode = pciide_pci_read(pc, pa, 0x80 + chp->ch_channel * 4); 568 569 for (drive = 0; drive < 2; drive++) { 570 drvp = &chp->ch_drive[drive]; 571 /* If no drive, skip */ 572 if ((drvp->drive_flags & DRIVE) == 0) 573 continue; 574 mode &= ~(0x03 << (drive * 4)); 575 if (drvp->drive_flags & DRIVE_UDMA) { 576 s = splbio(); 577 drvp->drive_flags &= ~DRIVE_DMA; 578 splx(s); 579 off = 0xa0 + chp->ch_channel * 16; 580 if (drvp->UDMA_mode > 2 && 581 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 582 drvp->UDMA_mode = 2; 583 scsc = pciide_pci_read(pc, pa, 0x8a); 584 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 585 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 586 scsc = pciide_pci_read(pc, pa, 0x8a); 587 if ((scsc & 0x30) == 0) 588 drvp->UDMA_mode = 5; 589 } 590 mode |= 0x03 << (drive * 4); 591 off = 0xac + chp->ch_channel * 16 + drive * 2; 592 val = pciide_pci_read(pc, pa, off) & ~0x3f; 593 if (scsc & 0x30) 594 val |= udma2_tbl[drvp->UDMA_mode]; 595 else 596 val |= udma_tbl[drvp->UDMA_mode]; 597 pciide_pci_write(pc, pa, off, val); 598 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 599 } else if (drvp->drive_flags & DRIVE_DMA) { 600 mode |= 0x02 << (drive * 4); 601 off = 0xa8 + chp->ch_channel * 16 + drive * 2; 602 val = dma_tbl[drvp->DMA_mode]; 603 pciide_pci_write(pc, pa, off, val & 0xff); 604 pciide_pci_write(pc, pa, off, val >> 8); 605 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 606 } else { 607 mode |= 0x01 << (drive * 4); 608 off = 0xa4 + chp->ch_channel * 16 + drive * 2; 609 val = pio_tbl[drvp->PIO_mode]; 610 pciide_pci_write(pc, pa, off, val & 0xff); 611 pciide_pci_write(pc, pa, off, val >> 8); 612 } 613 } 614 615 pciide_pci_write(pc, pa, 0x80 + chp->ch_channel * 4, mode); 616 if (idedma_ctl != 0) { 617 /* Add software bits in status register */ 618 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 619 idedma_ctl); 620 } 621 } 622
Indexes created Wed Oct 01 19:09:53 GMT 2025