cmdide.c revision 1.14
1 /* $NetBSD: cmdide.c,v 1.14 2004/08/14 15:08:06 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 36 #include <dev/pci/pcivar.h> 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pciidereg.h> 39 #include <dev/pci/pciidevar.h> 40 #include <dev/pci/pciide_cmd_reg.h> 41 42 43 static int cmdide_match(struct device *, struct cfdata *, void *); 44 static void cmdide_attach(struct device *, struct device *, void *); 45 46 CFATTACH_DECL(cmdide, sizeof(struct pciide_softc), 47 cmdide_match, cmdide_attach, NULL, NULL); 48 49 static void cmd_chip_map(struct pciide_softc*, struct pci_attach_args*); 50 static void cmd0643_9_chip_map(struct pciide_softc*, struct pci_attach_args*); 51 static void cmd0643_9_setup_channel(struct ata_channel*); 52 static void cmd_channel_map(struct pci_attach_args *, struct pciide_softc *, 53 int); 54 static int cmd_pci_intr(void *); 55 static void cmd646_9_irqack(struct ata_channel *); 56 static void cmd680_chip_map(struct pciide_softc*, struct pci_attach_args*); 57 static void cmd680_setup_channel(struct ata_channel*); 58 static void cmd680_channel_map(struct pci_attach_args *, struct pciide_softc *, 59 int); 60 61 static const struct pciide_product_desc pciide_cmd_products[] = { 62 { PCI_PRODUCT_CMDTECH_640, 63 0, 64 "CMD Technology PCI0640", 65 cmd_chip_map 66 }, 67 { PCI_PRODUCT_CMDTECH_643, 68 0, 69 "CMD Technology PCI0643", 70 cmd0643_9_chip_map, 71 }, 72 { PCI_PRODUCT_CMDTECH_646, 73 0, 74 "CMD Technology PCI0646", 75 cmd0643_9_chip_map, 76 }, 77 { PCI_PRODUCT_CMDTECH_648, 78 0, 79 "CMD Technology PCI0648", 80 cmd0643_9_chip_map, 81 }, 82 { PCI_PRODUCT_CMDTECH_649, 83 0, 84 "CMD Technology PCI0649", 85 cmd0643_9_chip_map, 86 }, 87 { PCI_PRODUCT_CMDTECH_680, 88 0, 89 "Silicon Image 0680", 90 cmd680_chip_map, 91 }, 92 { 0, 93 0, 94 NULL, 95 NULL 96 } 97 }; 98 99 static int 100 cmdide_match(struct device *parent, struct cfdata *match, void *aux) 101 { 102 struct pci_attach_args *pa = aux; 103 104 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 105 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 106 return (2); 107 } 108 return (0); 109 } 110 111 static void 112 cmdide_attach(struct device *parent, struct device *self, void *aux) 113 { 114 struct pci_attach_args *pa = aux; 115 struct pciide_softc *sc = (struct pciide_softc *)self; 116 117 pciide_common_attach(sc, pa, 118 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 119 120 } 121 122 static void 123 cmd_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 124 int channel) 125 { 126 struct pciide_channel *cp = &sc->pciide_channels[channel]; 127 bus_size_t cmdsize, ctlsize; 128 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 129 int interface, one_channel; 130 131 /* 132 * The 0648/0649 can be told to identify as a RAID controller. 133 * In this case, we have to fake interface 134 */ 135 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 136 interface = PCIIDE_INTERFACE_SETTABLE(0) | 137 PCIIDE_INTERFACE_SETTABLE(1); 138 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 139 CMD_CONF_DSA1) 140 interface |= PCIIDE_INTERFACE_PCI(0) | 141 PCIIDE_INTERFACE_PCI(1); 142 } else { 143 interface = PCI_INTERFACE(pa->pa_class); 144 } 145 146 sc->wdc_chanarray[channel] = &cp->ata_channel; 147 cp->name = PCIIDE_CHANNEL_NAME(channel); 148 cp->ata_channel.ch_channel = channel; 149 cp->ata_channel.ch_wdc = &sc->sc_wdcdev; 150 151 /* 152 * Older CMD64X doesn't have independant channels 153 */ 154 switch (sc->sc_pp->ide_product) { 155 case PCI_PRODUCT_CMDTECH_649: 156 one_channel = 0; 157 break; 158 default: 159 one_channel = 1; 160 break; 161 } 162 163 if (channel > 0 && one_channel) { 164 cp->ata_channel.ch_queue = 165 sc->pciide_channels[0].ata_channel.ch_queue; 166 } else { 167 cp->ata_channel.ch_queue = 168 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 169 } 170 if (cp->ata_channel.ch_queue == NULL) { 171 aprint_error("%s %s channel: " 172 "can't allocate memory for command queue", 173 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 174 return; 175 } 176 177 aprint_normal("%s: %s channel %s to %s mode\n", 178 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 179 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 180 "configured" : "wired", 181 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 182 "native-PCI" : "compatibility"); 183 184 /* 185 * with a CMD PCI64x, if we get here, the first channel is enabled: 186 * there's no way to disable the first channel without disabling 187 * the whole device 188 */ 189 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 190 aprint_normal("%s: %s channel ignored (disabled)\n", 191 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 192 cp->ata_channel.ch_flags |= ATACH_DISABLED; 193 return; 194 } 195 196 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 197 } 198 199 static int 200 cmd_pci_intr(void *arg) 201 { 202 struct pciide_softc *sc = arg; 203 struct pciide_channel *cp; 204 struct ata_channel *wdc_cp; 205 int i, rv, crv; 206 u_int32_t priirq, secirq; 207 208 rv = 0; 209 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 210 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 211 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 212 cp = &sc->pciide_channels[i]; 213 wdc_cp = &cp->ata_channel; 214 /* If a compat channel skip. */ 215 if (cp->compat) 216 continue; 217 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 218 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 219 crv = wdcintr(wdc_cp); 220 if (crv == 0) { 221 printf("%s:%d: bogus intr\n", 222 sc->sc_wdcdev.sc_dev.dv_xname, i); 223 sc->sc_wdcdev.irqack(wdc_cp); 224 } else 225 rv = 1; 226 } 227 } 228 return rv; 229 } 230 231 static void 232 cmd_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 233 { 234 int channel; 235 236 /* 237 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 238 * and base addresses registers can be disabled at 239 * hardware level. In this case, the device is wired 240 * in compat mode and its first channel is always enabled, 241 * but we can't rely on PCI_COMMAND_IO_ENABLE. 242 * In fact, it seems that the first channel of the CMD PCI0640 243 * can't be disabled. 244 */ 245 246 #ifdef PCIIDE_CMD064x_DISABLE 247 if (pciide_chipen(sc, pa) == 0) 248 return; 249 #endif 250 251 aprint_normal("%s: hardware does not support DMA\n", 252 sc->sc_wdcdev.sc_dev.dv_xname); 253 sc->sc_dma_ok = 0; 254 255 sc->sc_wdcdev.channels = sc->wdc_chanarray; 256 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 257 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 258 259 wdc_allocate_regs(&sc->sc_wdcdev); 260 261 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 262 cmd_channel_map(pa, sc, channel); 263 } 264 } 265 266 static void 267 cmd0643_9_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 268 { 269 int channel; 270 pcireg_t rev = PCI_REVISION(pa->pa_class); 271 272 /* 273 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 274 * and base addresses registers can be disabled at 275 * hardware level. In this case, the device is wired 276 * in compat mode and its first channel is always enabled, 277 * but we can't rely on PCI_COMMAND_IO_ENABLE. 278 * In fact, it seems that the first channel of the CMD PCI0640 279 * can't be disabled. 280 */ 281 282 #ifdef PCIIDE_CMD064x_DISABLE 283 if (pciide_chipen(sc, pa) == 0) 284 return; 285 #endif 286 287 aprint_normal("%s: bus-master DMA support present", 288 sc->sc_wdcdev.sc_dev.dv_xname); 289 pciide_mapreg_dma(sc, pa); 290 aprint_normal("\n"); 291 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32; 292 if (sc->sc_dma_ok) { 293 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 294 switch (sc->sc_pp->ide_product) { 295 case PCI_PRODUCT_CMDTECH_649: 296 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 297 sc->sc_wdcdev.UDMA_cap = 5; 298 sc->sc_wdcdev.irqack = cmd646_9_irqack; 299 break; 300 case PCI_PRODUCT_CMDTECH_648: 301 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 302 sc->sc_wdcdev.UDMA_cap = 4; 303 sc->sc_wdcdev.irqack = cmd646_9_irqack; 304 break; 305 case PCI_PRODUCT_CMDTECH_646: 306 if (rev >= CMD0646U2_REV) { 307 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 308 sc->sc_wdcdev.UDMA_cap = 2; 309 } else if (rev >= CMD0646U_REV) { 310 /* 311 * Linux's driver claims that the 646U is broken 312 * with UDMA. Only enable it if we know what we're 313 * doing 314 */ 315 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 316 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 317 sc->sc_wdcdev.UDMA_cap = 2; 318 #endif 319 /* explicitly disable UDMA */ 320 pciide_pci_write(sc->sc_pc, sc->sc_tag, 321 CMD_UDMATIM(0), 0); 322 pciide_pci_write(sc->sc_pc, sc->sc_tag, 323 CMD_UDMATIM(1), 0); 324 } 325 sc->sc_wdcdev.irqack = cmd646_9_irqack; 326 break; 327 default: 328 sc->sc_wdcdev.irqack = pciide_irqack; 329 } 330 } 331 332 sc->sc_wdcdev.channels = sc->wdc_chanarray; 333 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 334 sc->sc_wdcdev.PIO_cap = 4; 335 sc->sc_wdcdev.DMA_cap = 2; 336 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 337 338 ATADEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 339 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 340 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 341 DEBUG_PROBE); 342 343 wdc_allocate_regs(&sc->sc_wdcdev); 344 345 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) 346 cmd_channel_map(pa, sc, channel); 347 348 /* 349 * note - this also makes sure we clear the irq disable and reset 350 * bits 351 */ 352 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 353 ATADEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 354 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 355 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 356 DEBUG_PROBE); 357 } 358 359 static void 360 cmd0643_9_setup_channel(struct ata_channel *chp) 361 { 362 struct ata_drive_datas *drvp; 363 u_int8_t tim; 364 u_int32_t idedma_ctl, udma_reg; 365 int drive; 366 struct pciide_channel *cp = (struct pciide_channel*)chp; 367 struct pciide_softc *sc = (struct pciide_softc *)cp->ata_channel.ch_wdc; 368 369 idedma_ctl = 0; 370 /* setup DMA if needed */ 371 pciide_channel_dma_setup(cp); 372 373 for (drive = 0; drive < 2; drive++) { 374 drvp = &chp->ch_drive[drive]; 375 /* If no drive, skip */ 376 if ((drvp->drive_flags & DRIVE) == 0) 377 continue; 378 /* add timing values, setup DMA if needed */ 379 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 380 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 381 if (drvp->drive_flags & DRIVE_UDMA) { 382 /* UltraDMA on a 646U2, 0648 or 0649 */ 383 drvp->drive_flags &= ~DRIVE_DMA; 384 udma_reg = pciide_pci_read(sc->sc_pc, 385 sc->sc_tag, CMD_UDMATIM(chp->ch_channel)); 386 if (drvp->UDMA_mode > 2 && 387 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 388 CMD_BICSR) & 389 CMD_BICSR_80(chp->ch_channel)) == 0) 390 drvp->UDMA_mode = 2; 391 if (drvp->UDMA_mode > 2) 392 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 393 else if (sc->sc_wdcdev.UDMA_cap > 2) 394 udma_reg |= CMD_UDMATIM_UDMA33(drive); 395 udma_reg |= CMD_UDMATIM_UDMA(drive); 396 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 397 CMD_UDMATIM_TIM_OFF(drive)); 398 udma_reg |= 399 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 400 CMD_UDMATIM_TIM_OFF(drive)); 401 pciide_pci_write(sc->sc_pc, sc->sc_tag, 402 CMD_UDMATIM(chp->ch_channel), udma_reg); 403 } else { 404 /* 405 * use Multiword DMA. 406 * Timings will be used for both PIO and DMA, 407 * so adjust DMA mode if needed 408 * if we have a 0646U2/8/9, turn off UDMA 409 */ 410 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 411 udma_reg = pciide_pci_read(sc->sc_pc, 412 sc->sc_tag, 413 CMD_UDMATIM(chp->ch_channel)); 414 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 415 pciide_pci_write(sc->sc_pc, sc->sc_tag, 416 CMD_UDMATIM(chp->ch_channel), 417 udma_reg); 418 } 419 if (drvp->PIO_mode >= 3 && 420 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 421 drvp->DMA_mode = drvp->PIO_mode - 2; 422 } 423 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 424 } 425 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 426 } 427 pciide_pci_write(sc->sc_pc, sc->sc_tag, 428 CMD_DATA_TIM(chp->ch_channel, drive), tim); 429 } 430 if (idedma_ctl != 0) { 431 /* Add software bits in status register */ 432 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 433 idedma_ctl); 434 } 435 } 436 437 static void 438 cmd646_9_irqack(struct ata_channel *chp) 439 { 440 u_int32_t priirq, secirq; 441 struct pciide_channel *cp = (struct pciide_channel*)chp; 442 struct pciide_softc *sc = (struct pciide_softc *)cp->ata_channel.ch_wdc; 443 444 if (chp->ch_channel == 0) { 445 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 446 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 447 } else { 448 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 449 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 450 } 451 pciide_irqack(chp); 452 } 453 454 static void 455 cmd680_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 456 { 457 int channel; 458 459 if (pciide_chipen(sc, pa) == 0) 460 return; 461 462 aprint_normal("%s: bus-master DMA support present", 463 sc->sc_wdcdev.sc_dev.dv_xname); 464 pciide_mapreg_dma(sc, pa); 465 aprint_normal("\n"); 466 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32; 467 if (sc->sc_dma_ok) { 468 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 469 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 470 sc->sc_wdcdev.UDMA_cap = 6; 471 sc->sc_wdcdev.irqack = pciide_irqack; 472 } 473 474 sc->sc_wdcdev.channels = sc->wdc_chanarray; 475 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 476 sc->sc_wdcdev.PIO_cap = 4; 477 sc->sc_wdcdev.DMA_cap = 2; 478 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 479 480 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 481 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 482 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 483 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 484 485 wdc_allocate_regs(&sc->sc_wdcdev); 486 487 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) 488 cmd680_channel_map(pa, sc, channel); 489 } 490 491 static void 492 cmd680_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 493 int channel) 494 { 495 struct pciide_channel *cp = &sc->pciide_channels[channel]; 496 bus_size_t cmdsize, ctlsize; 497 int interface, i, reg; 498 static const u_int8_t init_val[] = 499 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 500 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 501 502 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 503 interface = PCIIDE_INTERFACE_SETTABLE(0) | 504 PCIIDE_INTERFACE_SETTABLE(1); 505 interface |= PCIIDE_INTERFACE_PCI(0) | 506 PCIIDE_INTERFACE_PCI(1); 507 } else { 508 interface = PCI_INTERFACE(pa->pa_class); 509 } 510 511 sc->wdc_chanarray[channel] = &cp->ata_channel; 512 cp->name = PCIIDE_CHANNEL_NAME(channel); 513 cp->ata_channel.ch_channel = channel; 514 cp->ata_channel.ch_wdc = &sc->sc_wdcdev; 515 516 cp->ata_channel.ch_queue = 517 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 518 if (cp->ata_channel.ch_queue == NULL) { 519 aprint_error("%s %s channel: " 520 "can't allocate memory for command queue", 521 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 522 return; 523 } 524 525 /* XXX */ 526 reg = 0xa2 + channel * 16; 527 for (i = 0; i < sizeof(init_val); i++) 528 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 529 530 aprint_normal("%s: %s channel %s to %s mode\n", 531 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 532 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 533 "configured" : "wired", 534 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 535 "native-PCI" : "compatibility"); 536 537 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 538 } 539 540 static void 541 cmd680_setup_channel(struct ata_channel *chp) 542 { 543 struct ata_drive_datas *drvp; 544 u_int8_t mode, off, scsc; 545 u_int16_t val; 546 u_int32_t idedma_ctl; 547 int drive; 548 struct pciide_channel *cp = (struct pciide_channel*)chp; 549 struct pciide_softc *sc = (struct pciide_softc *)cp->ata_channel.ch_wdc; 550 pci_chipset_tag_t pc = sc->sc_pc; 551 pcitag_t pa = sc->sc_tag; 552 static const u_int8_t udma2_tbl[] = 553 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 554 static const u_int8_t udma_tbl[] = 555 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 556 static const u_int16_t dma_tbl[] = 557 { 0x2208, 0x10c2, 0x10c1 }; 558 static const u_int16_t pio_tbl[] = 559 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 560 561 idedma_ctl = 0; 562 pciide_channel_dma_setup(cp); 563 mode = pciide_pci_read(pc, pa, 0x80 + chp->ch_channel * 4); 564 565 for (drive = 0; drive < 2; drive++) { 566 drvp = &chp->ch_drive[drive]; 567 /* If no drive, skip */ 568 if ((drvp->drive_flags & DRIVE) == 0) 569 continue; 570 mode &= ~(0x03 << (drive * 4)); 571 if (drvp->drive_flags & DRIVE_UDMA) { 572 drvp->drive_flags &= ~DRIVE_DMA; 573 off = 0xa0 + chp->ch_channel * 16; 574 if (drvp->UDMA_mode > 2 && 575 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 576 drvp->UDMA_mode = 2; 577 scsc = pciide_pci_read(pc, pa, 0x8a); 578 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 579 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 580 scsc = pciide_pci_read(pc, pa, 0x8a); 581 if ((scsc & 0x30) == 0) 582 drvp->UDMA_mode = 5; 583 } 584 mode |= 0x03 << (drive * 4); 585 off = 0xac + chp->ch_channel * 16 + drive * 2; 586 val = pciide_pci_read(pc, pa, off) & ~0x3f; 587 if (scsc & 0x30) 588 val |= udma2_tbl[drvp->UDMA_mode]; 589 else 590 val |= udma_tbl[drvp->UDMA_mode]; 591 pciide_pci_write(pc, pa, off, val); 592 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 593 } else if (drvp->drive_flags & DRIVE_DMA) { 594 mode |= 0x02 << (drive * 4); 595 off = 0xa8 + chp->ch_channel * 16 + drive * 2; 596 val = dma_tbl[drvp->DMA_mode]; 597 pciide_pci_write(pc, pa, off, val & 0xff); 598 pciide_pci_write(pc, pa, off, val >> 8); 599 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 600 } else { 601 mode |= 0x01 << (drive * 4); 602 off = 0xa4 + chp->ch_channel * 16 + drive * 2; 603 val = pio_tbl[drvp->PIO_mode]; 604 pciide_pci_write(pc, pa, off, val & 0xff); 605 pciide_pci_write(pc, pa, off, val >> 8); 606 } 607 } 608 609 pciide_pci_write(pc, pa, 0x80 + chp->ch_channel * 4, mode); 610 if (idedma_ctl != 0) { 611 /* Add software bits in status register */ 612 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 613 idedma_ctl); 614 } 615 } 616
Indexes created Tue Sep 23 14:10:03 GMT 2025