cmdide.c revision 1.19.2.1
1 /* $NetBSD: cmdide.c,v 1.19.2.1 2006/06/21 15:05:03 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: cmdide.c,v 1.19.2.1 2006/06/21 15:05:03 yamt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_cmd_reg.h> 44 45 46 static int cmdide_match(struct device *, struct cfdata *, void *); 47 static void cmdide_attach(struct device *, struct device *, void *); 48 49 CFATTACH_DECL(cmdide, sizeof(struct pciide_softc), 50 cmdide_match, cmdide_attach, NULL, NULL); 51 52 static void cmd_chip_map(struct pciide_softc*, struct pci_attach_args*); 53 static void cmd0643_9_chip_map(struct pciide_softc*, struct pci_attach_args*); 54 static void cmd0643_9_setup_channel(struct ata_channel*); 55 static void cmd_channel_map(struct pci_attach_args *, struct pciide_softc *, 56 int); 57 static int cmd_pci_intr(void *); 58 static void cmd646_9_irqack(struct ata_channel *); 59 static void cmd680_chip_map(struct pciide_softc*, struct pci_attach_args*); 60 static void cmd680_setup_channel(struct ata_channel*); 61 static void cmd680_channel_map(struct pci_attach_args *, struct pciide_softc *, 62 int); 63 64 static const struct pciide_product_desc pciide_cmd_products[] = { 65 { PCI_PRODUCT_CMDTECH_640, 66 0, 67 "CMD Technology PCI0640", 68 cmd_chip_map 69 }, 70 { PCI_PRODUCT_CMDTECH_643, 71 0, 72 "CMD Technology PCI0643", 73 cmd0643_9_chip_map, 74 }, 75 { PCI_PRODUCT_CMDTECH_646, 76 0, 77 "CMD Technology PCI0646", 78 cmd0643_9_chip_map, 79 }, 80 { PCI_PRODUCT_CMDTECH_648, 81 0, 82 "CMD Technology PCI0648", 83 cmd0643_9_chip_map, 84 }, 85 { PCI_PRODUCT_CMDTECH_649, 86 0, 87 "CMD Technology PCI0649", 88 cmd0643_9_chip_map, 89 }, 90 { PCI_PRODUCT_CMDTECH_680, 91 0, 92 "Silicon Image 0680", 93 cmd680_chip_map, 94 }, 95 { 0, 96 0, 97 NULL, 98 NULL 99 } 100 }; 101 102 static int 103 cmdide_match(struct device *parent, struct cfdata *match, void *aux) 104 { 105 struct pci_attach_args *pa = aux; 106 107 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 108 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 109 return (2); 110 } 111 return (0); 112 } 113 114 static void 115 cmdide_attach(struct device *parent, struct device *self, void *aux) 116 { 117 struct pci_attach_args *pa = aux; 118 struct pciide_softc *sc = (struct pciide_softc *)self; 119 120 pciide_common_attach(sc, pa, 121 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 122 123 } 124 125 static void 126 cmd_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 127 int channel) 128 { 129 struct pciide_channel *cp = &sc->pciide_channels[channel]; 130 bus_size_t cmdsize, ctlsize; 131 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 132 int interface, one_channel; 133 134 /* 135 * The 0648/0649 can be told to identify as a RAID controller. 136 * In this case, we have to fake interface 137 */ 138 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 139 interface = PCIIDE_INTERFACE_SETTABLE(0) | 140 PCIIDE_INTERFACE_SETTABLE(1); 141 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 142 CMD_CONF_DSA1) 143 interface |= PCIIDE_INTERFACE_PCI(0) | 144 PCIIDE_INTERFACE_PCI(1); 145 } else { 146 interface = PCI_INTERFACE(pa->pa_class); 147 } 148 149 sc->wdc_chanarray[channel] = &cp->ata_channel; 150 cp->name = PCIIDE_CHANNEL_NAME(channel); 151 cp->ata_channel.ch_channel = channel; 152 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 153 154 /* 155 * Older CMD64X doesn't have independant channels 156 */ 157 switch (sc->sc_pp->ide_product) { 158 case PCI_PRODUCT_CMDTECH_649: 159 one_channel = 0; 160 break; 161 default: 162 one_channel = 1; 163 break; 164 } 165 166 if (channel > 0 && one_channel) { 167 cp->ata_channel.ch_queue = 168 sc->pciide_channels[0].ata_channel.ch_queue; 169 } else { 170 cp->ata_channel.ch_queue = 171 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 172 } 173 if (cp->ata_channel.ch_queue == NULL) { 174 aprint_error("%s %s channel: " 175 "can't allocate memory for command queue", 176 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 177 return; 178 } 179 cp->ata_channel.ch_ndrive = 2; 180 181 aprint_normal("%s: %s channel %s to %s mode\n", 182 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name, 183 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 184 "configured" : "wired", 185 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 186 "native-PCI" : "compatibility"); 187 188 /* 189 * with a CMD PCI64x, if we get here, the first channel is enabled: 190 * there's no way to disable the first channel without disabling 191 * the whole device 192 */ 193 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 194 aprint_normal("%s: %s channel ignored (disabled)\n", 195 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 196 cp->ata_channel.ch_flags |= ATACH_DISABLED; 197 return; 198 } 199 200 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 201 } 202 203 static int 204 cmd_pci_intr(void *arg) 205 { 206 struct pciide_softc *sc = arg; 207 struct pciide_channel *cp; 208 struct ata_channel *wdc_cp; 209 int i, rv, crv; 210 u_int32_t priirq, secirq; 211 212 rv = 0; 213 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 214 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 215 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 216 cp = &sc->pciide_channels[i]; 217 wdc_cp = &cp->ata_channel; 218 /* If a compat channel skip. */ 219 if (cp->compat) 220 continue; 221 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 222 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 223 crv = wdcintr(wdc_cp); 224 if (crv == 0) { 225 printf("%s:%d: bogus intr\n", 226 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 227 sc->sc_wdcdev.irqack(wdc_cp); 228 } else 229 rv = 1; 230 } 231 } 232 return rv; 233 } 234 235 static void 236 cmd_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 237 { 238 int channel; 239 240 /* 241 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 242 * and base addresses registers can be disabled at 243 * hardware level. In this case, the device is wired 244 * in compat mode and its first channel is always enabled, 245 * but we can't rely on PCI_COMMAND_IO_ENABLE. 246 * In fact, it seems that the first channel of the CMD PCI0640 247 * can't be disabled. 248 */ 249 250 #ifdef PCIIDE_CMD064x_DISABLE 251 if (pciide_chipen(sc, pa) == 0) 252 return; 253 #endif 254 255 aprint_normal("%s: hardware does not support DMA\n", 256 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 257 sc->sc_dma_ok = 0; 258 259 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 260 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 261 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 262 263 wdc_allocate_regs(&sc->sc_wdcdev); 264 265 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 266 channel++) { 267 cmd_channel_map(pa, sc, channel); 268 } 269 } 270 271 static void 272 cmd0643_9_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 273 { 274 int channel; 275 pcireg_t rev = PCI_REVISION(pa->pa_class); 276 277 /* 278 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 279 * and base addresses registers can be disabled at 280 * hardware level. In this case, the device is wired 281 * in compat mode and its first channel is always enabled, 282 * but we can't rely on PCI_COMMAND_IO_ENABLE. 283 * In fact, it seems that the first channel of the CMD PCI0640 284 * can't be disabled. 285 */ 286 287 #ifdef PCIIDE_CMD064x_DISABLE 288 if (pciide_chipen(sc, pa) == 0) 289 return; 290 #endif 291 292 aprint_normal("%s: bus-master DMA support present", 293 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 294 pciide_mapreg_dma(sc, pa); 295 aprint_normal("\n"); 296 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 297 if (sc->sc_dma_ok) { 298 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 299 switch (sc->sc_pp->ide_product) { 300 case PCI_PRODUCT_CMDTECH_649: 301 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 302 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 303 sc->sc_wdcdev.irqack = cmd646_9_irqack; 304 break; 305 case PCI_PRODUCT_CMDTECH_648: 306 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 307 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 308 sc->sc_wdcdev.irqack = cmd646_9_irqack; 309 break; 310 case PCI_PRODUCT_CMDTECH_646: 311 if (rev >= CMD0646U2_REV) { 312 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 313 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 314 } else if (rev >= CMD0646U_REV) { 315 /* 316 * Linux's driver claims that the 646U is broken 317 * with UDMA. Only enable it if we know what we're 318 * doing 319 */ 320 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 321 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 322 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 323 #endif 324 /* explicitly disable UDMA */ 325 pciide_pci_write(sc->sc_pc, sc->sc_tag, 326 CMD_UDMATIM(0), 0); 327 pciide_pci_write(sc->sc_pc, sc->sc_tag, 328 CMD_UDMATIM(1), 0); 329 } 330 sc->sc_wdcdev.irqack = cmd646_9_irqack; 331 break; 332 default: 333 sc->sc_wdcdev.irqack = pciide_irqack; 334 } 335 } 336 337 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 338 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 339 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 340 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 341 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd0643_9_setup_channel; 342 343 ATADEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 344 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 345 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 346 DEBUG_PROBE); 347 348 wdc_allocate_regs(&sc->sc_wdcdev); 349 350 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 351 channel++) 352 cmd_channel_map(pa, sc, channel); 353 354 /* 355 * note - this also makes sure we clear the irq disable and reset 356 * bits 357 */ 358 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 359 ATADEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 360 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 361 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 362 DEBUG_PROBE); 363 } 364 365 static void 366 cmd0643_9_setup_channel(struct ata_channel *chp) 367 { 368 struct ata_drive_datas *drvp; 369 u_int8_t tim; 370 u_int32_t idedma_ctl, udma_reg; 371 int drive, s; 372 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 373 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 374 375 idedma_ctl = 0; 376 /* setup DMA if needed */ 377 pciide_channel_dma_setup(cp); 378 379 for (drive = 0; drive < 2; drive++) { 380 drvp = &chp->ch_drive[drive]; 381 /* If no drive, skip */ 382 if ((drvp->drive_flags & DRIVE) == 0) 383 continue; 384 /* add timing values, setup DMA if needed */ 385 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 386 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 387 if (drvp->drive_flags & DRIVE_UDMA) { 388 /* UltraDMA on a 646U2, 0648 or 0649 */ 389 s = splbio(); 390 drvp->drive_flags &= ~DRIVE_DMA; 391 splx(s); 392 udma_reg = pciide_pci_read(sc->sc_pc, 393 sc->sc_tag, CMD_UDMATIM(chp->ch_channel)); 394 if (drvp->UDMA_mode > 2 && 395 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 396 CMD_BICSR) & 397 CMD_BICSR_80(chp->ch_channel)) == 0) 398 drvp->UDMA_mode = 2; 399 if (drvp->UDMA_mode > 2) 400 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 401 else if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 2) 402 udma_reg |= CMD_UDMATIM_UDMA33(drive); 403 udma_reg |= CMD_UDMATIM_UDMA(drive); 404 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 405 CMD_UDMATIM_TIM_OFF(drive)); 406 udma_reg |= 407 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 408 CMD_UDMATIM_TIM_OFF(drive)); 409 pciide_pci_write(sc->sc_pc, sc->sc_tag, 410 CMD_UDMATIM(chp->ch_channel), udma_reg); 411 } else { 412 /* 413 * use Multiword DMA. 414 * Timings will be used for both PIO and DMA, 415 * so adjust DMA mode if needed 416 * if we have a 0646U2/8/9, turn off UDMA 417 */ 418 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 419 udma_reg = pciide_pci_read(sc->sc_pc, 420 sc->sc_tag, 421 CMD_UDMATIM(chp->ch_channel)); 422 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 423 pciide_pci_write(sc->sc_pc, sc->sc_tag, 424 CMD_UDMATIM(chp->ch_channel), 425 udma_reg); 426 } 427 if (drvp->PIO_mode >= 3 && 428 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 429 drvp->DMA_mode = drvp->PIO_mode - 2; 430 } 431 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 432 } 433 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 434 } 435 pciide_pci_write(sc->sc_pc, sc->sc_tag, 436 CMD_DATA_TIM(chp->ch_channel, drive), tim); 437 } 438 if (idedma_ctl != 0) { 439 /* Add software bits in status register */ 440 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 441 idedma_ctl); 442 } 443 } 444 445 static void 446 cmd646_9_irqack(struct ata_channel *chp) 447 { 448 u_int32_t priirq, secirq; 449 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 450 451 if (chp->ch_channel == 0) { 452 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 453 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 454 } else { 455 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 456 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 457 } 458 pciide_irqack(chp); 459 } 460 461 static void 462 cmd680_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 463 { 464 int channel; 465 466 if (pciide_chipen(sc, pa) == 0) 467 return; 468 469 aprint_normal("%s: bus-master DMA support present", 470 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 471 pciide_mapreg_dma(sc, pa); 472 aprint_normal("\n"); 473 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 474 if (sc->sc_dma_ok) { 475 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 476 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 477 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 478 sc->sc_wdcdev.irqack = pciide_irqack; 479 } 480 481 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 482 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 483 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 484 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 485 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd680_setup_channel; 486 487 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 488 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 489 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 490 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 491 492 wdc_allocate_regs(&sc->sc_wdcdev); 493 494 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 495 channel++) 496 cmd680_channel_map(pa, sc, channel); 497 } 498 499 static void 500 cmd680_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 501 int channel) 502 { 503 struct pciide_channel *cp = &sc->pciide_channels[channel]; 504 bus_size_t cmdsize, ctlsize; 505 int interface, i, reg; 506 static const u_int8_t init_val[] = 507 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 508 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 509 510 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 511 interface = PCIIDE_INTERFACE_SETTABLE(0) | 512 PCIIDE_INTERFACE_SETTABLE(1); 513 interface |= PCIIDE_INTERFACE_PCI(0) | 514 PCIIDE_INTERFACE_PCI(1); 515 } else { 516 interface = PCI_INTERFACE(pa->pa_class); 517 } 518 519 sc->wdc_chanarray[channel] = &cp->ata_channel; 520 cp->name = PCIIDE_CHANNEL_NAME(channel); 521 cp->ata_channel.ch_channel = channel; 522 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 523 524 cp->ata_channel.ch_queue = 525 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 526 if (cp->ata_channel.ch_queue == NULL) { 527 aprint_error("%s %s channel: " 528 "can't allocate memory for command queue", 529 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 530 return; 531 } 532 cp->ata_channel.ch_ndrive = 2; 533 534 /* XXX */ 535 reg = 0xa2 + channel * 16; 536 for (i = 0; i < sizeof(init_val); i++) 537 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 538 539 aprint_normal("%s: %s channel %s to %s mode\n", 540 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name, 541 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 542 "configured" : "wired", 543 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 544 "native-PCI" : "compatibility"); 545 546 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 547 } 548 549 static void 550 cmd680_setup_channel(struct ata_channel *chp) 551 { 552 struct ata_drive_datas *drvp; 553 u_int8_t mode, off, scsc; 554 u_int16_t val; 555 u_int32_t idedma_ctl; 556 int drive, s; 557 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 558 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 559 pci_chipset_tag_t pc = sc->sc_pc; 560 pcitag_t pa = sc->sc_tag; 561 static const u_int8_t udma2_tbl[] = 562 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 563 static const u_int8_t udma_tbl[] = 564 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 565 static const u_int16_t dma_tbl[] = 566 { 0x2208, 0x10c2, 0x10c1 }; 567 static const u_int16_t pio_tbl[] = 568 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 569 570 idedma_ctl = 0; 571 pciide_channel_dma_setup(cp); 572 mode = pciide_pci_read(pc, pa, 0x80 + chp->ch_channel * 4); 573 574 for (drive = 0; drive < 2; drive++) { 575 drvp = &chp->ch_drive[drive]; 576 /* If no drive, skip */ 577 if ((drvp->drive_flags & DRIVE) == 0) 578 continue; 579 mode &= ~(0x03 << (drive * 4)); 580 if (drvp->drive_flags & DRIVE_UDMA) { 581 s = splbio(); 582 drvp->drive_flags &= ~DRIVE_DMA; 583 splx(s); 584 off = 0xa0 + chp->ch_channel * 16; 585 if (drvp->UDMA_mode > 2 && 586 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 587 drvp->UDMA_mode = 2; 588 scsc = pciide_pci_read(pc, pa, 0x8a); 589 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 590 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 591 scsc = pciide_pci_read(pc, pa, 0x8a); 592 if ((scsc & 0x30) == 0) 593 drvp->UDMA_mode = 5; 594 } 595 mode |= 0x03 << (drive * 4); 596 off = 0xac + chp->ch_channel * 16 + drive * 2; 597 val = pciide_pci_read(pc, pa, off) & ~0x3f; 598 if (scsc & 0x30) 599 val |= udma2_tbl[drvp->UDMA_mode]; 600 else 601 val |= udma_tbl[drvp->UDMA_mode]; 602 pciide_pci_write(pc, pa, off, val); 603 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 604 } else if (drvp->drive_flags & DRIVE_DMA) { 605 mode |= 0x02 << (drive * 4); 606 off = 0xa8 + chp->ch_channel * 16 + drive * 2; 607 val = dma_tbl[drvp->DMA_mode]; 608 pciide_pci_write(pc, pa, off, val & 0xff); 609 pciide_pci_write(pc, pa, off+1, val >> 8); 610 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 611 } else { 612 mode |= 0x01 << (drive * 4); 613 off = 0xa4 + chp->ch_channel * 16 + drive * 2; 614 val = pio_tbl[drvp->PIO_mode]; 615 pciide_pci_write(pc, pa, off, val & 0xff); 616 pciide_pci_write(pc, pa, off+1, val >> 8); 617 } 618 } 619 620 pciide_pci_write(pc, pa, 0x80 + chp->ch_channel * 4, mode); 621 if (idedma_ctl != 0) { 622 /* Add software bits in status register */ 623 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 624 idedma_ctl); 625 } 626 } 627
Indexes created Wed Oct 01 19:09:53 GMT 2025