cmdide.c revision 1.19.2.3
1 /* $NetBSD: cmdide.c,v 1.19.2.3 2007/02/26 09:10:23 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: cmdide.c,v 1.19.2.3 2007/02/26 09:10:23 yamt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_cmd_reg.h> 44 45 46 static int cmdide_match(struct device *, struct cfdata *, void *); 47 static void cmdide_attach(struct device *, struct device *, void *); 48 49 CFATTACH_DECL(cmdide, sizeof(struct pciide_softc), 50 cmdide_match, cmdide_attach, NULL, NULL); 51 52 static void cmd_chip_map(struct pciide_softc*, struct pci_attach_args*); 53 static void cmd0643_9_chip_map(struct pciide_softc*, struct pci_attach_args*); 54 static void cmd0643_9_setup_channel(struct ata_channel*); 55 static void cmd_channel_map(struct pci_attach_args *, struct pciide_softc *, 56 int); 57 static int cmd_pci_intr(void *); 58 static void cmd646_9_irqack(struct ata_channel *); 59 static void cmd680_chip_map(struct pciide_softc*, struct pci_attach_args*); 60 static void cmd680_setup_channel(struct ata_channel*); 61 static void cmd680_channel_map(struct pci_attach_args *, struct pciide_softc *, 62 int); 63 64 static const struct pciide_product_desc pciide_cmd_products[] = { 65 { PCI_PRODUCT_CMDTECH_640, 66 0, 67 "CMD Technology PCI0640", 68 cmd_chip_map 69 }, 70 { PCI_PRODUCT_CMDTECH_643, 71 0, 72 "CMD Technology PCI0643", 73 cmd0643_9_chip_map, 74 }, 75 { PCI_PRODUCT_CMDTECH_646, 76 0, 77 "CMD Technology PCI0646", 78 cmd0643_9_chip_map, 79 }, 80 { PCI_PRODUCT_CMDTECH_648, 81 0, 82 "CMD Technology PCI0648", 83 cmd0643_9_chip_map, 84 }, 85 { PCI_PRODUCT_CMDTECH_649, 86 0, 87 "CMD Technology PCI0649", 88 cmd0643_9_chip_map, 89 }, 90 { PCI_PRODUCT_CMDTECH_680, 91 0, 92 "Silicon Image 0680", 93 cmd680_chip_map, 94 }, 95 { 0, 96 0, 97 NULL, 98 NULL 99 } 100 }; 101 102 static int 103 cmdide_match(struct device *parent, struct cfdata *match, 104 void *aux) 105 { 106 struct pci_attach_args *pa = aux; 107 108 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 109 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 110 return (2); 111 } 112 return (0); 113 } 114 115 static void 116 cmdide_attach(struct device *parent, struct device *self, void *aux) 117 { 118 struct pci_attach_args *pa = aux; 119 struct pciide_softc *sc = (struct pciide_softc *)self; 120 121 pciide_common_attach(sc, pa, 122 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 123 124 } 125 126 static void 127 cmd_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 128 int channel) 129 { 130 struct pciide_channel *cp = &sc->pciide_channels[channel]; 131 bus_size_t cmdsize, ctlsize; 132 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 133 int interface, one_channel; 134 135 /* 136 * The 0648/0649 can be told to identify as a RAID controller. 137 * In this case, we have to fake interface 138 */ 139 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 140 interface = PCIIDE_INTERFACE_SETTABLE(0) | 141 PCIIDE_INTERFACE_SETTABLE(1); 142 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 143 CMD_CONF_DSA1) 144 interface |= PCIIDE_INTERFACE_PCI(0) | 145 PCIIDE_INTERFACE_PCI(1); 146 } else { 147 interface = PCI_INTERFACE(pa->pa_class); 148 } 149 150 sc->wdc_chanarray[channel] = &cp->ata_channel; 151 cp->name = PCIIDE_CHANNEL_NAME(channel); 152 cp->ata_channel.ch_channel = channel; 153 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 154 155 /* 156 * Older CMD64X doesn't have independent channels 157 */ 158 switch (sc->sc_pp->ide_product) { 159 case PCI_PRODUCT_CMDTECH_649: 160 one_channel = 0; 161 break; 162 default: 163 one_channel = 1; 164 break; 165 } 166 167 if (channel > 0 && one_channel) { 168 cp->ata_channel.ch_queue = 169 sc->pciide_channels[0].ata_channel.ch_queue; 170 } else { 171 cp->ata_channel.ch_queue = 172 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 173 } 174 if (cp->ata_channel.ch_queue == NULL) { 175 aprint_error("%s %s channel: " 176 "can't allocate memory for command queue", 177 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 178 return; 179 } 180 cp->ata_channel.ch_ndrive = 2; 181 182 aprint_normal("%s: %s channel %s to %s mode\n", 183 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name, 184 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 185 "configured" : "wired", 186 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 187 "native-PCI" : "compatibility"); 188 189 /* 190 * with a CMD PCI64x, if we get here, the first channel is enabled: 191 * there's no way to disable the first channel without disabling 192 * the whole device 193 */ 194 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 195 aprint_normal("%s: %s channel ignored (disabled)\n", 196 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 197 cp->ata_channel.ch_flags |= ATACH_DISABLED; 198 return; 199 } 200 201 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 202 } 203 204 static int 205 cmd_pci_intr(void *arg) 206 { 207 struct pciide_softc *sc = arg; 208 struct pciide_channel *cp; 209 struct ata_channel *wdc_cp; 210 int i, rv, crv; 211 u_int32_t priirq, secirq; 212 213 rv = 0; 214 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 215 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 216 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 217 cp = &sc->pciide_channels[i]; 218 wdc_cp = &cp->ata_channel; 219 /* If a compat channel skip. */ 220 if (cp->compat) 221 continue; 222 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 223 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 224 crv = wdcintr(wdc_cp); 225 if (crv == 0) { 226 printf("%s:%d: bogus intr\n", 227 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 228 sc->sc_wdcdev.irqack(wdc_cp); 229 } else 230 rv = 1; 231 } 232 } 233 return rv; 234 } 235 236 static void 237 cmd_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 238 { 239 int channel; 240 241 /* 242 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 243 * and base addresses registers can be disabled at 244 * hardware level. In this case, the device is wired 245 * in compat mode and its first channel is always enabled, 246 * but we can't rely on PCI_COMMAND_IO_ENABLE. 247 * In fact, it seems that the first channel of the CMD PCI0640 248 * can't be disabled. 249 */ 250 251 #ifdef PCIIDE_CMD064x_DISABLE 252 if (pciide_chipen(sc, pa) == 0) 253 return; 254 #endif 255 256 aprint_normal("%s: hardware does not support DMA\n", 257 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 258 sc->sc_dma_ok = 0; 259 260 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 261 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 262 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 263 264 wdc_allocate_regs(&sc->sc_wdcdev); 265 266 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 267 channel++) { 268 cmd_channel_map(pa, sc, channel); 269 } 270 } 271 272 static void 273 cmd0643_9_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 274 { 275 int channel; 276 pcireg_t rev = PCI_REVISION(pa->pa_class); 277 278 /* 279 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 280 * and base addresses registers can be disabled at 281 * hardware level. In this case, the device is wired 282 * in compat mode and its first channel is always enabled, 283 * but we can't rely on PCI_COMMAND_IO_ENABLE. 284 * In fact, it seems that the first channel of the CMD PCI0640 285 * can't be disabled. 286 */ 287 288 #ifdef PCIIDE_CMD064x_DISABLE 289 if (pciide_chipen(sc, pa) == 0) 290 return; 291 #endif 292 293 aprint_verbose("%s: bus-master DMA support present", 294 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 295 pciide_mapreg_dma(sc, pa); 296 aprint_verbose("\n"); 297 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 298 if (sc->sc_dma_ok) { 299 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 300 switch (sc->sc_pp->ide_product) { 301 case PCI_PRODUCT_CMDTECH_649: 302 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 303 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 304 sc->sc_wdcdev.irqack = cmd646_9_irqack; 305 break; 306 case PCI_PRODUCT_CMDTECH_648: 307 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 308 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 309 sc->sc_wdcdev.irqack = cmd646_9_irqack; 310 break; 311 case PCI_PRODUCT_CMDTECH_646: 312 if (rev >= CMD0646U2_REV) { 313 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 314 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 315 } else if (rev >= CMD0646U_REV) { 316 /* 317 * Linux's driver claims that the 646U is broken 318 * with UDMA. Only enable it if we know what we're 319 * doing 320 */ 321 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 322 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 323 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 324 #endif 325 /* explicitly disable UDMA */ 326 pciide_pci_write(sc->sc_pc, sc->sc_tag, 327 CMD_UDMATIM(0), 0); 328 pciide_pci_write(sc->sc_pc, sc->sc_tag, 329 CMD_UDMATIM(1), 0); 330 } 331 sc->sc_wdcdev.irqack = cmd646_9_irqack; 332 break; 333 default: 334 sc->sc_wdcdev.irqack = pciide_irqack; 335 } 336 } 337 338 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 339 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 340 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 341 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 342 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd0643_9_setup_channel; 343 344 ATADEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 345 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 346 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 347 DEBUG_PROBE); 348 349 wdc_allocate_regs(&sc->sc_wdcdev); 350 351 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 352 channel++) 353 cmd_channel_map(pa, sc, channel); 354 355 /* 356 * note - this also makes sure we clear the irq disable and reset 357 * bits 358 */ 359 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 360 ATADEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 361 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 362 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 363 DEBUG_PROBE); 364 } 365 366 static void 367 cmd0643_9_setup_channel(struct ata_channel *chp) 368 { 369 struct ata_drive_datas *drvp; 370 u_int8_t tim; 371 u_int32_t idedma_ctl, udma_reg; 372 int drive, s; 373 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 374 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 375 376 idedma_ctl = 0; 377 /* setup DMA if needed */ 378 pciide_channel_dma_setup(cp); 379 380 for (drive = 0; drive < 2; drive++) { 381 drvp = &chp->ch_drive[drive]; 382 /* If no drive, skip */ 383 if ((drvp->drive_flags & DRIVE) == 0) 384 continue; 385 /* add timing values, setup DMA if needed */ 386 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 387 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 388 if (drvp->drive_flags & DRIVE_UDMA) { 389 /* UltraDMA on a 646U2, 0648 or 0649 */ 390 s = splbio(); 391 drvp->drive_flags &= ~DRIVE_DMA; 392 splx(s); 393 udma_reg = pciide_pci_read(sc->sc_pc, 394 sc->sc_tag, CMD_UDMATIM(chp->ch_channel)); 395 if (drvp->UDMA_mode > 2 && 396 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 397 CMD_BICSR) & 398 CMD_BICSR_80(chp->ch_channel)) == 0) 399 drvp->UDMA_mode = 2; 400 if (drvp->UDMA_mode > 2) 401 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 402 else if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 2) 403 udma_reg |= CMD_UDMATIM_UDMA33(drive); 404 udma_reg |= CMD_UDMATIM_UDMA(drive); 405 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 406 CMD_UDMATIM_TIM_OFF(drive)); 407 udma_reg |= 408 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 409 CMD_UDMATIM_TIM_OFF(drive)); 410 pciide_pci_write(sc->sc_pc, sc->sc_tag, 411 CMD_UDMATIM(chp->ch_channel), udma_reg); 412 } else { 413 /* 414 * use Multiword DMA. 415 * Timings will be used for both PIO and DMA, 416 * so adjust DMA mode if needed 417 * if we have a 0646U2/8/9, turn off UDMA 418 */ 419 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 420 udma_reg = pciide_pci_read(sc->sc_pc, 421 sc->sc_tag, 422 CMD_UDMATIM(chp->ch_channel)); 423 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 424 pciide_pci_write(sc->sc_pc, sc->sc_tag, 425 CMD_UDMATIM(chp->ch_channel), 426 udma_reg); 427 } 428 if (drvp->PIO_mode >= 3 && 429 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 430 drvp->DMA_mode = drvp->PIO_mode - 2; 431 } 432 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 433 } 434 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 435 } 436 pciide_pci_write(sc->sc_pc, sc->sc_tag, 437 CMD_DATA_TIM(chp->ch_channel, drive), tim); 438 } 439 if (idedma_ctl != 0) { 440 /* Add software bits in status register */ 441 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 442 idedma_ctl); 443 } 444 } 445 446 static void 447 cmd646_9_irqack(struct ata_channel *chp) 448 { 449 u_int32_t priirq, secirq; 450 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 451 452 if (chp->ch_channel == 0) { 453 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 454 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 455 } else { 456 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 457 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 458 } 459 pciide_irqack(chp); 460 } 461 462 static void 463 cmd680_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 464 { 465 int channel; 466 467 if (pciide_chipen(sc, pa) == 0) 468 return; 469 470 aprint_verbose("%s: bus-master DMA support present", 471 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 472 pciide_mapreg_dma(sc, pa); 473 aprint_verbose("\n"); 474 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 475 if (sc->sc_dma_ok) { 476 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 477 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 478 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 479 sc->sc_wdcdev.irqack = pciide_irqack; 480 } 481 482 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 483 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 484 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 485 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 486 sc->sc_wdcdev.sc_atac.atac_set_modes = cmd680_setup_channel; 487 488 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 489 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 490 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 491 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 492 493 wdc_allocate_regs(&sc->sc_wdcdev); 494 495 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 496 channel++) 497 cmd680_channel_map(pa, sc, channel); 498 } 499 500 static void 501 cmd680_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 502 int channel) 503 { 504 struct pciide_channel *cp = &sc->pciide_channels[channel]; 505 bus_size_t cmdsize, ctlsize; 506 int interface, i, reg; 507 static const u_int8_t init_val[] = 508 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 509 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 510 511 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 512 interface = PCIIDE_INTERFACE_SETTABLE(0) | 513 PCIIDE_INTERFACE_SETTABLE(1); 514 interface |= PCIIDE_INTERFACE_PCI(0) | 515 PCIIDE_INTERFACE_PCI(1); 516 } else { 517 interface = PCI_INTERFACE(pa->pa_class); 518 } 519 520 sc->wdc_chanarray[channel] = &cp->ata_channel; 521 cp->name = PCIIDE_CHANNEL_NAME(channel); 522 cp->ata_channel.ch_channel = channel; 523 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 524 525 cp->ata_channel.ch_queue = 526 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 527 if (cp->ata_channel.ch_queue == NULL) { 528 aprint_error("%s %s channel: " 529 "can't allocate memory for command queue", 530 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 531 return; 532 } 533 cp->ata_channel.ch_ndrive = 2; 534 535 /* XXX */ 536 reg = 0xa2 + channel * 16; 537 for (i = 0; i < sizeof(init_val); i++) 538 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 539 540 aprint_normal("%s: %s channel %s to %s mode\n", 541 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name, 542 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 543 "configured" : "wired", 544 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 545 "native-PCI" : "compatibility"); 546 547 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 548 } 549 550 static void 551 cmd680_setup_channel(struct ata_channel *chp) 552 { 553 struct ata_drive_datas *drvp; 554 u_int8_t mode, off, scsc; 555 u_int16_t val; 556 u_int32_t idedma_ctl; 557 int drive, s; 558 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 559 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 560 pci_chipset_tag_t pc = sc->sc_pc; 561 pcitag_t pa = sc->sc_tag; 562 static const u_int8_t udma2_tbl[] = 563 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 564 static const u_int8_t udma_tbl[] = 565 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 566 static const u_int16_t dma_tbl[] = 567 { 0x2208, 0x10c2, 0x10c1 }; 568 static const u_int16_t pio_tbl[] = 569 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 570 571 idedma_ctl = 0; 572 pciide_channel_dma_setup(cp); 573 mode = pciide_pci_read(pc, pa, 0x80 + chp->ch_channel * 4); 574 575 for (drive = 0; drive < 2; drive++) { 576 drvp = &chp->ch_drive[drive]; 577 /* If no drive, skip */ 578 if ((drvp->drive_flags & DRIVE) == 0) 579 continue; 580 mode &= ~(0x03 << (drive * 4)); 581 if (drvp->drive_flags & DRIVE_UDMA) { 582 s = splbio(); 583 drvp->drive_flags &= ~DRIVE_DMA; 584 splx(s); 585 off = 0xa0 + chp->ch_channel * 16; 586 if (drvp->UDMA_mode > 2 && 587 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 588 drvp->UDMA_mode = 2; 589 scsc = pciide_pci_read(pc, pa, 0x8a); 590 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 591 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 592 scsc = pciide_pci_read(pc, pa, 0x8a); 593 if ((scsc & 0x30) == 0) 594 drvp->UDMA_mode = 5; 595 } 596 mode |= 0x03 << (drive * 4); 597 off = 0xac + chp->ch_channel * 16 + drive * 2; 598 val = pciide_pci_read(pc, pa, off) & ~0x3f; 599 if (scsc & 0x30) 600 val |= udma2_tbl[drvp->UDMA_mode]; 601 else 602 val |= udma_tbl[drvp->UDMA_mode]; 603 pciide_pci_write(pc, pa, off, val); 604 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 605 } else if (drvp->drive_flags & DRIVE_DMA) { 606 mode |= 0x02 << (drive * 4); 607 off = 0xa8 + chp->ch_channel * 16 + drive * 2; 608 val = dma_tbl[drvp->DMA_mode]; 609 pciide_pci_write(pc, pa, off, val & 0xff); 610 pciide_pci_write(pc, pa, off+1, val >> 8); 611 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 612 } else { 613 mode |= 0x01 << (drive * 4); 614 off = 0xa4 + chp->ch_channel * 16 + drive * 2; 615 val = pio_tbl[drvp->PIO_mode]; 616 pciide_pci_write(pc, pa, off, val & 0xff); 617 pciide_pci_write(pc, pa, off+1, val >> 8); 618 } 619 } 620 621 pciide_pci_write(pc, pa, 0x80 + chp->ch_channel * 4, mode); 622 if (idedma_ctl != 0) { 623 /* Add software bits in status register */ 624 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 625 idedma_ctl); 626 } 627 } 628
Indexes created Wed Oct 01 19:09:53 GMT 2025