cmdide.c revision 1.2
1 /* $NetBSD: cmdide.c,v 1.2 2003/10/11 17:40:15 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 36 #include <dev/pci/pcivar.h> 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pciidereg.h> 39 #include <dev/pci/pciidevar.h> 40 #include <dev/pci/pciide_cmd_reg.h> 41 #include <dev/pci/pciide_sii3112_reg.h> 42 43 44 static int cmdide_match(struct device *, struct cfdata *, void *); 45 static void cmdide_attach(struct device *, struct device *, void *); 46 47 CFATTACH_DECL(cmdide, sizeof(struct pciide_softc), 48 cmdide_match, cmdide_attach, NULL, NULL); 49 50 static void cmd_chip_map(struct pciide_softc*, struct pci_attach_args*); 51 static void cmd0643_9_chip_map(struct pciide_softc*, struct pci_attach_args*); 52 static void cmd0643_9_setup_channel(struct channel_softc*); 53 static void cmd_channel_map(struct pci_attach_args *, struct pciide_softc *, 54 int); 55 static int cmd_pci_intr(void *); 56 static void cmd646_9_irqack(struct channel_softc *); 57 static void cmd680_chip_map(struct pciide_softc*, struct pci_attach_args*); 58 static void cmd680_setup_channel(struct channel_softc*); 59 static void cmd680_channel_map(struct pci_attach_args *, struct pciide_softc *, 60 int); 61 62 static void cmd3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 63 static void cmd3112_setup_channel(struct channel_softc*); 64 65 static const struct pciide_product_desc pciide_cmd_products[] = { 66 { PCI_PRODUCT_CMDTECH_640, 67 0, 68 "CMD Technology PCI0640", 69 cmd_chip_map 70 }, 71 { PCI_PRODUCT_CMDTECH_643, 72 0, 73 "CMD Technology PCI0643", 74 cmd0643_9_chip_map, 75 }, 76 { PCI_PRODUCT_CMDTECH_646, 77 0, 78 "CMD Technology PCI0646", 79 cmd0643_9_chip_map, 80 }, 81 { PCI_PRODUCT_CMDTECH_648, 82 IDE_PCI_CLASS_OVERRIDE, 83 "CMD Technology PCI0648", 84 cmd0643_9_chip_map, 85 }, 86 { PCI_PRODUCT_CMDTECH_649, 87 IDE_PCI_CLASS_OVERRIDE, 88 "CMD Technology PCI0649", 89 cmd0643_9_chip_map, 90 }, 91 { PCI_PRODUCT_CMDTECH_680, 92 IDE_PCI_CLASS_OVERRIDE, 93 "Silicon Image 0680", 94 cmd680_chip_map, 95 }, 96 { PCI_PRODUCT_CMDTECH_3112, 97 IDE_PCI_CLASS_OVERRIDE, 98 "Silicon Image SATALink 3112", 99 cmd3112_chip_map, 100 }, 101 { 0, 102 0, 103 NULL, 104 NULL 105 } 106 }; 107 108 static int 109 cmdide_match(struct device *parent, struct cfdata *match, void *aux) 110 { 111 struct pci_attach_args *pa = aux; 112 113 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 114 if (pciide_lookup_product(pa->pa_id, pciide_cmd_products)) 115 return (2); 116 } 117 return (0); 118 } 119 120 static void 121 cmdide_attach(struct device *parent, struct device *self, void *aux) 122 { 123 struct pci_attach_args *pa = aux; 124 struct pciide_softc *sc = (struct pciide_softc *)self; 125 126 pciide_common_attach(sc, pa, 127 pciide_lookup_product(pa->pa_id, pciide_cmd_products)); 128 129 } 130 131 static void 132 cmd_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 133 int channel) 134 { 135 struct pciide_channel *cp = &sc->pciide_channels[channel]; 136 bus_size_t cmdsize, ctlsize; 137 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 138 int interface, one_channel; 139 140 /* 141 * The 0648/0649 can be told to identify as a RAID controller. 142 * In this case, we have to fake interface 143 */ 144 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 145 interface = PCIIDE_INTERFACE_SETTABLE(0) | 146 PCIIDE_INTERFACE_SETTABLE(1); 147 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 148 CMD_CONF_DSA1) 149 interface |= PCIIDE_INTERFACE_PCI(0) | 150 PCIIDE_INTERFACE_PCI(1); 151 } else { 152 interface = PCI_INTERFACE(pa->pa_class); 153 } 154 155 sc->wdc_chanarray[channel] = &cp->wdc_channel; 156 cp->name = PCIIDE_CHANNEL_NAME(channel); 157 cp->wdc_channel.channel = channel; 158 cp->wdc_channel.wdc = &sc->sc_wdcdev; 159 160 /* 161 * Older CMD64X doesn't have independant channels 162 */ 163 switch (sc->sc_pp->ide_product) { 164 case PCI_PRODUCT_CMDTECH_649: 165 one_channel = 0; 166 break; 167 default: 168 one_channel = 1; 169 break; 170 } 171 172 if (channel > 0 && one_channel) { 173 cp->wdc_channel.ch_queue = 174 sc->pciide_channels[0].wdc_channel.ch_queue; 175 } else { 176 cp->wdc_channel.ch_queue = 177 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 178 } 179 if (cp->wdc_channel.ch_queue == NULL) { 180 aprint_error("%s %s channel: " 181 "can't allocate memory for command queue", 182 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 183 return; 184 } 185 186 aprint_normal("%s: %s channel %s to %s mode\n", 187 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 188 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 189 "configured" : "wired", 190 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 191 "native-PCI" : "compatibility"); 192 193 /* 194 * with a CMD PCI64x, if we get here, the first channel is enabled: 195 * there's no way to disable the first channel without disabling 196 * the whole device 197 */ 198 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 199 aprint_normal("%s: %s channel ignored (disabled)\n", 200 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 201 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 202 return; 203 } 204 205 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 206 } 207 208 static int 209 cmd_pci_intr(void *arg) 210 { 211 struct pciide_softc *sc = arg; 212 struct pciide_channel *cp; 213 struct channel_softc *wdc_cp; 214 int i, rv, crv; 215 u_int32_t priirq, secirq; 216 217 rv = 0; 218 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 219 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 220 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 221 cp = &sc->pciide_channels[i]; 222 wdc_cp = &cp->wdc_channel; 223 /* If a compat channel skip. */ 224 if (cp->compat) 225 continue; 226 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 227 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 228 crv = wdcintr(wdc_cp); 229 if (crv == 0) 230 printf("%s:%d: bogus intr\n", 231 sc->sc_wdcdev.sc_dev.dv_xname, i); 232 else 233 rv = 1; 234 } 235 } 236 return rv; 237 } 238 239 static void 240 cmd_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 241 { 242 int channel; 243 244 /* 245 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 246 * and base adresses registers can be disabled at 247 * hardware level. In this case, the device is wired 248 * in compat mode and its first channel is always enabled, 249 * but we can't rely on PCI_COMMAND_IO_ENABLE. 250 * In fact, it seems that the first channel of the CMD PCI0640 251 * can't be disabled. 252 */ 253 254 #ifdef PCIIDE_CMD064x_DISABLE 255 if (pciide_chipen(sc, pa) == 0) 256 return; 257 #endif 258 259 aprint_normal("%s: hardware does not support DMA\n", 260 sc->sc_wdcdev.sc_dev.dv_xname); 261 sc->sc_dma_ok = 0; 262 263 sc->sc_wdcdev.channels = sc->wdc_chanarray; 264 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 265 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 266 267 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 268 cmd_channel_map(pa, sc, channel); 269 } 270 } 271 272 static void 273 cmd0643_9_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 274 { 275 struct pciide_channel *cp; 276 int channel; 277 pcireg_t rev = PCI_REVISION(pa->pa_class); 278 279 /* 280 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 281 * and base adresses registers can be disabled at 282 * hardware level. In this case, the device is wired 283 * in compat mode and its first channel is always enabled, 284 * but we can't rely on PCI_COMMAND_IO_ENABLE. 285 * In fact, it seems that the first channel of the CMD PCI0640 286 * can't be disabled. 287 */ 288 289 #ifdef PCIIDE_CMD064x_DISABLE 290 if (pciide_chipen(sc, pa) == 0) 291 return; 292 #endif 293 294 aprint_normal("%s: bus-master DMA support present", 295 sc->sc_wdcdev.sc_dev.dv_xname); 296 pciide_mapreg_dma(sc, pa); 297 aprint_normal("\n"); 298 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 299 WDC_CAPABILITY_MODE; 300 if (sc->sc_dma_ok) { 301 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 302 switch (sc->sc_pp->ide_product) { 303 case PCI_PRODUCT_CMDTECH_649: 304 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 305 sc->sc_wdcdev.UDMA_cap = 5; 306 sc->sc_wdcdev.irqack = cmd646_9_irqack; 307 break; 308 case PCI_PRODUCT_CMDTECH_648: 309 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 310 sc->sc_wdcdev.UDMA_cap = 4; 311 sc->sc_wdcdev.irqack = cmd646_9_irqack; 312 break; 313 case PCI_PRODUCT_CMDTECH_646: 314 if (rev >= CMD0646U2_REV) { 315 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 316 sc->sc_wdcdev.UDMA_cap = 2; 317 } else if (rev >= CMD0646U_REV) { 318 /* 319 * Linux's driver claims that the 646U is broken 320 * with UDMA. Only enable it if we know what we're 321 * doing 322 */ 323 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 324 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 325 sc->sc_wdcdev.UDMA_cap = 2; 326 #endif 327 /* explicitly disable UDMA */ 328 pciide_pci_write(sc->sc_pc, sc->sc_tag, 329 CMD_UDMATIM(0), 0); 330 pciide_pci_write(sc->sc_pc, sc->sc_tag, 331 CMD_UDMATIM(1), 0); 332 } 333 sc->sc_wdcdev.irqack = cmd646_9_irqack; 334 break; 335 default: 336 sc->sc_wdcdev.irqack = pciide_irqack; 337 } 338 } 339 340 sc->sc_wdcdev.channels = sc->wdc_chanarray; 341 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 342 sc->sc_wdcdev.PIO_cap = 4; 343 sc->sc_wdcdev.DMA_cap = 2; 344 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 345 346 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 347 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 348 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 349 DEBUG_PROBE); 350 351 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 352 cp = &sc->pciide_channels[channel]; 353 cmd_channel_map(pa, sc, channel); 354 } 355 /* 356 * note - this also makes sure we clear the irq disable and reset 357 * bits 358 */ 359 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 360 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 361 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 362 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 363 DEBUG_PROBE); 364 } 365 366 static void 367 cmd0643_9_setup_channel(struct channel_softc *chp) 368 { 369 struct ata_drive_datas *drvp; 370 u_int8_t tim; 371 u_int32_t idedma_ctl, udma_reg; 372 int drive; 373 struct pciide_channel *cp = (struct pciide_channel*)chp; 374 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 375 376 idedma_ctl = 0; 377 /* setup DMA if needed */ 378 pciide_channel_dma_setup(cp); 379 380 for (drive = 0; drive < 2; drive++) { 381 drvp = &chp->ch_drive[drive]; 382 /* If no drive, skip */ 383 if ((drvp->drive_flags & DRIVE) == 0) 384 continue; 385 /* add timing values, setup DMA if needed */ 386 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 387 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 388 if (drvp->drive_flags & DRIVE_UDMA) { 389 /* UltraDMA on a 646U2, 0648 or 0649 */ 390 drvp->drive_flags &= ~DRIVE_DMA; 391 udma_reg = pciide_pci_read(sc->sc_pc, 392 sc->sc_tag, CMD_UDMATIM(chp->channel)); 393 if (drvp->UDMA_mode > 2 && 394 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 395 CMD_BICSR) & 396 CMD_BICSR_80(chp->channel)) == 0) 397 drvp->UDMA_mode = 2; 398 if (drvp->UDMA_mode > 2) 399 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 400 else if (sc->sc_wdcdev.UDMA_cap > 2) 401 udma_reg |= CMD_UDMATIM_UDMA33(drive); 402 udma_reg |= CMD_UDMATIM_UDMA(drive); 403 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 404 CMD_UDMATIM_TIM_OFF(drive)); 405 udma_reg |= 406 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 407 CMD_UDMATIM_TIM_OFF(drive)); 408 pciide_pci_write(sc->sc_pc, sc->sc_tag, 409 CMD_UDMATIM(chp->channel), udma_reg); 410 } else { 411 /* 412 * use Multiword DMA. 413 * Timings will be used for both PIO and DMA, 414 * so adjust DMA mode if needed 415 * if we have a 0646U2/8/9, turn off UDMA 416 */ 417 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 418 udma_reg = pciide_pci_read(sc->sc_pc, 419 sc->sc_tag, 420 CMD_UDMATIM(chp->channel)); 421 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 422 pciide_pci_write(sc->sc_pc, sc->sc_tag, 423 CMD_UDMATIM(chp->channel), 424 udma_reg); 425 } 426 if (drvp->PIO_mode >= 3 && 427 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 428 drvp->DMA_mode = drvp->PIO_mode - 2; 429 } 430 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 431 } 432 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 433 } 434 pciide_pci_write(sc->sc_pc, sc->sc_tag, 435 CMD_DATA_TIM(chp->channel, drive), tim); 436 } 437 if (idedma_ctl != 0) { 438 /* Add software bits in status register */ 439 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 440 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 441 idedma_ctl); 442 } 443 } 444 445 static void 446 cmd646_9_irqack(struct channel_softc *chp) 447 { 448 u_int32_t priirq, secirq; 449 struct pciide_channel *cp = (struct pciide_channel*)chp; 450 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 451 452 if (chp->channel == 0) { 453 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 454 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 455 } else { 456 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 457 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 458 } 459 pciide_irqack(chp); 460 } 461 462 static void 463 cmd680_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 464 { 465 struct pciide_channel *cp; 466 int channel; 467 468 if (pciide_chipen(sc, pa) == 0) 469 return; 470 471 aprint_normal("%s: bus-master DMA support present", 472 sc->sc_wdcdev.sc_dev.dv_xname); 473 pciide_mapreg_dma(sc, pa); 474 aprint_normal("\n"); 475 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 476 WDC_CAPABILITY_MODE; 477 if (sc->sc_dma_ok) { 478 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 479 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 480 sc->sc_wdcdev.UDMA_cap = 6; 481 sc->sc_wdcdev.irqack = pciide_irqack; 482 } 483 484 sc->sc_wdcdev.channels = sc->wdc_chanarray; 485 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 486 sc->sc_wdcdev.PIO_cap = 4; 487 sc->sc_wdcdev.DMA_cap = 2; 488 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 489 490 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 491 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 492 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 493 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 494 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 495 cp = &sc->pciide_channels[channel]; 496 cmd680_channel_map(pa, sc, channel); 497 } 498 } 499 500 static void 501 cmd680_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc, 502 int channel) 503 { 504 struct pciide_channel *cp = &sc->pciide_channels[channel]; 505 bus_size_t cmdsize, ctlsize; 506 int interface, i, reg; 507 static const u_int8_t init_val[] = 508 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 509 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 510 511 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 512 interface = PCIIDE_INTERFACE_SETTABLE(0) | 513 PCIIDE_INTERFACE_SETTABLE(1); 514 interface |= PCIIDE_INTERFACE_PCI(0) | 515 PCIIDE_INTERFACE_PCI(1); 516 } else { 517 interface = PCI_INTERFACE(pa->pa_class); 518 } 519 520 sc->wdc_chanarray[channel] = &cp->wdc_channel; 521 cp->name = PCIIDE_CHANNEL_NAME(channel); 522 cp->wdc_channel.channel = channel; 523 cp->wdc_channel.wdc = &sc->sc_wdcdev; 524 525 cp->wdc_channel.ch_queue = 526 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 527 if (cp->wdc_channel.ch_queue == NULL) { 528 aprint_error("%s %s channel: " 529 "can't allocate memory for command queue", 530 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 531 return; 532 } 533 534 /* XXX */ 535 reg = 0xa2 + channel * 16; 536 for (i = 0; i < sizeof(init_val); i++) 537 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 538 539 aprint_normal("%s: %s channel %s to %s mode\n", 540 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 541 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 542 "configured" : "wired", 543 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 544 "native-PCI" : "compatibility"); 545 546 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 547 } 548 549 static void 550 cmd680_setup_channel(struct channel_softc *chp) 551 { 552 struct ata_drive_datas *drvp; 553 u_int8_t mode, off, scsc; 554 u_int16_t val; 555 u_int32_t idedma_ctl; 556 int drive; 557 struct pciide_channel *cp = (struct pciide_channel*)chp; 558 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 559 pci_chipset_tag_t pc = sc->sc_pc; 560 pcitag_t pa = sc->sc_tag; 561 static const u_int8_t udma2_tbl[] = 562 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 563 static const u_int8_t udma_tbl[] = 564 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 565 static const u_int16_t dma_tbl[] = 566 { 0x2208, 0x10c2, 0x10c1 }; 567 static const u_int16_t pio_tbl[] = 568 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 569 570 idedma_ctl = 0; 571 pciide_channel_dma_setup(cp); 572 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 573 574 for (drive = 0; drive < 2; drive++) { 575 drvp = &chp->ch_drive[drive]; 576 /* If no drive, skip */ 577 if ((drvp->drive_flags & DRIVE) == 0) 578 continue; 579 mode &= ~(0x03 << (drive * 4)); 580 if (drvp->drive_flags & DRIVE_UDMA) { 581 drvp->drive_flags &= ~DRIVE_DMA; 582 off = 0xa0 + chp->channel * 16; 583 if (drvp->UDMA_mode > 2 && 584 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 585 drvp->UDMA_mode = 2; 586 scsc = pciide_pci_read(pc, pa, 0x8a); 587 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 588 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 589 scsc = pciide_pci_read(pc, pa, 0x8a); 590 if ((scsc & 0x30) == 0) 591 drvp->UDMA_mode = 5; 592 } 593 mode |= 0x03 << (drive * 4); 594 off = 0xac + chp->channel * 16 + drive * 2; 595 val = pciide_pci_read(pc, pa, off) & ~0x3f; 596 if (scsc & 0x30) 597 val |= udma2_tbl[drvp->UDMA_mode]; 598 else 599 val |= udma_tbl[drvp->UDMA_mode]; 600 pciide_pci_write(pc, pa, off, val); 601 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 602 } else if (drvp->drive_flags & DRIVE_DMA) { 603 mode |= 0x02 << (drive * 4); 604 off = 0xa8 + chp->channel * 16 + drive * 2; 605 val = dma_tbl[drvp->DMA_mode]; 606 pciide_pci_write(pc, pa, off, val & 0xff); 607 pciide_pci_write(pc, pa, off, val >> 8); 608 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 609 } else { 610 mode |= 0x01 << (drive * 4); 611 off = 0xa4 + chp->channel * 16 + drive * 2; 612 val = pio_tbl[drvp->PIO_mode]; 613 pciide_pci_write(pc, pa, off, val & 0xff); 614 pciide_pci_write(pc, pa, off, val >> 8); 615 } 616 } 617 618 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 619 if (idedma_ctl != 0) { 620 /* Add software bits in status register */ 621 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 622 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 623 idedma_ctl); 624 } 625 } 626 627 static void 628 cmd3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 629 { 630 struct pciide_channel *cp; 631 bus_size_t cmdsize, ctlsize; 632 pcireg_t interface; 633 int channel; 634 635 if (pciide_chipen(sc, pa) == 0) 636 return; 637 638 aprint_normal("%s: bus-master DMA support present", 639 sc->sc_wdcdev.sc_dev.dv_xname); 640 pciide_mapreg_dma(sc, pa); 641 aprint_normal("\n"); 642 643 /* 644 * Rev. <= 0x01 of the 3112 have a bug that can cause data 645 * corruption if DMA transfers cross an 8K boundary. This is 646 * apparently hard to tickle, but we'll go ahead and play it 647 * safe. 648 */ 649 if (PCI_REVISION(pa->pa_class) <= 0x01) { 650 sc->sc_dma_maxsegsz = 8192; 651 sc->sc_dma_boundary = 8192; 652 } 653 654 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 655 WDC_CAPABILITY_MODE; 656 sc->sc_wdcdev.PIO_cap = 4; 657 if (sc->sc_dma_ok) { 658 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 659 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 660 sc->sc_wdcdev.irqack = pciide_irqack; 661 sc->sc_wdcdev.DMA_cap = 2; 662 sc->sc_wdcdev.UDMA_cap = 6; 663 } 664 sc->sc_wdcdev.set_modes = cmd3112_setup_channel; 665 666 sc->sc_wdcdev.channels = sc->wdc_chanarray; 667 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 668 669 /* 670 * The 3112 can be told to identify as a RAID controller. 671 * In this case, we have to fake interface 672 */ 673 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 674 interface = PCI_INTERFACE(pa->pa_class); 675 } else { 676 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 677 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 678 } 679 680 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 681 cp = &sc->pciide_channels[channel]; 682 if (pciide_chansetup(sc, channel, interface) == 0) 683 continue; 684 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 685 pciide_pci_intr); 686 } 687 } 688 689 static void 690 cmd3112_setup_channel(struct channel_softc *chp) 691 { 692 struct ata_drive_datas *drvp; 693 int drive; 694 u_int32_t idedma_ctl, dtm; 695 struct pciide_channel *cp = (struct pciide_channel*)chp; 696 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 697 698 /* setup DMA if needed */ 699 pciide_channel_dma_setup(cp); 700 701 idedma_ctl = 0; 702 dtm = 0; 703 704 for (drive = 0; drive < 2; drive++) { 705 drvp = &chp->ch_drive[drive]; 706 /* If no drive, skip */ 707 if ((drvp->drive_flags & DRIVE) == 0) 708 continue; 709 if (drvp->drive_flags & DRIVE_UDMA) { 710 /* use Ultra/DMA */ 711 drvp->drive_flags &= ~DRIVE_DMA; 712 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 713 dtm |= DTM_IDEx_DMA; 714 } else if (drvp->drive_flags & DRIVE_DMA) { 715 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 716 dtm |= DTM_IDEx_DMA; 717 } else { 718 dtm |= DTM_IDEx_PIO; 719 } 720 } 721 722 /* 723 * Nothing to do to setup modes; it is meaningless in S-ATA 724 * (but many S-ATA drives still want to get the SET_FEATURE 725 * command). 726 */ 727 if (idedma_ctl != 0) { 728 /* Add software bits in status register */ 729 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 730 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 731 idedma_ctl); 732 } 733 pci_conf_write(sc->sc_pc, sc->sc_tag, 734 chp->channel == 0 ? SII3112_DTM_IDE0 : SII3112_DTM_IDE1, dtm); 735 } 736
Indexes created Wed Sep 24 14:09:57 GMT 2025